Syntest Tool 使用說明. Speaker: Yu-Hsien Cheng Adviser: Kuen-Jong Lee. VLSI/CAD Training Course

Transcription

1 Syntest Tool 使用說明 Speaker: Yu-Hsien Cheng Adviser: Kuen-Jong Lee VLSI/CAD Training Course

2 Foreword Why testing? Class.2

3 Why Testing? Economics! Reduce test cost (enhance profit) Automatic test equipment (ATE) is extremely expensive Shorten time-to-market (time-to-volume) Market dominating or sharing Guarantee IC quality and reliability Rule of Ten: Defects detected in Cost Wafer Packaged chip Board 1 10 System Field Class.3

4 Outline Introduction to VLSI testing Fault simulation ATPG Scan + ATPG Boundary Scan Memory BIST Class.4

5 Basic concept of Testing Testing: To tell whether a circuit is good or bad Vdd /1 Related fields Verification: To verify the correctness of a design Diagnosis: To tell the faulty site Reliability: To tell whether a good system will work correctly or not after some time. Class.5

6 Difficulties in Testing Fault may occur anytime - Design - Process - Package - Field Fault may occur at any place Vdd VLSI circuit are large - Most problems encountered in testing are NP-complete I/O access is limited PCB SOC Class.6 Vss

7 How to do testing From designer s point of view: Circuit modeling Fault modeling Modeling Logic simulation Fault simulation Test generation Design for test Built-in self test ATPG Testable design Synthesis for testability Class.7

8 Fault Modeling Model the effects of physical defects Most commonly used fault model: Single stuck-at fault A B C D E F G A s-a-1 A s-a-0 E s-a-1 E s-a-0 B s-a-1 B s-a-0 F s-a-1 F s-a-0 C s-a-1 C s-a-0 G s-a-1 G s-a-0 14 faults D s-a-1 D s-a-0 Other fault models: - Break faults, Bridging faults, Transistor stuck-open faults, Transistor stuck-on faults, Delay faults Class.8

9 Faults, Errors and Failures Defect: An unintended difference between the implemented hardware and its intended design Fault: A representation of a defect at the abstracted function level May or may not cause a system failure Error: Manifestation of a fault that results in incorrect circuit (system) outputs or states Caused by faults Failure: Deviation of a circuit or system from its specified behavior Fails to do what it should do Caused by an error Class.9

10 Defect, Fault, and Error Example Defect: b short to ground Fault: signal b stuck-at 0 Error: a=1, b=1, output c=0 (correct output c=1) No Error when a=0 or b=0 a b c Class.10

11 Fault Coverage (FC) FC = # faults detected # faults in fault list Example: a b c 10 6 stuck-at faults ( a 0,a 1,b 0,b 1,c 0,c 1 ) Test faults detected FC {(0,0)} {(0,1)} {(1,1)} {(0,0),(1,1)} {(1,0),(0,1),(1,1)} c 1 a 1,c 1 a 0,b 0,c 0 a 0,b 0,c 0,c 1 all 16.67% 33.33% 50.00% 66.67% % Class.11

12 Outline Introduction to VLSI testing Logic & Fault simulation ATPG Scan + ATPG Boundary Scan Memory BIST Class.12

13 Logic simulation To determine how a good circuit should work Given input vectors, determine the normal circuit response A I C A B C E D F B E G C F C C1 C C2 B R B I R I F C DE C JE D H E Class.13

14 Fault simulation To determine the behavior of faulty circuits A 1 0 B 0 C 0 D E s.a.0 1/0 F 1 1/0 G Given a test vector, determine all faults that are detected by this test vector. Example: A B C Test vector (1 1) detects { a 0, b 0, c 1 } Class.14

15 Fault simulation (1/5) Tool : asicgen Ciucuit : ISCAS85 c17 Class.15

16 Fault simulation (2/5) Steps (1) :\>mkdir designs 在 UNIX 下建好將來會用到的子目錄 ( 注意不要打成 design) (2) :\>vlogin c17.v opath designs 將 c17.v 轉成 SYNTEST 資料格式的 c17.sdb, 並存於 -opath 所指定的 designs 子目錄下 (3) :\>expin opath designs c17 把 c17.sdb 經由 link 與 flatten 後在 designs 子目錄下產生 c17.x.sdb 及 c17.c.sdb, 這兩個檔案是我們在做 fault simulation 時所需要的電路資料 Class.16

17 Fault simulation (3/5) (4) :\>asicgen c17 fsim stm_file c17.stm 該程式會自動去找同一目錄下的 c17.stm 作為 fault simulation pattern < 執行結果 > 產生 c17.rpt c17.udt c17.hdt 等檔案 c17.rpt 內含 fault coverage 及一些執行訊息, 可用文書編輯軟體觀看其內容 Class.17

18 Fault simulation (4/5) Class.18

19 Fault simulation (5/5) 可以指名特定的 faults 做 fault simulation (5) :\>asicgen c17 fsim flt test.flt -stm_file c17.stm 程式會對 -flt 指定的 test.flt 中所列出的 faults 去做 simulation( 一樣是依據 c17.stm 中所列的 patterns) test.flt 內容如右 : Z 代表輸入,I0,I1, 代表輸入 Class.19

20 Outline Introduction to VLSI testing Logic & Fault simulation ATPG Scan + ATPG Boundary Scan Memory BIST Class.20

21 Test generation Given a fault, identify a test to detect this fault Example: A B C /0 To detect D s-a-0, D must be set to 1. Thus A=B=1. E To propagate fault effect to the primary output E must be 1. Thus C must be 0. Test vector: A=1, B=1, C=0 1 D 1/0 F Class.21

22 Automatic Test Pattern Generation ATPG: Given a circuit, identify a set of test vectors to detect all faults under consideration. Input circuit Form fault list More faults? Yes No Exit Fault dropping Select a fault Test generation Fault simulation Class.22

23 ATPG (1/6) Tool : asicgen Circuit : ISCAS85 c17 (combinational) Steps (1) 同 fault simulation 的前 3 步, 將 c17.v 轉成 syntest 能處理的資料型態 (2) :\>asicgen c17 以 combinational ATPG algorithm 來產生 patterns 產生 c17.tp 即為 c17 所需的 pattern Class.23

24 ATPG (2/6) Class.24

25 ATPG (3/6) C17.tp 是 ATPG 所產生的 test patterns. Class.25

26 ATPG (4/6) (3) :\>tpout c17 vlog 將 c17.tp 轉成 Verilog 的 textfixture file-c17.drv.v (4) :\>verilog c17.drv.v c17.v 用 Verilog 來驗證產生的 pattern 是否有效 Class.26

27 ATPG (5/6) Circuit : 4-bits counter (sequential) Steps (1) :\>mkdir designs lib (2) :\>vlogin counter_syn.v -define SYNTEST_TS -opath designs -lib sti_tsmc_artisan_18.v lib sti_tsmc_artisan_18.v 會把 sti_tsmc_artisan_18.v 等檔案的內容轉成 SYNTEST database 格式並存於 lib 子目錄中 因為 counter_syn.v 中內含一些 gates 為 standard cells, 而這些 cells 的相關資訊定義在 sti_tsmc_artisan_18.v 中, 所以我們才需要加上這個選項 Class.27

28 ATPG (6/6) (3) :\>expin counter (4) :\>asicgen counter non_scan 使用 sequential ATPG algorithm 來產生 pattern Class.28

29 Outline Introduction to VLSI testing Logic & Fault simulation ATPG Scan + ATPG Boundary Scan Memory BIST Class.29

30 Scan Design Original design Modified design PIs POs PIs POs Combinational logic Combinational logic FF FF SFF SFF SO FF Class.30 T/N SI SFF

31 Scan + ATPG (1/3) Tool : scansel scansyn asicgen Circuit : 4-bits counter Steps (full scan) (1) :\>mkdir designs lib fscan (2) :\> vlogin counter_syn.v -define SYNTEST_TS - opath designs -lib sti_tsmc_artisan_18.v (3) :\>expin counter (4) :\>scansel counter -fscan -fscan 表示 full-scan, 會選取電路中所有的 sequential elements 當成將要轉成 scan cell 的對象 Class.31

32 Scan + ATPG (2/3) 在做 Scan Synthesis 時需要準備兩個檔案 18_tsmc_artiasn.map: 定義 Flip-Flop 與 scan cells 之間轉換的關係 counter.dft: 有關 scan 的設定, 在 tutorial 會給個 template scansel counter fscan 當沒有指定 scan chain 數目時會當成一條, 可以透過 scan_chain #num 來設定 scan chain 數目 scansel counter fscan scan_chain 2: 代表有兩條 scan chain Class.32

33 Scan + ATPG (3/3) (5) :\>scansyn counter -fscan (6) :\>lsdb counter_s0 verilog hierarchy timescale o counter_s0.v 輸出 scan 後的電路 -verilog 表示將會存成 Verilog file;-hierarchy 表示會把電路各階層都存入檔案 ;- timescale 會在檔案中加入 :`timescale 1ns/10ps 指出我們日後模擬所用的時間單位 ;-o counter_s0.v 將會把電路存為 counter_s0.v 之檔名 (7) :\>asicgen counter_s0 -post_fscan -o fscan/counter_s0 -post_fscan: 已加了 full-scan;-o fscan/counter_s0 意指 ATPG 所產生的檔案會存於 fscan 子目錄下以 counter_s0 開頭的檔案中 Class.33

34 Outline Introduction to VLSI testing Logic & Fault simulation ATPG Scan + ATPG Boundary Scan Memory BIST Class.34

35 Objectives for Boundary Scan Standards for board level testing can be used to test 1. Chips 2. Chip interconnections 3. Modules 4. Module interconnections 5. Subsystems 6. Systems 7. Multi-Chip Modules Class.35

36 Boundary Scan I/O Pad Boundary scan cell Boundary scan path TRST* TDI Sout APPLICATION LOGIC TMS Misc. registers TCK TDO T A P M U X Instruction register Bypass register Sin BIST register Scan register TRST*:Test rest (Optional) TDI: Test data input TD0: Test data output TCK: Test clock TMS: Test mode select Class.36

37 Boundary Scan (Cont.) TRST* TRST* TDI TMS TCK TDO T A P M U X Misc. registers Instruction register Bypass register Sout Sin APPLICATION LOGIC BIST register Scan register TDI TMS TCK TDO T A P M U X Misc. registers Instruction register Bypass register Sout Sin APPLICATION LOGIC BIST register Scan register TRST* TRST* TDI TMS TCK TDO T A P M U X Misc. registers Instruction register Bypass register Sout Sin APPLICATION LOGIC BIST register Scan register TDI TMS TCK TDO T A P M U X Misc. registers Instruction register Bypass register Sout Sin APPLICATION LOGIC BIST register Scan register Class.37

38 Boundary Scan (1/6) Tool : bscansyn bscan2bsdl bscanvec Circuit : ISCAS85 c17 Steps (1) :\>mkdir lib designs (2) :\>vlogin c17.v opath designs lib pad.v bc.v pad.v, bc.v 內含 boundary scan cell 及 pad 的定義 (3) :\>expin c17 cellonly -cellonly: 只產生 c17.c.sdb, 沒有產生 c17.x.sdb; 這是因為 boundary scan 只需.c.sdb 檔即可 Class.38

39 Boundary Scan (2/6) (4) :\>bscansyn c17 add_tap add_pad -add_tap: 加入 tap controller 與 boundary scan cells -add_pad: 對每個 I/O port 加入 pad 在做 bscansyn 時, 需要另外三個檔案 : c17.pin c17.lib c17.bsc c17.pin: 記錄著 c17 電路的 I/O pins c17.lib: 包含 TAP controller boundary scan cell 和 pad cell 的設定 17.bsc: 是 boundary scan 的設定檔 * 如果使用不同的電路需要修改.pin 檔 此外也需要修改.bsc 檔裡面所設定讀取的.pin 檔名 Class.39

40 Boundary Scan (3/6) (4) 執行後產生以下檔案 c17.bsyn.rpt: file containing processing messages and design statistics c17_tap.v: RTL Verilog model of the added TAP controller c17.bso: a pin description file reporting detailed information of all the boundary scan cells added into the design. This can serve as useful debug information. c17_jtag.v: 加了 boundary scan chain 的 c17 電路 Class.40

41 Boundary Scan (4/6) (5) :\>ln s c17.bsc c17_jtag.bsc (6) :\>ln s c17.lib c17_jtag.lib (7) :\>bscan2bsdl c17_jtag (5)~(7) 產生 BSDL(Boundary Scan Description Language) 檔 輸出 BSDL 檔為 :c17_jtag.bsd 輸出 c17_jtag.int, 該檔記錄 c17_jtag 的 port list 執行過程記錄在 c17_jtag.bsdl.rpt Class.41

42 Boundary Scan (5/6) (8) :\>bscanvec c17_jtag interface c17_jtag.int 產生 test patterns -interface c17_jtag.int 是告訴 tool: 電路的 port order 是依據 c17_jtag.int 檔 (9) :\>tpout c17_jtag 輸出 Verilog test fixture (10) :\>verilog c17_jtag.drv.v c17_jtag.v c17_tap.v bc.v pad.v 模擬 boundary scan 的基本 instructions Class.42

43 Boundary Scan (6/6) Class.43

44 Outline Introduction to VLSI testing Logic & Fault simulation ATPG Scan + ATPG Boundary Scan Memory BIST Class.44

45 Built-In-Self Test (BIST) Places the job of device testing inside the device itself Generates its own stimulus and analyzes its own response from system mux circuit under test to system pattern generator BIST Controller Response Analyzer good/fail biston bistdone Class.45

46 Memory BIST Architecture Before After di addr wen Memory Module data sys_di sys_addr sys_wen clk hold_l rst_l test_h si se Memory Module data q so Class.46

47 Memory BIST Architecture (Cont.) sys_addr sys_d isys_wen rst_l clk hold_l test_h Algorithm-Based Pattern Generator di addr wen Memory Module compress_hclk rst si se data Compressor q so BIST Circuitry Class.47

48 Memory BIST (1/7) Tool : srambist Circuit : r2w1mem.mdf srambist 無法直接讀入 Verilog file, 我們必須依照已知的 Verilog 檔案來定義 r2w1mem.mdf 檔 Class.48

49 Memory BIST (2/7) r2w1mem.mdf 內容 Class.49

50 Memory BIST (3/7) Class.50

51 Memory BIST (4/7) Aaddr Baddr waddr dain r2w1mem 4 4 Aout Bout wrenable Class.51

52 Memory BIST (5/7) 定義 memory BIST 使用的 algorithm (march.bcf) Class.52

53 Memory BIST (6/7) Steps (1) :\>srambist r2w1mem bcf_file march.bcf algorithm march_cp 產生 memory 的 BIST 電路 srambist 會去讀 r2w1mem.mdf, 把它當成要產生 BIST 電路的目標 memory model -bcf_file 後面接.bcf 的名稱 ;- algorithm 後面接我們要用的 algorithm 名字 r2w1mem_top.v - Verilog BIST TOP MODULE file r2w1mem_rb.v - Verilog BIST CONTROLLER file r2w1mem_wrapper.v - Verilog WRAPPER file r2w1mem_sim.v - Verilog SRAM BIST testbench file r2w1mem.scp - Synopsys Synthesis Script file r2w1mem.bist.rpt - SRAM BIST report file Class.53

54 Memory BIST (7/7) (2) :\>verilog r2w1mem_top.v r2w1mem_sim.v r2w1mem_rb.v r2w1mem.v r2w1mem_wrapper.v Class.54