Chapter 2 (Part 2) Instructions: Language of the Computer

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1 Chapter 2 (Part 2) Instructions: Language of the Computer 陳瑞奇 (J.C. Chen) 亞洲大學資訊工程學系 Adapted from class notes by Prof. C.T. King, NTHU, Prof. M.J. Irwin, PSU and Prof. D. Patterson, UCB Logical Operations Fig. 2.8, p.87 ( 頁 87) Instructions for bitwise manipulation Operation C Java MIPS Shift left << << sll Shift right >> >>> srl Bitwise AND & & and, andi Bitwise OR or, ori Bitwise NOT ~ ~ nor 2.6 Logical Operations Useful for extracting and inserting groups of bits in a word 位元運算子 關係運算子 && 2

2 shift right logically srl $s1, $s2, 8 sll $s1, $s2, 8 shift left logically 4 Shift left logical (sll) p.88 ( 頁 88)? Example: R op rs rt rd shamt funct I op rs rt 16 bit address/constant sll $t2, $s0, 4 Instruction Format (R-format): Why not I-format? op rs rt rd shamt funct <32 5

3 srl $s1, $s2, 32? = add $s1, $zero, $zero >31 bits 6 Shift left logical (sll) p.88 ( 頁 88) Example: sll $t2, $s0, 4 Instruction Format (R-format): R-type op rs rt rd shamt funct

4 NOT Operations Useful to invert bits in a word Change 0 to 1, and 1 to 0 MIPS has NOR 3-operand instruction a NOR b == NOT ( a OR b ) not $t0, $t1? nor $t0, $t1, $zero $t1 X Register 0: always read as zero $t nor $t0, $t1, $t1 10 Variety of Logic Gates 11

5 Logical Operations (cont.) Fig. 2.1, p.64 ( 頁 62) $zero Not Shifts Instructions for Making Decisions Decision making A computer vs. a simple calculator: Decision making instructions alter the control flow, i.e., change the "next" instruction to be executed MIPS conditional branch instructions (I-format): beq rs, rt, L1 if (rs == rt) branch to instruction labeled L1; bne rs, rt, L1 if (rs!= rt) branch to instruction labeled L1; j L1 (J-format) unconditional jump to instruction labeled L1? 13

6 Compiling If Statements p.91 ( 頁 91) Example: f $s0, g $s1, h $s2, i $s3, j $s4 if (i==j) f=g+h; else f=g-h; bne $s3, $s4, Else add $s0, $s1, $s2 j Exit Else: sub $s0, $s1, $s2 Exit:... Assembler calculates addresses Fig Supporting Procedures in Computer Hardware MIPS procedure call instruction (jump-and-link): jal ProcedureAddress #jump and link Saves PC+4 in register $ra to have a link to the next instruction for the procedure return PC = Program Counter = Instruction Address Register = IAR Source: 27

7 2.8 Supporting Procedures in Computer Hardware MIPS procedure call instruction (jump-and-link): jal ProcedureAddress #jump and link R op rs rt rd shamt funct? X I op rs rt 16 bit address/constant Machine format (J-format): op 26 bit address Supporting Procedures in Computer Hardware MIPS procedure call instruction (jump-and-link): jal ProcedureAddress #jump and link Saves PC+4 in register $ra to have a link to the next instruction for the procedure return Machine format (J-format): op 26 bit address Then can do procedure return with a jump register instruction jr $ra #return Instruction format (R-format): op rs funct

8 ? 30 Supporting Procedures (cont.) Convention in allocating its registers for procedure calling: $a0 - $a3: four argument registers $v0 - $v1: two value registers in which to return values $ra: one return address register (PC + 4) PC = Program Counter $v0 =? = Instruction Address Register = IAR Caller vs. Callee $a0 = n Procedure 33

9 Aside: Spilling Registers What if the callee needs more registers? What if the procedure is recursive? uses a stack a last-in-first-out queue in memory for passing additional values or saving (recursive) return address(es) high addr Push Pop Push top of stack $sp low addr Pop 34 Aside: Spilling Registers What if the callee needs more registers? What if the procedure is recursive? uses a stack a last-in-first-out queue in memory for passing additional values or saving (recursive) return address(es) high addr One of the general registers, $sp, is used to address the stack (which grows from high address to low address) add data onto the stack push Push top of stack $sp $sp = $sp 4 data on stack at new $sp low addr Pop remove data from the stack pop data from stack at $sp $sp = $sp

10 Stack Fig p.100( 頁 100) 38 Allocating Space for New Data on the Heap stack pointer? Heap: data structure, LV global pointer Constants Static v./array MIPS machine code program counter Fig The MIPS memory allocation for program and data p.120 ( 頁 117) 43

11 e.g., A = A + 5; B = B + 1; Small constants are used often in typical codec = C - 18; 2.9 MIPS Immediate Instructions Possible approaches? put typical constants in memory and load them create hard-wired registers (like $zero) for constants like 1 have special instructions that contain constants! addi $sp, $sp, 4 #$sp = $sp + 4 Machine format (I format): op rs rt 16 bit immediate I format The constant is kept inside the instruction itself! Immediate format limits values to the range to Design Principle: Make the common case fast. 52 How About Larger Constants? p.107( 頁 108) We'd also like to be able to load a 32 bit constant into a register, for this we must use two instructions 數大便是美! 徐志摩 西湖記 addi $sp, $sp, 4? 數大 便是美, 碧綠的山坡前幾千隻綿羊, 挨成一片的雪絨, 是美 op rs rt 16 bit immediate I format 32 bits = 53

12 How About Larger Constants? p.107( 頁 108) We'd also like to be able to load a 32 bit constant into a register, for this we must use two instructions a new "load upper immediate" instruction lui $t0, Then must get the lower order bits right, use ori $t0, $t0, 大數 Addresses in Branches Instructions: bne $t4,$t5,label #Next instruction is at Label if $t4 $t5 beq $t4,$t5,label #Next instruction is at Label if $t4=$t5 Formats: I 64KB op rs rt 16 bit address Could specify a register (like lw and sw) and add it to address 256KB Word addressing offset (= byte addressing 18 bits) use Instruction Address Register (PC = program counter) most branches are local (principle of locality) 4GB 56

13 MIPS Control Flow Instructions MIPS conditional branch instructions: bne $s0, $s1, Lbl #go to Lbl if $s0 $s1 beq $s0, $s1, Lbl #go to Lbl if $s0=$s1 Instruction Format (I-format): op rs rt 16 bit offset PC How is the branch destination address specified? PC-relative addressing instruction address is the sum of the PC and a 16-bit constant contained within the instruction op rs rt offset sll 2 bits Program Counter (PC) Memory branch destination instruction 57 Specifying Branch Destinations op rs rt 16 bit offset 64KB Fetch PC = PC+4 sll 2 bits 256KB Exec Decode PC = PC+4 4GB 58

14 Other Control Flow Instructions MIPS also has an unconditional branch instruction or jump instruction: j label # go to label jal proc # call proc Instruction Format (J-format): op 26-bit address 4GB from the low order 26 bits of the jump instruction 26 4 PC 64MB MB Fetch new instruction Jump instructions just use high order bits of PC address boundaries of 256 MB 60 Branching Far Away What if the branch destination is further away than can be captured in 16 bits? The assembler comes to the rescue it inserts an unconditional jump to the branch target and inverts the condition beq $s0, $s1, L1 becomes > 16bits L2: bne $s0, $s1, L2 j L1 62

15 MIPS Operand Addressing Modes Register addressing operand is in a register op rs rt rd funct Register Base (displacement) addressing operand is at the memory location whose address is the sum of a register and a 16-bit constant contained within the instruction base register Register relative (indirect) with Pseudo-direct with 0($a0) word operand op rs rt offset Memory word or byte operand addr($zero) Immediate addressing operand is a 16-bit constant contained within the instruction op rs rt operand p.112 ( 頁 113) 63 MIPS Instruction Addressing Modes PC-relative addressing instruction address is the sum of the PC and a 16-bit constant contained within the instruction sll 2 bits op rs rt offset Program Counter (PC) Memory branch destination instruction Pseudo-direct addressing instruction address is the 26-bit constant contained within the instruction concatenated with the upper 4 bits of the PC op 4 bits jump address Program Counter (PC) sll 2 bits Memory jump destination instruction p.112 ( 頁 113) 64

16 Addressing Mode Summary Fig p.112 ( 頁 113) 半字組 字組 65 Decoding Machine Code p.113 ( 頁 115) A code dump 00af8020hex? (assembly language) op rs rt rd shamt funct How? add $s0, $a1, $t7 66

17 MIPS R3000 Instruction Set Architecture (ISA) Instruction Categories Computational Load/Store Jump and Branch Floating Point - coprocessor Memory Management Special Registers R0 - R31 PC HI LO 3 Instruction Formats: all 32 bits wide OP rs rt rd sa funct R format OP rs rt immediate I format OP jump target J format 67 MIPS Register Convention Fig. 2.14, p.105( 頁 106) Name Register Number Usage Preserve on call? $zero 0 constant 0 (hardware) n.a. $at 1 reserved for assembler n.a. $v0 - $v1 2-3 returned values no $a0 - $a3 4-7 arguments no $t0 - $t temporaries no $s0 - $s saved values yes $t8 - $t temporaries no $gp 28 global pointer yes $sp 29 stack pointer yes $fp 30 frame pointer yes $ra 31 return addr (hardware) yes $k0 - $k1 (26 27) are reserved for the operating system 68

18 MIPS instruction encoding p.114( 頁 114)Fig.2.17 op (31:26) (000) 1(001) 2(010) 3(011) 4(100) 5(101) 6(110) 7(111) 0(000) R-format Bltz/gez jump jump & link branch eq branch ne blez bgtz 1(001) add immediate addiu 2(010) TLB FlPt 3(011) set less than imm. sltiu andi ori xori load upper imm 4(100) load byte lh lwl load word 5(101) store byte 6(110) lwc0 lwc1 sh swl store word lbu lhu lwr swr 7(111) swc0 swc1 69 MIPS instruction encoding p.114( 頁 114)Fig.2.17 op (31:26) = (R-format), funct(5:0) 2-0 0(000) 1(001) 2(010) 3(011) 4(100) 5(101) 6(110) 7(111) 5-3 0(000) sll srl sra sllv srlv srav 1(001) jump reg. jalr syscal l 2(010) mfhi mthi mflo mtlo break 3(011) mult multu div divu 4(100) add addu subtract subu and or xor nor 5(101) set l.t. sltu 6(110) 7(111) p.115 ( 頁 115) Fig

19 Review: Section 2.5 Instructions, like registers and words of data, are 32 bits long Arithmetic Instruction Format (R format): add $t0, $s1, $s2 p.80 ( 頁 80) R-type op rs rt rd shamt funct op 6-bits opcode that specifies the operation rs 5-bits register file address of the first source operand rt 5-bits register file address of the second source operand rd 5-bits register file address of the result s destination shamt 5-bits shift amount (for shift instructions) funct 6-bits function code augmenting the opcode 71 Review: Section 2.5 p.80 ( 頁 80) Instructions, like registers and words of data, are also 32 bits long Example: add $t0, $s1, $s2 registers have numbers, $t0=8, $s1=17, $s2=18 R-type op rs rt rd shamt funct Machine Language Instruction Format: op rs rt rd shamt funct Machine Code( instruction) 72

20 Decoding Machine Code 00af8020(hex) 00af8020 (16) 0x00af8020 p.113 ( 頁 115) 00AF op rs rt rd shamt funct add $s0, $a1, $t7 73 Compiler 2.11 Translation and Startup Assembler Linker p.119 ( 頁 120) Fig O.S. Loader 81

21 2.16 ARM & MIPS Similarities ARM: the most popular embedded core Similar basic set of instructions to MIPS ARM MIPS Date announced Instruction size 32 bits 32 bits Address space 32-bit flat 32-bit flat Data alignment Aligned Aligned Data addressing modes 9 3 Registers bit bit Input/output Memory mapped p.135 ( 頁 138) Fig Memory mapped Real Stuff: ARM Instructions 2.19 MIPS (RISC) Design Principles Simplicity favors regularity fixed size instructions 32-bits small number of instruction formats opcode always the first 6 bits p.150 ( 頁 156) Good design demands good compromises three instruction formats Smaller is faster limited instruction set limited number of registers in register file limited number of addressing modes Make the common case fast arithmetic operands from the register file (load-store machine) allow instructions to contain immediate operands 90

22 CISC: Intel, AMD (x86 Overview) Complexity: Instructions from 1 to 17 bytes long one operand must act as both a source and destination one operand can come from memory complex addressing modes e.g., base or scaled index with 8 or 32 bit displacement 99 Homework Assignment #2 (Due in 2 weeks) 題號 ( 分數 %) 2.3 (10%) 對以下的 C 敘述句, 對應的 MIPS 組合碼是什麼? 假設變數 f g h i 及 j 分別被指定存於暫存器 $s0 $s1 $s2 $s3 及 $s4 中 又假設陣列 A 及 B 的基底位址分別存於暫存器 $s6 及 $s7 中 B[8] = A[i - j]; 2.9 (10%) 將下列 C 碼翻譯成 MIPS 碼 假設變數 f g h i 及 j 分別被指定存於暫存器 $s0 $s1 $s2 $s3 及 $s4 中 又假設陣列 A 及 B 的基底位址分別存於暫存器 $s6 及 $s7 中 在假設陣列 A 及 B 的元素是 4 位元的字組 : B[8] = A[i] A[j]; 103

23 HW# 假設暫存器 $s0 與 $s1 分別存有值 0x 與 0xD (5%) 執行下列組合指令後,$t0 的值為何? add $t0, $s0, $s (5%) 在 $t0 中的值試所欲的值 或是已有滿溢發生? 2.14 (10%) 對於下列二進制數字 : , 寫出他的組合語言指令類型以及指令 2.15 (10%) 對下列指令 :sw $t1,32($t2), 寫出它的指令類型以及十六進制表示法 2.16 (10%) 對下列 MIPS 欄位 :op=0,rs=3,rt=2,rd=3, shamt=0,funct=34, 寫出它的指令類型 組合語言類型 以及二進制表示法 104 HW# (10%) 對下列 MIPS 欄位 :op=0x23,rs=1,rt=2, const=0x4, 寫出它的指令類型 組合語言類型, 以及二進制表示法 2.21 (10%) 寫出可用於實現下列假指令的最少的 MIPS 指令 : not $t1, $t2 //bit-wise invert 2.24 (10%) 假設程式計數器 (PC) 設定為 0x 是否可能以 MIPS 組合指令跳躍 (j) 將 PC 設為地址 0x ? 是否可能以 MIPS 組合指令若相等分支 (beq) 將 PC 設為該相同地址? 2.39 (10%) 寫出能產生 32 位元常數 並將該值存於暫存器 $t1 中的 MIPS 組合語言碼 105