Chapter 8 FPGA Basics

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1 Chapter 8 FPGA Basics NCHU EE Yin-Tsung Hwang YT Hwang VLSI SP 1 What are PLs? YT Hwang VLSI SP 2

Programmable Logic evices A pre-fabricated ASIC capable of performing any logic subject to user programming compromise between the semi-custom ASICs and standard components a collection of logic

2 Programmable Logic evices A pre-fabricated ASIC capable of performing any logic subject to user programming compromise between the semi-custom ASICs and standard components a collection of logic elements placed in a programmable interconnection framework fast design turn around time field programmable EPROM, E 2 PROM, Flash, SRAM based YT Hwang VLSI SP 3 PL Programmability (1) programmable combinational logic PT-based, (look-up table) PT-based building block 2-level logic, high fan-in -based building block 4-5 inputs, fine-grain arch. ROM like YT Hwang VLSI SP 4

3 PL Programmability (2) programmable register register type, register control YT Hwang VLSI SP 5 PL Programmability (3) programmable interconnect routing resources including switching elements, local/global lines, clock buffers YT Hwang VLSI SP 6

4 PL Programmability (4) programmable I/O direction, I/O register, 3-state, slew rate YT Hwang VLSI SP 7 Field Programmability can verify designs at any time by configuring the FPGA/ CPL devices on board via the download cable or hardware programmer YT Hwang VLSI SP 8

5 PL Classifications General classification Simple programmable logic device (SPL) Complex programmable logic device (CPL) Field programmable gate array (FPGA) Classification by programming technology Fuse, anti-fuse (OTP) EPROM, EEPROM, Flash (multiple programming) SRAM (volatile, need configuration when power up) Classification by routing structures Segmented (incremental) routing Continuous routing YT Hwang VLSI SP 9 Simple PL Programmable AN/OR array Sum-Of-Product (SOP) to implement Boolean functions facilitated with FFs, output macros, and feedback path foldback architecture low density, low cost, fixed delay examples: PAL, GAL, PEEL, FPLA YT Hwang VLSI SP 10

6 PAL Architecture YT Hwang VLSI SP 11 Complex PL architecture YT Hwang VLSI SP 12

7 Field Programmable Gate Array architecture originates from gate array 2- array of programmable logic blocks (cells) programmable / incremental interconnect less predictable timing, place &routing is crucial matrix based architecture Xilinx XC4000, Spartan, Virtex, uicklogic Row based architecture Actel ACT families Continuous interconnect architecture Altera Flex 8K/10K, APEX YT Hwang VLSI SP 13 Generic FPGA logic cell 16X1 Mcell Primary Inputs Carry logic Look-Up Table (RAM) Macrocell I/O cells Logic cell YT Hwang VLSI SP 14

8 Continuous v.s. Segmented CROSS BAR continuous segmented YT Hwang VLSI SP 15 Rapid Prototyping & System Verification To see is to believe The ASIC respin cost is too high Verification at lower speed YT Hwang VLSI SP 16

transistors in 70nm process High logic gate count Up to millions of logic gates Large on chip memory From several K bits

9 Low cost solution of FPGAs Hardcopy technology Reduced die area Only two mask layer cost YT Hwang VLSI SP 17 Latest FPGA Features Advanced process For example, Xilinx Spartan III use 90nm process Next generation Virtex FPGA will contain 1G transistors in 70nm process High logic gate count Up to millions of logic gates Large on chip memory From several K bits to several M bits On chip processor ARM 7/9, PowerPC On chip multiplier/sp High speed I/O Up to 3.125Gbps YT Hwang VLSI SP 18

10 What s inside? Altera Excalibur ual-port RAM Single-Port RAM ARM922T Core Processor + Memory + 1,000,000 plus logic capacity PL Area for Customer esign YT Hwang VLSI SP 19 SoPC example Stripe PRAM ual-port RAM Interface AMBA Bus Interface Ethernet Controller Media Independent Interface SRAM (Single Port) Logic AMBA Bus Interface Nios CPU ATM Cell Processor 33-MHz Utopia-2 PHY Manager SRAM Interface Flash Interface PLLs SRAM Controller EBI Bridge Bridge ARM Processor Master Port Slave Port AMBA Bus Interface AMBA Bus Interface PCI Controller Custom Logic PCI YT Hwang VLSI SP 20

FPGA Architecture Overview YT Hwang VLSI SP 21 The Spartan-IIE Solution More Than Just Silicon I/O Connectivity SelectIO TM Technology Support major I/O standards Memory Resources SRL16 registers

11 FPGA Architecture Overview YT Hwang VLSI SP 21 The Spartan-IIE Solution More Than Just Silicon I/O Connectivity SelectIO TM Technology Support major I/O standards Memory Resources SRL16 registers istributed Memory Block Memory External Memory I O B I O B LL R A M R A M CLB CLB R A M CLB IOB... IOB... CLB LL R A M I O B I O B LL IOB IOB LL Logic & Routing Flexible logic implementation Vector Based Routing Internal 3-State bussing System Clock Management igital elay Lock Loops (LLs) YT Hwang VLSI SP 22

12 CLB Structure COUT COUT G4 G3 G2 G1 F5IN BY SR F4 F3 F2 F1 Look-Up Table O Look-Up Table O Carry & Control Logic Carry & Control Logic YB Y XB X S CK EC R S CK EC R G4 G3 G2 G1 F5IN BY SR F4 F3 F2 F1 Look-Up Table O Look-Up Table O Carry & Control Logic Carry & Control Logic YB Y XB X S CK EC R S CK EC R CIN CLK CE SLICE CIN CLK CE SLICE Each slice has 2 -FF pairs with associated carry logic Two 3-state buffers (BUFT) associated with each CLB, accessible by all CLB outputs YT Hwang VLSI SP 23 CLB Slice Structure Each slice contains two sets of the following: Four-input Any 4-input logic function Or 16-bit x 1 sync RAM Or 16-bit shift register Carry & Control Fast arithmetic logic Multiplier logic Multiplexer logic Storage element Latch or flip-flop Set and reset True or inverted inputs Sync. or async. control

up to 19 inputs edicated muxes are faster

13 edicated Expansion Multiplexers MUXF5 combines 2 s to create 4x1 multiplexer Or any 5-input function (5) Or selected functions up to 9 inputs MUXF6 combines 2 slices to form 8x1 multiplexer Or any 6-input function (6) Or selected functions up to 19 inputs edicated muxes are faster and more space efficient CLB Slice Slice MUXF5 MUXF5 MUXF6 YT Hwang VLSI SP 26

14 istributed RAM CLB configurable as istributed RAM A equals 16x1 RAM Implements Single and ual- Ports Cascade s to increase RAM size Synchronous write Synchronous/Asynchronous read Accompanying flip-flops used for synchronous read RAM32X1S WE WCLK A0 A1 A2 A3 A4 or = = O RAM16X1S WE WCLK A0 A1 A2 A3 RAM16X2S 0 1 WE WCLK A0 A1 A2 A3 or O0 O1 O RAM16X1 WE WCLK A0 SPO A1 A2 A3 PRA0 PO PRA1 PRA2 PRA3 YT Hwang VLSI SP 27 Shift Register Each can be configured as shift register Serial in, serial out ynamically addressable delay up to 16 cycles For programmable pipeline Cascade for greater cycle delays Use CLB flip-flops to add depth IN CE CLK = CE CE CE CE OUT EPTH[3:0] YT Hwang VLSI SP 28

15 Shift Register Cycles Operation A Operation B 4 Cycles 8 Cycles Operation C 3 Cycles 64 Register-rich FPGA 3 Cycles 9-Cycle imbalance Allows for addition of pipeline stages to increase throughput ata paths must be balanced to keep desired functionality YT Hwang VLSI SP 29 Shift Register 12 Cycles 64 Operation A Operation B 4 Cycles 8 Cycles Operation C Pipeline 64 3 Cycles 9 Cycles as shift register Used to add pipeline stages Increase overall register count 16 bit shift register per 64 bit shift register per CLB 12 Cycles Paths statically balanced YT Hwang VLSI SP 30

16 CLB Arithmetic Logic edicated carry logic Provides high performance for counters & arithmetic functions iscrete XOR component for single level sum completion Two separate carry chains in CLB allow for 3 operand functions Single-level Sum Can also be used to cascade s for wide-input logic functions YT Hwang VLSI SP 31 3 Operand Adder Function COUT COUT B1 B0 Look-Up Table Carry & Control Logic PARTIAL1 Look-Up Table O Carry & Control Logic SUM1 A1 A0 Look-Up Table Carry & Control Logic PARTIAL0 Look-Up Table Carry & Control Logic SUM0 C1 C0 CIN SLICE0 CLB CIN SLICE1 A, B, C are two-bits wide SUM = A + B + C or PARTIAL + C, where PARTIAL = A + B Implementation First 2-operand sum A+B is performed in Slice 0 Second 2-operand sum PARTIAL + C is performed in Slice 1 Fast local feedback connection within the CLB Very small delay for on PARTIAL YT Hwang VLSI SP 32

17 Carry Logic for Wide Input Functions Higher performance Efficient resource utilization Common applications Wide input decoding Comparators HL design entry can be inferred MUXCY must be instantiated YT Hwang VLSI SP Input AN Function L K J I H G F E C B A 3 INIT= INIT= INIT= MUXCY MUXCY MUXCY Vcc Output 4-Input AN Truth Table Inputs(ABC) Output(Z) Output(HEX) Utilization 3 s and 3 MUXCYs As opposed to 4 s Performance 1 logic level As opposed to 2 logic levels YT Hwang VLSI SP 34

18 12- Input OR Function L K J I H G F E C B A 3 INIT= INIT= INIT= MUXCY MUXCY MUXCY Output Vcc Vcc Vcc 4-Input NOR Truth Table Inputs(ABC) Output(Z) Output(HEX) Utilization 3 s and 3 MUXCYs As opposed to 4 s Performance 1 logic level As opposed to 2 logic levels YT Hwang VLSI SP 35 edicated CLB Multiplier Logic A CY_MUX CO S I CI CY_XOR MULT_AN edicated AN gate A x B B edicated AN gate Highly efficient Shift & Add implementation For a 16x16 Multiplier 30% reduction in area and one less logic level YT Hwang VLSI SP 36

19 Spartan-IIE Memory Hierarchy C CL E K A0 A1 A2 A3 Shift Register 16 registers, 1 Compact & fast CL K A0 A1 A2 A3 SRL16E SRL16 Pipelining Buffers Bytes istributed RAM Single-port ual port Cascadable 16x1 SP Coefficients Small FIFOs Scratch Pad Block RAMs 4Kbit blocks True dual-port Port A 4Kx1 2Kx2 1Kx4 512x8 256x16 Block RAM Port B Cache Tag memory Large FIFOs Packet buffers Video line buffers Kilobytes High-Performance External Memory Interfaces R I/O SSTL, HSTL, CTT SRAM SGRAM PB SRAM R SRAM ZBT SRAM R SRAM Collaboration with memory vendors IT, Cypress, Micron, NEC, Samsung, Toshiba... YT Hwang VLSI SP 37 istributed RAM CLB configurable as istributed RAM A equals 16x1 RAM Implements single and dual ports Cascade s to increase RAM size Synchronous write Synchronous/Asynchronous read Accompanying flip-flops used for synchronous read RAM32X1S WE WCLK A0 A1 A2 A3 A4 or = = O RAM16X1S WE WCLK A0 A1 A2 A3 RAM16X2S 0 1 WE WCLK A0 A1 A2 A3 O0 O1 or O RAM16X1 WE WCLK A0 SPO A1 A2 A3 PRA0 PO PRA1 PRA2 PRA3 YT Hwang VLSI SP 38

20 SRL-16 and SRL-16E CLK A0 A1 A2 A3 SRL16 IN CE CLK CE CE 16-bit Shift Register Look-Up-Table CE CLK A0 A1 A2 A3 SRL16E CLB Slice Slice CE CE OUT 16-bit Shift Register Look-Up-Table with Clock Enable AR[3:0] YT Hwang VLSI SP 39 istributed RAM ual-port Implementation 2 s equal 16x1 dual-port RAM A Port B Port Uses A[3:0] address Write and read Uses PA[3:0] address Read only Excellent for FIFOs, scratch pads. A[3:0] WE WCLK RAM16X1 16 x 1 RAM 16 x 1 RAM SPO PA[3:0] PO YT Hwang VLSI SP 40

21 Block RAM Most efficient memory implementation edicated blocks of memory Ideal for most memory requirements 8 to 72 memory blocks 4096 bits per blocks Use multiple blocks for larger memories Port A Spartan-IIE True ual-port Block RAM Port B Block RAM Builds both single and true dual-port RAMs CORE Generator provides custom-sized block RAMs uickly generates optimized RAM implementation YT Hwang VLSI SP 41 Block RAM Configurable synchronous Block RAM Single-port RAM True dual-port RAM Two independent single-port RAMs Block count increases with FPGA size evice No. of Blocks Block RAM Bits XC2S50E 8 32,768 XC2S100E 10 40,960 XC2S150E 12 49,152 XC2S200E 14 57,344 XC2S300E 16 65,536 XC2S400E ,840 XC2S600E ,912 YT Hwang VLSI SP 42

22 Block RAM Flexible 4096-bit block Variable aspect ratio 4096 x x x x x 16 Increase memory depth or width by cascading blocks YT Hwang VLSI SP 43 Block RAM Single-Port Implementation Easy cascading of block RAMs Utilize variable aspect ratio for desired RAM size Example esired RAM size: 1024 x x x 4 = 1024 x 8 CORE Generator software Efficiently cascades RAM blocks uick custom RAM implementation ATA[7..4] ATA[3..0] 1024 X 8 RAM RAMB4_S4 WE EN RST O[3:0] CLK AR[9:0] I[3:0] RAMB4_S4 WE EN RST O[3:0] CLK AR[9:0] I[3:0] OUT[7..4] OUT[3..0] YT Hwang VLSI SP 44

23 ual-port Bus Flexibility Port A In 1K-Bit epth RAMB4_S4_S16 WEA ENA RSTA OA[3:0] CLKA ARA[9:0] IA[3:0] Port A Out 4-Bit Width WEB Port B In 256-Bit epth ENB RSTB CLKB ARB[7:0] OB[15:0] Port B Out 16-Bit Width IB[15:0] Each port can be configured with a different data bus width Provides easy data width conversion without any additional logic YT Hwang VLSI SP 45 Two Independent Single-Port RAMs Port A In 2K-Bit epth VCC, AR[10:0] RAMB4_S1_S1 WEA ENA RSTA OA[0] CLKA ARA[10:0] IA[0] Port A Out 1-Bit Width Port B In 2K-Bit epth GN, AR[10:0] WEB ENB RSTB CLKB ARB[10:0] IB[0] OB[0] Port B Out 1-Bit Width Added advantage of True ual- Port No wasted RAM Bits Can split a ual-port 4K RAM into two Single-Port 2K RAM Simultaneous independent access to each RAM To access the lower RAM Tie the MSB address bit to Logic Low To access the upper RAM Tie the MSB address bit to Logic High YT Hwang VLSI SP 46

24 CAM in Block RAM Content Addressable Memory (CAM) Storage array like a RAM Functionally opposite of a RAM uickly find the location of a particular stored value Output the address and toggle the MATCH line, if data match is found RAM A[9:0] ATA [7:0] 1024x8 CAM ATA[7:0] A [9:0] 1024x8 MATCH Used in telecommunications, networking, Ethernet, ATM switches Xilinx provides reference designs and application notes YT Hwang VLSI SP 47 System Interfaces -- SelectI/O LVS Voltage Standards 3.3V 2.5V 1.8V 1.5V Chip-to-Chip Interfaces LVPECL LVCMOS LVTTL 19 ifferent Standards Supported! Backplane Interfaces AGP GTL GTL+ PCI BLVS High-speed Memory Interfaces CTT HSTL SSTL w Supports multiple voltage and signal standards simultaneously w Eliminate costly bus transceivers YT Hwang VLSI SP 48

SelectI/O TM Standards Standard V REF V CCO Chip to Chip Interface LVTTL na 3.3 LVCMOS2 na 2.5 LVCMOS18 na 1.8 LVS na 2.5 LVPECL na 3.3 Backplane Interface PCI 33MHz 3.3V na 3.3 PCI 66MHz 3.3V na 3.3 GTL 0.

25 SelectI/O TM Standards Standard V REF V CCO Chip to Chip Interface LVTTL na 3.3 LVCMOS2 na 2.5 LVCMOS18 na 1.8 LVS na 2.5 LVPECL na 3.3 Backplane Interface PCI 33MHz 3.3V na 3.3 PCI 66MHz 3.3V na 3.3 GTL 0.80 na GTL na AGP-2X Bus LVS na 2.5 Memory Interface HSTL-I HSTL-III & IV SSTL3-I & II SSTL2-I & II CTT Output Input V CCO V CCO defines output voltage Internal Reference User I/O Pin V REF V REF defines input threshold reference voltage Available as user I/O when using internal reference YT Hwang VLSI SP 49 I/Os Separated into 8 Banks Bank 0 Bank 1 CLB GCLK3 Bank 7 I R... Bank 6 O B I O B LL A M R A M... CLB IOB GCLK1... IOB GCLK2... GCLK0 CLB CLB LL R A M R A M LL IOB IOB LL I O B I O B Bank 2 Bank 3 Banks 2 and 3 used during configuration IOB=I/O Blocks Bank 5 Bank 4 YT Hwang VLSI SP 50

26 I/O Signal Types I/O Signal Type Single-Ended ifferential LVCMOS HSTL SSTL LVTTL LVS Bus LVS LVPECL NOTE: Only the popular IO types shown here YT Hwang VLSI SP 51 Single Ended I/O Traditional means of data transfer ata is carried on a single line Bigger voltage swing between logic Low and High 3.3 V Logic High river Receiver 2 V ata Out ata In 0.8 V 1.2V swing Logic Low Single ended data transfer LVTTL input levels YT Hwang VLSI SP 52

Smaller voltage swing between logic Low and High Higher performance Lower power Lower noise 3.

27 SystemI/O Single-Ended I/O Standards Summary YT Hwang VLSI SP 53 ifferential I/O Latest means of data transfer One data bit is carried through two signal lines Voltage difference determines logic High or Low Smaller voltage swing between logic Low and High Higher performance Lower power Lower noise 3.3 V ata Out river Rt Receiver + - ata In 1.7 V 1.3 V 0.4V swing ifferential signal data transfer LVS Input levels YT Hwang VLSI SP 54

28 SelectI/O: ifferential I/O Types LVS (Low Voltage ifferential Signal) Unidirectional data transfer Bus LVS Bi-directional communication between 2 or more devices Can transmit and receive LVS signals through the same pins LVPECL (Low Voltage Positive Emitter Coupled Logic) Unidirectional data transfer Popular industry standard for fast clocking YT Hwang VLSI SP 55

Virtex-II Architecture

Virtex-II Architecture Block SelectRAM resource I/O Blocks (IOBs) edicated multipliers Programmable interconnect Configurable Logic Blocks (CLBs) Virtex -II architecture s core voltage operates at 1.5V