Digital Design: An Embedded Systems Approach Using VHDL

Transcription

1 Digital Design: An Embedded Systems Approach Using Chapter 5 Memories Portions of this work are from the book, Digital Design: An Embedded Systems Approach Using, by Peter J. Ashd, published by Morgan Kaufmann Publishers, Copyright 27 Elsevier Inc. All rights reserved. Geral Concepts A memory is an array of storage locations Each with a unique address Like a collection of registers, but with optimized implemtation Address is unsigned-binary coded n address bits 2 n locations All locations the same size 2 n m bit memory n 2 2 n m bits Digital Design Chapter 5 Memories 2

2 Memory Sizes Use power-of-2 multipliers Kilo (K): 2 =,24 3 Mega (M): 2 2 =,48,576 6 Giga (G): 2 3 =,73,74,824 9 Example 32K 32-bit memory Capacity =,25K = Mbit Requires 5 address bits Size is determined by application requiremts Digital Design Chapter 5 Memories 3 Basic Memory Operations a() a() a(n ) d_in() d_in() d_in(m ) d_out() d_out() d_out(m ) a inputs: unsigned address d_in and d_out Type depds on application Write operation =, = d_in value stored in location giv by address inputs Read operation =, = d_out driv with value of location giv by address inputs Idle: = Digital Design Chapter 5 Memories 4 2

3 Example: Audio Delay Unit System clock: MHz Audio samples: 8-bit signed, at 5kHz New sample arrives wh audio_in_ = Delay control: 8-bit unsigned ms to delay Output: audio_out_ = wh output ready 2µs audio_in s t s t+ audio_in_ audio_out s t d s t d+ audio_out_ Digital Design Chapter 5 Memories 5 Audio Delay Datapath count_ Q 4 delay addr_sel audio_in mem_ mem_ a d_in d_out 6 audio_out Max delay = 255ms Need to store = 2,75 samples Use a 6K 8-bit memory (4 address bits) Digital Design Chapter 5 Memories 6 3

4 Audio Delay Control Section Step : (idle state) audio_in_ = do nothing audio_in_ = ite memory using counter value as address Step 2: Read memory using subtracter output as address, incremt counter State audio_ in_ Next state addr_sel mem_ mem_ count_ audio_ out_ Step Step Step Step 2 Step 2 Step Digital Design Chapter 5 Memories 7 Wider Memories Memory componts have a fixed width E.g.,, 4, 8, 6,... Use memory componts in parallel to make a wider memory E.g, three 6K 6 componts for a 6K 48 memory a(3 ) d_in(5 ) d_in(3 6) d_in(47 32) a(3 ) d_in(5 ) d_out(5 ) a(3 ) d_in(5 ) d_out(5 ) a(3 ) d_in(5 ) d_out(5 ) d_out(5 ) d_out(3 6) d_out(47 32) Digital Design Chapter 5 Memories 8 4

5 More Locations To provide 2 n locations with 2 k -location componts Use 2 n /2 k componts Address A at offset A mod 2 k least-significant k bits of A in compont A/2 k most-significant n k bits of A decode to select compont 2 k 2 k 2 k k 2 2 k 2 2 k k 2 n 2 k 2 n 2 k + 2 n Digital Design Chapter 5 Memories 9 More Locations a(3 ) d_in(7 ) a(3 ) d_in(7 ) d_out(7 ) a(5 4) 2 3 a(3 ) d_in(7 ) d_out(7 ) Example: 64K 8 memory composed of 6K 8 componts a(3 ) d_in(7 ) d_out(7 ) a(3 ) 2 3 d_out(7 ) d_in(7 ) d_out(7 ) Digital Design Chapter 5 Memories 5

6 Tristate Drivers Allow multiple outputs to be connected together Only one active at a time Remaining outputs are high-impedance Both output transistors turned off Allow bidirectional input/output ports +V output +V +V +V Digital Design Chapter 5 Memories Memories with Tristate Ports During ite memory d drivers hi-z a(3 ) a(3 ) d(7 ) memory sses d During read selected memory drives d a(5 4) 2 3 a(3 ) d(7 ) Fewer pins and wires Reduced cost of PCB a(3 ) d(7 ) Usually not available within ASICs or FPGAs d(7 ) a(3 ) d(7 ) Digital Design Chapter 5 Memories 2 6

7 Memory Types Random-Access Memory (RAM) Can read and ite Static RAM (SRAM) Stores data so long as power is supplied Asynchronous SRAM: not clocked Synchronous SRAM (SSRAM): clocked Dynamic RAM (DRAM) Needs to be periodically refreshed Read-Only Memory (ROM) Combinational Programmable and Flash reitable Volatile and non-volatile Digital Design Chapter 5 Memories 3 Asynchronous SRAM Data stored in -bit latch cells Address decoded to able a giv cell Usually use active-low control inputs Not available as componts in ASICs or FPGAs A D CE WE OE A CE WE OE D t su t h read data stored data Digital Design Chapter 5 Memories 4 7

8 Asynch SRAM Timing Timing parameters published in data sheets Access time From address/able valid to data-out valid Cycle time From start to d of access Data setup and hold Before/after d of WE pulse Makes asynch SRAMs hard to use in clocked synchronous designs Digital Design Chapter 5 Memories 5 Example Data Sheet Digital Design Chapter 5 Memories 6 8

9 Synchronous SRAM (SSRAM) Clocked storage registers for inputs address, data and control inputs stored on a clock edge held for read/ite cycle Flow-through SSRAM no register on data output A a a 2 D_in xx D_out xx M(a 2 ) Digital Design Chapter 5 Memories 7 Example: Coefficit Multiplier Compute function Coefficit stored in flow-through SSRAM 2-bit unsigned integer index for i x, y, c i 2-bit signed fixed-point 8 pre- and 8 post-binary point bits Use a single multiplier Multiply c i x x y = c i 2 x Digital Design Chapter 5 Memories 8 9

10 Multiplier Datapath SSRAM i A c_in D_in D_out c_ram_ c_ram_ x D Q D Q y ce x_ce ce mult_sel y_ce Digital Design Chapter 5 Memories 9 Multiplier Timing and Control step,,, step2,,, step3,,, start c_ram_ x_ce mult_sel y_ce step step step2 step3 step Digital Design Chapter 5 Memories 2

11 Pipelined SSRAM Data output also has a register More suitable for high-speed systems Access RAM in one cycle, use the data in the next cycle A D_in a xx a 2 D_out xx M(a 2 ) Digital Design Chapter 5 Memories 2 Memories in RAM storage represted by an array signal type RAM_4Kx6 is array ( to 495) of std_logic_vector(5 downto ); signal data_ram : RAM_4Kx6;... data_ram_flow_through : process () is begin if rising_edge() th if = '' th if = '' th data_ram(to_integer(a)) <= d_in; d_out <= d_in; else d_out <= RAM(to_integer(a)); d if; d if; d if; d process data_ram_flow_through; Digital Design Chapter 5 Memories 22

12 Example: Coefficit Multiplier library ieee; use ieee.std_logic_64.all, ieee.numeric_std.all, ieee.fixed_pkg.all; tity scaled_square is port (, reset : in std_logic; start : in std_logic; i : in unsigned( downto ); c_in, x : in sfixed(7 downto -2); y : out sfixed(7 downto -2) ); d tity scaled_square; architecture rtl of scaled_square is signal c_ram_, c_ram_, x_ce, mult_sel, y_ce : std_logic; signal c_out, x_out : sfixed(7 downto -2); signal y_out : sfixed(7 downto -2); type c_array is array ( to 495) of sfixed(7 downto -2); signal c_ram : c_array; type state is (step, step2, step3); signal currt_state, next_state : state; Digital Design Chapter 5 Memories 23 Example: Coefficit Multiplier begin c_ram_ <= ''; c_ram_flow_through : process () is begin if rising_edge() th if c_ram_ = '' th if c_ram_ = '' th c_ram(to_integer(i)) <= c_in; c_out <= c_in; else c_out <= c_ram(to_integer(i)); d if; d if; d if; d process c_ram_flow_through; Digital Design Chapter 5 Memories 24 2

13 Example: Coefficit Multiplier y_reg : process () is variable operand, operand2 : sfixed(7 downto -2); begin if rising_edge() th if y_ce = '' th if mult_sel = '' th operand := c_out; operand2 := x_out; else operand := x_out; operand2 := y_out; d if; y_out <= operand * operand2; d if; d if; d process y_reg; y <= y_out; state_reg : process... next_state_logic : process... output_logic : process... d architecture rtl; Digital Design Chapter 5 Memories 25 Pipelined SSRAM in data_ram_pipelined : process () is variable pipeline_ : std_logic; variable pipeline_d_out : std_logic_vector(5 downto ); begin if rising_edge() th if pipelined_ = '' th d_out <= pipelined_d_out; d if; pipeline_ := ; output register SSRAM if = '' th if = '' th data_ram(to_integer(a)) <= d_in; pipeline_d_out := d_in; else pipeline_d_out := RAM(to_integer(a)); d if; d if; d if; d process data_ram_pipelined; Digital Design Chapter 5 Memories 26 3

14 Gerating SSRAM Componts Variations on SSRAM behavior E.g., ite-first, read-first or no-change on ite cycle Burst accesses to successive locations Not all synthesis tools recognize the same templates Use a RAM core gerator tool Digital Design Chapter 5 Memories 27 Example: RAM Core Gerator Digital Design Chapter 5 Memories 28 4

15 Multiport Memories Multiple address, data and control connections to the storage locations Allows concurrt accesses Avoids multiplexing and sequcing Scario Data producer and data consumer What if two ites to a location occur concurrtly? Result may be unpredictable Some multi-port memories include an arbiter Digital Design Chapter 5 Memories 29 FIFO Memories First-In/First-Out buffer Connecting producer and consumer Decouples rates of production/consumption Producer subsystem FIFO Consumer subsystem Implemtation using dual-port RAM Circular buffer Full: ite-addr = read-addr Empty: ite-addr = read-addr ite read Digital Design Chapter 5 Memories 3 5

16 Example: FIFO Datapath rd_ counter 8-bit ce Q A_rd reset = equal reset counter 8-bit ce Q reset A_ dual-port SSRAM A_ A_rd D_ D_rd _ rd_ D_rd D Equal = full or empty Need to distinguish betwe these states How? Digital Design Chapter 5 Memories 3 Example: FIFO Control Control FSM filling wh ite without concurrt read emptying wh without concurrt ite Unchanged wh concurrt ite and read _, rd_ emptying,, filling full = filling and equal empty = emptying and equal Digital Design Chapter 5 Memories 32 6

17 Multiple Clock Domains Need to resynchronize data that traverses clock domains Use resynchronizing registers May overrun if sder's clock is faster than receiver's clock FIFO smooths out differces in data flow rates Latch cells inside FIFO RAM itt with sder's clock, read with receiver's clock Digital Design Chapter 5 Memories 33 Dynamic RAM (DRAM) Data stored in a -transistor/-capacitor cell Smaller cell than SRAM, so more per chip But longer access time Write operation pull bit-line high or low ( or ) activate word line Read operation bit line word line precharge bit-line to intermediate voltage activate word line, and sse charge equalization reite to restore charge Digital Design Chapter 5 Memories 34 7

18 DRAM Refresh Charge on capacitor decays over time Need to sse and reite periodically Typically every cell every 64ms Refresh each location DRAMs organized into banks of rows Refresh whole row at a time Can t access while refreshing Interleave refresh among accesses Or burst refresh every 64ms Digital Design Chapter 5 Memories 35 Read-Only Memory (ROM) For constant data, or CPU programs Masked ROM Data manufactured into the ROM Programmable ROM (PROM) Use a PROM programmer Erasable PROM (EPROM) UV erasable Electrically erasable (EEPROM) Flash RAM Digital Design Chapter 5 Memories 36 8

19 Combinational ROM A ROM maps address input to data output This is a combinational function! Specify using a table Example: 7-segmt decoder BCD BCD BCD2 BCD3 blank A A A2 A3 A4 D D D2 D3 D4 D5 D6 a b c d e f g Address Contt Address Contt Digital Design Chapter 5 Memories 37 Example: ROM in library ieee; use ieee.numeric_std.all; architecture ROM_based of sev_seg_decoder is type ROM_array is array ( to 3) of std_logic_vector ( 7 downto ); constant ROM_contt : ROM_array := ( => "", => "", 2 => "", 3 => "", 4 => "", 5 => "", 6 => "", 7 => "", 8 => "", 9 => "" to 5 => "", 6 to 3 => "" ); begin seg <= ROM_contt(to_integer(unsigned(blank & bcd))); d architecture ROM_based; Digital Design Chapter 5 Memories 38 9

20 Flash RAM Non-volatile, readable (relatively fast), itable (relatively slow) Storage partitioned into blocks Erase a whole block at a time, th ite/read Once a location is itt, can't reite until erased NOR Flash Can ite and read individual locations Used for program storage, random-access data NAND Flash Dser, but can only ite and read block at a time Used for bulk data, e.g., cameras, memory sticks Digital Design Chapter 5 Memories 39 Memory Errors Bits in memory can be flipped Hard error The chip is brok E.g., manufacturing defect, wear (in Flash) Soft error Stored data corrupted, but cell still works E.g., from atmospheric neutrons Soft-error rate frequcy of occurrce Digital Design Chapter 5 Memories 4 2

21 Error Detection using Parity Add a parity bit to each location On ite access compute data parity and store with data On read access check parity, take exception on error If we could tell which bit flipped correct by flipping it back, th ite back to memory location Can t do this with parity Digital Design Chapter 5 Memories 4 Error-Correcting Codes (ECC) Allow idtification of the flipped bit Hamming Codes E.g., for single-bit-error correction of N-bit word, need log 2 N + extra bits Example: 8-bit word, d... d 8 2-bit ECC code, e...e 2 e, e 2, e 4, e 8 are check bits, the rest data d 8 d 7 d 6 d 5 d 4 d 3 d 2 d e 2 e e e 9 e 8 e 7 e 6 e 5 e 4 e 3 e 2 e Digital Design Chapter 5 Memories 42 2

22 Hamming Code Example d 8 d 7 d 6 d 5 d 4 d 3 d 2 d e = e 3 e 5 e 7 e 9 e e 2 e e e 9 e 8 e 7 e 6 e 5 e 4 e 3 e 2 e e 2 = e 3 e 6 e 7 e e e e 2 e 4 e 8 e 3 e 5 e 6 e 7 e 9 e e e 2 e 4 = e 5 e 6 e 7 e 2 e 8 = e 9 e e e 2 Every data bit covered by two or more check bits On ite: Compute check bits and store with data Digital Design Chapter 5 Memories 43 Hamming Code Example e e 2 e 4 e 8 e 3 e 5 e 6 e 7 e 9 e e e 2 On read: Recompute check bits and XOR with read check bits result called the syndrome => no error If data bit flipped covering bits of syndrome are = binary code of flipped ECC bit If stored check bit flipped that bit of syndrome is On error, unflip bit and reite memory location Digital Design Chapter 5 Memories 44 22

23 Multiple-Error Detection What if two bits flip syndrome idtifies ong bit, or is invalid One extra check bit allows single-error correction, double-error detection N Single-bit correction Check bits Overhead 4 5% 5 3% 6 9% 7 % 8 6.3% 9 3.5% Double-bit detection Check bits Overhead 5 63% 6 38% 7 22% 8 3% 9 7.% 3.9% Digital Design Chapter 5 Memories 45 Summary Memory: addressable storage locations Read and Write operations Asynchronous RAM Synchronous RAM (SSRAM) Dynamic RAM (DRAM) Read-Only Memory (ROM) and Flash Multiport RAM and FIFOs Error Detection and Correction Hamming Codes Digital Design Chapter 5 Memories 46 23