Dvojiška aritmetika. Miha Moškon. UL-FRI (R3.61)
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1 Dvojiška aritmetika Miha Moškon UL-FRI (R3.61)
2 Zapis predznačenih števil Zapis predznak in velikost Zapis z odmikom Eniški komplement Dvojiški komplement
3 Zapis predznak in velikost najvišji bit določa predznak 0: pozitivno število 1: negativno število ostali biti določajo velikost števila prednost lahko berljiv zapis slabosti posebna obravnava MSB bita pri aritmetičnih operacijah seštevanje/odštevanje: primerjati moramo velikosti operandov, da določimo predznak rezultata dve ničli Primer: 3-bitno število binarno vrednost
4 Zapis predznak in velikost Obseg števil za n bitov: Primer: 4-bitno število
5 Zapis z odmikom množico vrednosti razpolovimo na negativne in pozitivne kjer smo razpolovili, imamo 0 odmik primer: 3-bitno število odmik = 3 vrednost = zapis 3 prednosti: samo ena ničla slabosti: pri aritmetičnih operacijah moramo odmik eksplicitno upoštevati Primer: 3-bitno število binarno vrednost
6 Zapis z odmikom primer seštevanja dveh števil: Primer: 3-bitno število binarno vrednost Rezultat je napačen! Zakaj? števili, ki ju seštevamo števili zapisani z odmikom odmik V primeru seštevanja, dobimo torej dva odmika in moramo enega odšteti: Kaj pa odštevanje in množenje?
7 Eniški komplement negativno vrednost števila dobimo tako, da invertiramo vse bite v zapisu eniški komplement števila p v n-bitnem zapisu dobimo z enačbo: slabosti primer (n=3): dve ničli aritmetika: v določenih primerih napačen rezultat popravek : negativno vrednost potegnemo za 1 navzgor Primer: 3-bitno število binarno vrednost
8 Dvojiški komplement negativno vrednost števila dobimo tako, da invertiramo vse bite v zapisu in prištejemo 1 z drugimi besedami: vrednosti negativnega števila v eniškem komplementu prištejemo 1 dvojiški komplement števila p v n-bitnem zapisu dobimo z enačbo: prednosti: samo ena ničla ni težav z aritmetičnimi operacijami Primer: 3-bitno število binarno vrednost
9 Dvojiški komplement Samo 1 ničla V zapisu je negativnih števil za 1 več kot pozitivnih števil. Primer: 4-bitna števila
10 Dvojiški komplement Primer ročne pretvorbe: n = 11 p = 405= ( ) = k =
11 Seštevanje z dvojiškim komplementom
12 Odštevanje z dvojiškim komplementom
13 Preliv (Overflow) n-bitni zapis: števila v razponu primer: n =3: [-4,3] n = 16: [-32768,32767]: če prištejemo 1, dobimo narobe Če rezultata ne moremo zapisati v območju predstavitve števila, govorimo o prelivu/prekoračitvi (arithmetic overflow) Potrebujemo logiko za zaznavanje preliva!
14 Primeri preliva Če imajo števila različne predznake, do preliva ne more priti!
15 Zaznavanje preliva Seštevanje dveh pozitivnih števil nam vrne negativno število (MSB števil je 0, MSB rezultata je 1). Seštevanje dveh negativnih števil na vrne pozitivno število (MSB števil je 1, MSB rezultata je 0). Zaznavanje preliva:
16 Zaznavanje preliva Preliv lahko izrazimo s prenosoma pri seštevanju najbolj pomembnih bitov a n-1 b n-1 c n-1 c n s n-1 V c n c n-1 c n in c n
17 Izogibanje prelivu Razteg predznaka (angl. sign extension). Podvojimo MSB, ki v dvojiškem komplementu določa predznak. Pri seštevanju dveh n-bitnih števil, tako dobimo (n+1)-bitni rezultat do preliva ne more priti! Prenos na MSB lahko ignoriramo. Primer: brez razširitve: 4 6 = = = 6 z razširitvijo: 4 6 = (1) (1) = ( ) = = - 10
18 Števila v jeziku VHDL Nepredznačena števila: v dvojiškem zapisu je MSB na levi. Predznačena števila: dvojiški komplement za negativna števila; MSB določa predznak. Vgrajeni številski tipi omejeni: npr. integer je 32-bitno število, ki ne podpira bitnih operacij in indeksiranja (načeloma se uporablja le za konstante). type INTEGER is range to ; subtype NATURAL is INTEGER range 0 to ; subtype POSITIVE is INTEGER range 1 to ; Uporaba knjižnic za dodatne podatkovne tipe.
19 Števila v jeziku VHDL Knjižnica: std_logic_arith: knjižnica proizvajalca Synopsis omogoča deklaracijo tipov signed in unsigned: signal a: signed(7 downto 0); signal b: unsigned(7 downto 0); podpira aritmetične operacije nad števili (npr. + in -) vektor nima numerične interpretacije type SIGNED is array(natural range <>) of STD_LOGIC; type UNSIGNED is array(natural range <>) of STD_LOGIC; Od -128 do 127 Od 0 do 255 uporaba skupaj s knjižnicama za avtomatsko intepretacijo std_logic vektorja (ne uporabljaj obeh hkrati) UNSIGNED aritmetika skupaj z uporabo knjižnice std_logic_unsigned SIGNED aritmetika skupaj z uporabo knjižnice std_logic_signed
20 Števila v jeziku VHDL Knjižnice: numeric_std, numeric_bit: IEEE knjižnici za numerične operacije na std_logic in bit podatkovnih tipih. omogoča deklaracijo tipov signed in unsigned alternativa knjižnici arith redko kombinacija s knjižnicama std_logic_unsigned ali std_logic_signed. Nikoli std_logic_arith in numeric_std hkrati (konflikt)! type SIGNED is array(natural range <>) of STD_LOGIC; type UNSIGNED is array(natural range <>) of STD_LOGIC; type SIGNED is array(natural range <>) of BIT; type UNSIGNED is array(natural range <>) of BIT;
21 Števila v jeziku VHDL Rezultat nad dvema vektorjema različnih velikosti je dolžine daljšega vektorja. Rezanje prekoračitve.
22 Števila v jeziku VHDL library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all ; signal A:unsigned(3 downto 0); signal B:signed (3 downto 0); signal C:std_logic_vector (3 downto 0); A <= "1111"; -- A = B <= "1111"; -- B = (-1) 10 C <= "1111"; -- C = 15 10, ker je vključena std_logic_unsigned
23 Pretvorba med tipi Pomembni tipi: signed, unsigned, integer, std_logic_vector Funkcije za pretvorbo med tipi: conv_[type] asig:integer, signed, unsigned, std_logic_vector conv_integer(asig): convert asig to integer conv_unsigned(asig,n): convert asig to n-bit unsigned conv_signed(asig,n): convert asig to n-bit signed conv_std_logic_vector(asig,n):convert asig to n-bit std_logic_vector
24 Pretvorba med tipi: v vektor conv_std_logic_vector(arg: integer, size: integer) return std_logic_vector; conv_std_logic_vector(arg: unsigned, size: integer) return std_logic_vector; conv_std_logic_vector(arg: signed, size: integer) return std_logic_vector;
25 Pretvorba med tipi: natural v unsigned library ieee; use ieee.std_logic_arith.all; use ieee.std_logc_1164.all; entity conversion_demo is port(value_i : in natural range 0 to 255; result_o : out unsigned(7 downto 0) ); end; architecture behavior of conversion_demo is begin result_o <= conv_unsigned(value_i,result_o length); end;
26 Pretvora med tipi: v signed in unsigned Poleg conv Iz vektorja: signed(arg: std_logic_vector) return signed; unsigned(arg: std_logic_vector) return unsigned; Iz integerja: to_unsigned(arg: integer, size: integer) return unsigned; to_signed(arg: integer, size: integer) return signed;
27 Pretvorba med tipi: vektor v unsigned library ieee; use ieee.std_logic_arith.all; use ieee.std_logc_1164.all; entity conversion_demo is port(value_i : in std_logic_vector(7 downto 0); result_o : out unsigned(7 downto 0) ); end; architecture behavior of conversion_demo is begin result_o <= unsigned(value_i); end;
28 Pretvora med tipi: integer Poleg conv to_integer(arg) return integer;
29 Povečevanje obsega library ieee; use ieee.std_logic_arith.all; use ieee.std_logc_1164.all; entity unsigned_resize_larger is port(a_i : in unsigned(7 downto 0); z_o : out unsigned(15 downto 0) ); end; architecture behavior of unsigned_resize_larger is begin z_o <= conv_unsigned(a_i, 16); end; msb lsb
30 Povečevanje obsega library ieee; use ieee.std_logic_arith.all; use ieee.std_logc_1164.all; entity signed_resize_larger is port(a_i : in signed(7 downto 0); z_o : out signed(15 downto 0) ); end; architecture behavior of signed_resize_larger is begin z_o <= conv_signed(a_i, 16); end; msb lsb
31 Povečevanje obsega library ieee; use ieee.std_logic_arith.all; use ieee.std_logc_1164.all; entity signed_resize_larger is port(a_i : in signed(7 downto 0); z_o : out signed(15 downto 0) ); end; architecture behavior of signed_resize_larger is begin z_o <= conv_signed(a_i, z_o'length); end; msb lsb
32 Zmanjševanje obsega library ieee; use ieee.std_logic_arith.all; use ieee.std_logc_1164.all; entity signed_resize_smaller is port(a_i : in unsigned(15 downto 0); z_o : out unsigned(7 downto 0) ); end; architecture behavior of unsigned_resize_smaller is begin z_o <= conv_unsigned(a_i, 8); end; msb lsb
33 Zmanjševanje obsega library ieee; use ieee.std_logic_arith.all; use ieee.std_logc_1164.all; entity signed_resize_smaller is port(a_i : in signed(15 downto 0); z_o : out signed(7 downto 0) ); end; architecture behavior of signed_resize_smaller is begin z_o <= conv_signed(a_i, 8); end; msb lsb
34 Operacije nad števili Primerjanje števil: =, /=, <, <=, >, >= Aritmetične operacije: +, - *, abs Bitne operacije: AND, OR, NOT Konkatenacija: & Lastna izvedba množilnikov bolj priporočljiva! Operatorjev kot so **, / in mod se v splošnem ne da sintetizirati Deluje le pri deljenju s potenco števila 2.
35 Različne kombinacije SIGNED + INTEGER return SIGNED SIGNED + NATURAL return SIGNED UNSIGNED + INTEGER return UNSIGNED UNSIGNED + NATURAL return UNSIGNED UNSIGNED + SIGNED ni dovoljeno Eksplicitna pretvorba s funkcijami iz prejšnjih prosojnic
36 Različne kombinacije Signal A_uv, B_uv, C_uv, D_uv, E_uv : unsigned(7 downto 0) ; Signal R_sv, S_sv, T_sv, U_sv, V_sv : signed(7 downto 0) ; Signal J_slv, K_slv, L_slv : std_logic_vector(7 downto 0) ; signal Y_sv : signed(7 downto 0) ; A_uv <= B_uv + C_uv ; -- Unsigned + Unsigned = Unsigned D_uv <= B_uv + 1 ; -- Unsigned + Integer = Unsigned E_uv <= 1 + C_uv; -- Integer + Unsigned = Unsigned R_sv <= S_sv + T_sv ; -- Signed + Signed = Signed U_sv <= S_sv + 1 ; -- Signed + Integer = Signed V_sv <= 1 + T_sv; -- Integer + Signed = Signed J_slv <= K_slv + L_slv ; -- if using std_logic_unsigned -- Illegal Cannot mix different array types Y_sv <= A_uv - B_uv; -- want signed result
37 Seštevanje nepredznačenih števil (neupoštevanje preliva) library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all ; entity adder_unsigned is port( a : in STD_LOGIC_VECTOR(1 downto 0); b : in STD_LOGIC_VECTOR(1 downto 0); sum : out STD_LOGIC_VECTOR(1 downto 0)); end adder_unsigned; architecture arch of adder_unsigned is begin sum <= a + b; end arch; Zaradi uporabe knjižnice std_logic_unsigned uporaba posebnih tipov ni potrebna!
38 Seštevanje predznačenih števil (upoštevanje preliva) library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_arith.all; use ieee.std_logic_signed.all ; entity adder_signed is port( a : in STD_LOGIC_VECTOR(1 downto 0); b : in STD_LOGIC_VECTOR(1 downto 0); sum : out STD_LOGIC_VECTOR(2 downto 0)); end adder_signed; architecture arch of adder_signed is begin sum <= (a(1) & a) + (b(1) & b); end arch; Zaradi uporabe knjižnice std_logic_signed uporaba posebnih tipov ni potrebna!
39 Aritmetično logična enota (ALE) Arithmetic Logic Unit (ALU) Aritmetične operacije: npr. seštevanje in odštevanje Logične operacije: npr. logične funkcije in pomikanje podatkov
40 74181 Kombinatorno vezje za izvedbo aritmetično-logičnih operacij. Priključki: A,B: podatkovna vhoda F: podatkovni izhod C n+4 : prenos na najvišjem mestu A=B: enakost vhodov M: kontrolni vhod, ki določa tip operacije M=0: aritmetične M=1: logične S: kontrolni vhodi, ki določajo konkretno operacijo Izvedba 48 različnih operacij.
41 74181
42 74181
43 74181 Invertirani izhodi: kako se izognemo uporabi negatorjev na vhodih in izhodih? Pri logičnih funkcijah uporabljamo dualno funkcijo: Primer:
44 74181 Seštevanje: kako se izognemo uporabi negatorjev na vhodih in izhodih? Pri seštevanju negiramo C n in C n+4. Primer: seštevanje dveh števil seštevanje dveh števil s (S=1001) 'C n 'C n
45 Seštevanje: 74181
46 74181 Odštevanje: kako se izognemo uporabi negatorjev na vhodih in izhodih? Invertirati moramo le izhodni prenos (C n+4 )! Primer: Odštevanje dveh števil odštevanje dveh števil s (-2 10 ) C n C n (S=0110) Če damo na vhod 0, se odšteje 1 in obratno (glej tabelo) C n
47 Primer 1: ALE v VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity ALU_VHDL is port ( number1_i, number2_i: in std_logic_vector(3 downto 0); op_i: in std_logic_vector(2 downto 0); carry_o : out std_logic; flag_o : out std_logic; result_o : out std_logic_vector(3 downto 0) ); end entity ALU_VHDL; architecture Behavioral of ALU_VHDL is signal temp: std_logic_vector(4 downto 0); begin...
48 process(number1_i, number2_i, op_i) is begin flag_o <= '0'; carry_o <= '0'; case op_i is when "000" => -- res = num1 + num2 temp <= std_logic_vector((unsigned('0' & number1_i) + unsigned(number2_i))); result <= temp(3 downto 0); carry_o <= temp(4); when "001" => -- res = num1 - num2, flag = 1 if num2 > num1 if (number1_i >= number2_i) then result <= std_logic_vector(unsigned(number1_i) - unsigned(number2_i)); flag <= '0'; else result <= std_logic_vector(unsigned(number2_i) - unsigned(number1_i)); flag <= '1'; end if; when "010" => result <= number1_i and number2_i; when "011" => result <= number1_i or number2_i; when "100" => result <= number1_i xor number2_i; when "101" => result <= not number1_i; when "110" => result <= not number2_i; when others => -- res = num1 + num2 + 1 temp <= std_logic_vector((unsigned('0' & number1_i) + unsigned(number2_i)) + 1); result <= temp(3 downto 0); carry_o <= temp(4); end case; end process; end architecture Behavioral;
49 Primer 2: ALE v VHDL library IEEE; use IEEE. STD_LOGIC_1164. ALL; use IEEE. STD_LOGIC_ARITH. ALL; use IEEE. STD_LOGIC_UNSIGNED. ALL; entity ale is Generic ( data_width : integer := 8 ); Port ( data_a_i : in STD_LOGIC_VECTOR ( data_width -1 downto 0); data_b_i : in STD_LOGIC_VECTOR ( data_width -1 downto 0); alu_op_i : in STD_LOGIC_VECTOR (2 downto 0); data_o : out STD_LOGIC_VECTOR ( data_width -1 downto 0) ); end ale;
50 Primer ALE v VHDL architecture Behavioral of ale is constant c_alu_op_add : std_logic_vector(2 downto 0) := "000"; constant c_alu_op_sub : std_logic_vector(2 downto 0) := "001"; constant c_alu_op_and : std_logic_vector(2 downto 0) := "010"; constant c_alu_op_or : std_logic_vector(2 downto 0) := "011"; constant c_alu_op_xor : std_logic_vector(2 downto 0) := "100"; begin with alu_op_i select data_o <= data_a_i + data_b_i when c_alu_op_add, data_a_i - data_b_i when c_alu_op_sub, data_a_i and data_b_i when c_alu_op_and, data_a_i or data_b_i when c_alu_op_or, data_a_i xor data_b_i when c_alu_op_xor, 0 when others ; end Behavioral;
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