FPGA.

Transcription

1

2 CMOS TTL Verilog VHDL

3 7400. NAND CMOS TTL 1 0 source sink datasheet bounce

4 bounce debunce RS Latch debounce Typical Characteristics NO NC Semiconductor Material Wavelength Colour V 20mA NOR NAND GaAs nm Infra- Red 1.2v bounce GaAsP nm Red 1.8v bounce GaAsP nm Amber 2.0v GaAsP:N nm Yellow 2.2v AlGaP nm Green 3.5v SiC nm Blue 3.6v GaInN 450nm White 4.0v 0 1 CMOS (source) (standard) (sink) TTL 7400 kω Vcc

5 Vcc Ω 1 High Low 1 0 debounce 7400 RS Latch NAND

6 NOT OR AND carry Reset Load clock clock clock load reset clock load reset clock load reset clock clock look-ahead-carry

7 NOT OR AND seg seg 7segment seven segment 9 0 dp g f e d c b a 7seg (Common Anode) (Common Cathode) 7seg 7seg 7seg k

8

9 reset clk (load) reset khz ms khz (time-base) b a b khz a b BCD Hz reset b b khz a ms 7seg reset Hz Hz

10 (time-base) Hz Hz 74283

11 BCD BCD to 7segment

12 don t care FSM ASM BCD 74153

13 A/D 1 Latch D/A DAC D/A R/2R (R) V od kω kω ADC A/D A/D S&H A/D

14 (successive approximations) R/2R D/A A/D start conversion D/A start conversion D/A A/D

15 x Vcc active low low low active low load enable x = x 1 3 = (low) low reset set reset

16

17 (3S400-PQ208) Spartan 3 SDRAM Dip-Switch MHz (RS232) USB DAC ADC Flash ROM ROM JTAg Xilinx ISE clear VHDL code for 7-segment drive library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity svnsegdrv is port ( din : in std_logic_vector (3 downto 0); segs : out std_logic_vector (7 downto 0));

18 end svnsegdrv; architecture behavioral of svnsegdrv is --file produced for nasre shargh fpga board --input : 4 bits are normally located : left msb, right lsb begin -- abcdefgdp common cathode -- with din select -- segs <= " " when "0000", -- " " when "0001", -- " " when "0010", -- " " when "0011", -- " " when "0100", -- " " when "0101", -- " " when "0110", -- " " when "0111", -- " " when "1000", -- " " when "1001", -- " " when "1010", -- " " when "1011", -- " " when "1100", -- " " when "1101", -- " " when "1110", -- " " when "1111", -- " " when others; with din select -- abcdefgdp common anode segs <= " " when "0000", " " when "0001", " " when "0010", " " when "0011", " " when "0100", " " when "0101", " " when "0110", " " when "0111", " " when "1000", " " when "1001", " " when "1010", " " when "1011", " " when "1100", " " when "1101", " " when "1110", " " when "1111", " " when others; end behavioral;

19 MHz AM/PM dip-switch MHz khz VHDL code for clock library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity clock2 is port ( clk : in std_logic; csel : in std_logic_vector (2 downto 0); yml : out std_logic_vector (7 downto 0); ymh : out std_logic_vector (7 downto 0); yhl : out std_logic_vector (7 downto 0); yhh : out std_logic_vector (7 downto 0); ampm : out std_logic);

20 end clock2; architecture behavioral of clock2 is component svnsegdrv port( din : in std_logic_vector(3 downto 0); segs : out std_logic_vector(7 downto 0) ); end component; signal d0 : std_logic_vector(3 downto 0) := (others => '0'); signal d1 : std_logic_vector(3 downto 0) := (others => '0'); signal d2 : std_logic_vector(3 downto 0) := (others => '0'); signal d3 : std_logic_vector(3 downto 0) := (others => '0'); signal c : std_logic_vector(27 downto 0) := (others => '0'); signal ck : std_logic; signal sampm : std_logic := '0'; begin process(clk, ck) begin if rising_edge(clk) then --ck'event and clk='1' then c<=c+1; end if; if rising_edge(ck) then if d0="1001" then d0 <= (others => '0'); if d1="0101" then d1 <= (others => '0'); if d2="1001" or (d2="0001" and d3="0001") then d2 <= (others => '0'); if d3="0001" then d3 <= (others => '0'); sampm <= not sampm; else d3<=d3+1; end if; else d2<=d2+1; end if; else d1<=d1+1; end if; else d0<=d0+1; end if; end if; end process; dd0: svnsegdrv port map(din => d0, segs => yml ); dd1: svnsegdrv port map(din => d1, segs => ymh ); dd2: svnsegdrv port map(din => d2, segs => yhl ); dd3: svnsegdrv port map(din => d3, segs => yhh ); ampm <= sampm; ck <= c(23) when (csel(0)='1') else c(20) when (csel(1)='1') else c(17) when (csel(2)='1') else c(14); end behavioral;

21 VHDL VHDL hex n n-bit x n-bit.ucf ucf pull-up.ucf VHDL code for keypad decoding library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity clock2 is

22 port ( clk : in std_logic; column : in std_logic_vector (3 downto 0); csel : in std_logic_vector (2 downto 0); row : out std_logic_vector (3 downto 0); y : out std_logic_vector (7 downto 0); cout : out std_logic_vector (7 downto 0); ampm : out std_logic); end clock2; architecture behavioral of clock2 is begin component svnsegdrv port( din : in std_logic_vector(3 downto 0); segs : out std_logic_vector(7 downto 0) ); end component; signal count : std_logic_vector(3 downto 0) := (others => '0'); signal reg : std_logic_vector(3 downto 0) := (others => '0'); signal decode : std_logic_vector(3 downto 0) := (others => '0'); signal c : std_logic_vector(27 downto 0) := (others => '0'); signal ck : std_logic; signal regclk : std_logic := '0'; process(clk) begin if rising_edge(clk) then --ck'event and clk='1' then c<=c+1; end if; end process; process(ck) begin if rising_edge(ck) then if count="1111" then count <= (others => '0'); else count<=count+1; end if; if regclk='1' then reg <= count; end if; end if; end process; process (count(1 downto 0),column(0),column(1),column(2),column(3)) begin case count(1 downto 0) is when "00" => regclk <= not column(0); when "01" => regclk <= not column(1); when "10" => regclk <= not column(2); when "11" => regclk <= not column(3); when others => regclk <= not column(0); end case; end process; dd0: svnsegdrv port map(din => count, segs => cout ); dd1: svnsegdrv port map(din => reg, segs => y ); ck <= c(23) when (csel(0)='1') else c(20) when (csel(1)='1') else c(17) when (csel(2)='1') else c(14); with count(3 downto 2) select row <= "0111" when "00", "1011" when "01", "1101" when "10", "1110" when others;

23 end behavioral;

24 BCD truncation

25 BCD BCD BCD BCD BCD n BCD function Destination (BCD) x100 x10 x1 Source (binary) start state shift # shift # shift #3, 7> add with result shift #4, 5> add with result shift # shift #6, 6> add with result shift #7, 7> add with result shift # n n m m BCD m BCD BCD BCD BCD

26 ascii bps bps dipswitch bps RS232 0 start bit 1 stop bit parity 1 idle 1 bps D D RS232

27 0 1 start idle stop 1 framing error 0 parity error dipswitch bps ascii bps bps

28 o o o (busy)

29