Synthesis of Sequential Logic from Behavioral Code
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1 It s all about the flip-flop. Synthesis of Sequential Logi from Behavioral Code Storage devies are the distinguishing feature that differentiate ombinational and sequential logi. Why sequential logi is so muh harder than ombinational logi. Inferene: There isn t an operator that synthesizes to a flip-flop as there is, say, with + for addition. Logi Design: Designs are trikier it s not just what will happen it s not even just when it will happen but whether this happens before that or after that. Verilog Subtleties: Those ignorant of Verilog timing may be tormented with seemingly arbitrary errors or behavior. omb 1 LSU EE 4755 Leture Transpareny. Formatted 9:23, 6 Otober 2017 from lsli-syn-seq. syn omb
2 Enounter s Generi Flip-Flop: flop. Inferene of Registers flop features: apre srl Is positive edge triggered (). flop Has input d and output q. d q Has asynhronous preset (apre) and lear (alr). Has a syn. enable (sena) input. sena alr srd omb 2 LSU EE 4755 Leture Transpareny. Formatted 9:23, 6 Otober 2017 from lsli-syn-seq. syn omb
3 Enounter s Generi Flip-Flop: flop. Inferene and Mapping During elaboration flop used for all inferred edge-triggered registers. During tehnology mapping flop replaed with registers from tehnology library. apre srl d sena flop alr srd q omb 3 LSU EE 4755 Leture Transpareny. Formatted 9:23, 6 Otober 2017 from lsli-syn-seq. syn omb
4 Classroom Hardware Diagrams The term register will be used for one or more flip-flops. For inferred and optimized hardware will use streamlined diagrams, omitting unused inputs: apre srl d flop q enable data register_en en D Q val sena alr srd omb 4 LSU EE 4755 Leture Transpareny. Formatted 9:23, 6 Otober 2017 from lsli-syn-seq. syn omb
5 Edge-Triggered Flip-Flop Inferene Inferene Seleting a hardware omponent orresponding to a piee of Verilog behavioral ode. Performed by a synthesis program. Relationship between behavioral Verilog and inferred hardware is determined by the synthesis program not by the Verilog standard or any other standard doument. omb 5 LSU EE 4755 Leture Transpareny. Formatted 9:23, 6 Otober 2017 from lsli-syn-seq. syn omb
6 Edge-Triggered Flip-Flop Inferene Rules These Inferene Rules Based on Enounter RTL Compiler. Referene: HDL Modeling in Enounter RTL Compiler 14.2 April For inferene of edge-triggered register R loked by : R must be a variable type. R must be assigned in exatly one always blok and must be either onsistently bloking (R=x;) or onsistently non-bloking (R<=x;). The always blok must start with always or always ff. The always must be followed by an event ontrol of the posedge,...). omb 6 LSU EE 4755 Leture Transpareny. Formatted 9:23, 6 Otober 2017 from lsli-syn-seq. syn omb
7 Simple Register module register #( int width = 16 ) ( output logi [width-1:0] val, input uwire [width-1:0] data, input uwire ); data register D Q val posedge ) val <= data; endmodule t data val omb 7 LSU EE 4755 Leture Transpareny. Formatted 9:23, 6 Otober 2017 from lsli-syn-seq. syn omb
8 Register with Enable module register_en #( int width = 16 ) ( output logi [width-1:0] val, input uwire enable, input uwire [width-1:0] data, input uwire ); enable data register_en en D Q val posedge ) if ( enable ) val <= data; endmodule t enable data val omb 8 LSU EE 4755 Leture Transpareny. Formatted 9:23, 6 Otober 2017 from lsli-syn-seq. syn omb
9 Clok with Reset Note multiple C values. ount_reset module ount_reset #( int bits = 16 ) ( output logi [bits-1:0], input uwire reset, input uwire ); 16'd1 reset + 16'd0 D posedge ) if ( reset ) <= 0; else <= + 1; endmodule omb 9 LSU EE 4755 Leture Transpareny. Formatted 9:23, 6 Otober 2017 from lsli-syn-seq. syn omb
10 Threshold Output module ount_thd #( int bits = 16 ) ( output logi [bits-1:0], output logi over_th, input uwire [bits-1:0] threshold, input uwire ); posedge ) begin = + 1; over_th = > threshold; end endmodule threshold 16'd1 + ount_thd D over_th t D over_th 5 threshold over_th over_th omb 10 LSU EE 4755 Leture Transpareny. Formatted 9:23, 6 Otober 2017 from lsli-syn-seq. syn omb
11 Two Issues: Critial path through adder/omparison unit. Do we really want a flip-flop for over th? t ount_thd threshold 16'd1 + over_th D D over_th threshold over_th over_th 5 omb 11 LSU EE 4755 Leture Transpareny. Formatted 9:23, 6 Otober 2017 from lsli-syn-seq. syn omb
12 Fix ritial path issue. module ount_thd_alt2 #( int bits = 16 ) ( output logi [bits-1:0], output logi over_th, input uwire [bits-1:0] threshold, input uwire ); posedge ) begin over_th = > threshold; = + 1; end threshold 16'd1 ount_thd + over_th D D over_th endmodule omb 12 LSU EE 4755 Leture Transpareny. Formatted 9:23, 6 Otober 2017 from lsli-syn-seq. syn omb
13 Reat any time to threshold, not just at positive edge. module ount_thd_alt #( int bits = 16 ) ( output logi [bits-1:0], output logi over_th, input uwire [bits-1:0] threshold, input uwire ); threshold 16'd1 ount_thd + D posedge ) <= + 1; over_th always_omb over_th = > threshold; endmodule omb 13 LSU EE 4755 Leture Transpareny. Formatted 9:23, 6 Otober 2017 from lsli-syn-seq. syn omb
14 Example: Sequential Shifter Remember: We an build an n-bit shifter using log 2 n 2 i -bit shifters and 2-input muxen. Why not use one fixed shifter and use it up to n 1 times? Why not use < log 2 n shifters and muxen but use them multiple times? We ll start with one fixed shifter. omb 14 LSU EE 4755 Leture Transpareny. Formatted 9:23, 6 Otober 2017 from lsli-syn-seq. syn omb
15 Idea sketh for sequential shifter. shift_lt_seq sf shift_ xed trips thru shifter un un t Pass value through shifter times. omb 15 LSU EE 4755 Leture Transpareny. Formatted 9:23, 6 Otober 2017 from lsli-syn-seq. syn omb
16 Idea sketh for sequential shifter. shift_lt_seq sf shift_ xed un un start Magi Cloud tm 4'd1 ready Use register to ount number of times. omb 16 LSU EE 4755 Leture Transpareny. Formatted 9:23, 6 Otober 2017 from lsli-syn-seq. syn omb
17 Timing. shift_lt_seq 0 sf shift_ xed 1 un un start Magi Cloud tm 4'd1 ted 2 ready r : External devie provides inputs. Inputs assumed to be available early in lok yle. ted omb 17 LSU EE 4755 Leture Transpareny. Formatted 9:23, 6 Otober 2017 from lsli-syn-seq. syn omb
18 Timing. shift_lt_seq 0 sf shift_ xed 1 un un start Magi Cloud tm 4'd1 ted 2 ready r : At positive edge: initialized to. ted initialized to un. omb 18 LSU EE 4755 Leture Transpareny. Formatted 9:23, 6 Otober 2017 from lsli-syn-seq. syn omb
19 Timing. shift_lt_seq 0 sf shift_ xed 1 un un start Magi Cloud tm 4'd1 ted 2 ready r : Early in Cyle 1: ready goes to zero. ted omb 19 LSU EE 4755 Leture Transpareny. Formatted 9:23, 6 Otober 2017 from lsli-syn-seq. syn omb
20 Timing. shift_lt_seq 0 sf shift_ xed 1 un un start Magi Cloud tm 4'd1 ted 2 ready r : During yles 1 and 2: New value of ount is omputed, shift performed. ted omb 20 LSU EE 4755 Leture Transpareny. Formatted 9:23, 6 Otober 2017 from lsli-syn-seq. syn omb
21 Timing. shift_lt_seq 0 sf shift_ xed 1 un un start Magi Cloud tm 4'd1 ted 2 ready r : Beginning of yle 3: Ready signal set to 1. ted omb 21 LSU EE 4755 Leture Transpareny. Formatted 9:23, 6 Otober 2017 from lsli-syn-seq. syn omb
22 Notes about behavior. Start signal must be stable at positive edge. Inputs required to be available early in lok yle. Result available at beginning of lok yle. Ready signal available early in lok yle. omb 22 LSU EE 4755 Leture Transpareny. Formatted 9:23, 6 Otober 2017 from lsli-syn-seq. syn omb
23 Sequential Shifter Verilog module shift_lt_seq #( int wid_lg = 4, int wid = 1 << wid_lg ) ( output logi [wid-1:0], output uwire ready, input [wid-1:0] un, input [wid_lg-1:0], input start, input ); uwire [wid-1:0] sf_out; shift_fixed #(wid_lg,1) sf( sf_out,, 1 b1 ); // Fixed Shifter logi [wid_lg-1:0] ; posedge ) if ( start == 1 ) begin = un; // Load a new item to shift... = ; //.. and initialize amount. end else if ( > 0 ) begin end = sf_out; // Shift by one more bit.. --; //.. and update ount. assign ready = == 0; // Set ready to 1 when ount is zero. endmodule omb 23 LSU EE 4755 Leture Transpareny. Formatted 9:23, 6 Otober 2017 from lsli-syn-seq. syn omb
24 Inferred Hardware, No Optimization module shift_lt_seq #( int wid_lg = 4, int wid = 1 << wid_lg ) ( output logi [wid-1:0], output uwire ready, input [wid-1:0] un, input [wid_lg-1:0], input start, input ); 1'd1 sf shift_ xed wid_lg=4 =1 t shift_lt_seq uwire [wid-1:0] sf_out; shift_fixed #(wid_lg,1) sf(sf_out,,1 b1); logi [wid_lg-1:0] ; start 4'd0 > 0 posedge ) if ( start == 1 ) begin un = un; = ; end else if ( > 0 ) begin 4'd1 = sf_out; --; 4'd0 r ready end else begin = ; = ; end assign ready = == 0; omb 24endmodule LSU EE 4755 Leture Transpareny. Formatted 9:23, 6 Otober 2017 from lsli-syn-seq. syn omb
25 Inferred Hardware, No Optimization sf shift_ xed wid_lg=4 =1 shift_lt_seq 1 0 1'd1 t start 4'd0 > 0 un ted 2 4'd1 r 'd0 r ready ted omb 25 LSU EE 4755 Leture Transpareny. Formatted 9:23, 6 Otober 2017 from lsli-syn-seq. syn omb
26 t s sf shift_ xed wid_lg=4 =1 shift_lt_seq 0 1'd1 t 1 start 4'd0 > 0 un 4'd1 ted 'd0 r ready r Pay Attention To ted Setup delay: inputs to registers. Operation delay: register to register. Output delay: generation of the ready signal. omb 26 LSU EE 4755 Leture Transpareny. Formatted 9:23, 6 Otober 2017 from lsli-syn-seq. syn omb
27 Streamlining and Optimization Streamline hardware illustration to make it readable. Inlude optimizations we hope synthesis program will make. Optimization Opportunities Use an enable for registers. Shifter is just a bit renaming plus one zero. The three operations on, > 0, 1, and == an all be done by the same logi. omb 27 LSU EE 4755 Leture Transpareny. Formatted 9:23, 6 Otober 2017 from lsli-syn-seq. syn omb
28 m l sf shift_ xed wid_lg=4 =1 shift_lt_seq shift_lt_seq wid_lg=4 1'd1 t start 4'd0 > 0 start v v 1'd0 en un un 4'd1 en 4'd0 r ready ready omb 28 LSU EE 4755 Leture Transpareny. Formatted 9:23, 6 Otober 2017 from lsli-syn-seq. syn omb
29 Sequential Shifter with Multiple Shifters For example: Shift x by 9 bits. num_shifters=2 Use a sequential shifter with 4-bit and 1-bit shifters. Shift by 4-bits twie and by 1-bit one. Features shift_ xed wid_lg=4, =1 shift un shift_ ed wid_lg=4, =4 un shift The register divided into multiple segments. Fixed shifter may or may not shift. start Magi Cloud tm 4'd1 4'd1 ready omb 29 LSU EE 4755 Leture Transpareny. Formatted 9:23, 6 Otober 2017 from lsli-syn-seq. syn omb
30 Performane Analysis and Design Optimization Goal: Choose the best shifter for some larger design. omb 30 LSU EE 4755 Leture Transpareny. Formatted 9:23, 6 Otober 2017 from lsli-syn-seq. syn omb
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