Compiling a Parallel DSL to GPU

Transcription

1 Compiling Prllel DSL to GPU Rmesh Nrynswmy Bdri Gopln Synopsys In. Synopsys

2 Agend Overview of Verilog Simultion Prllel Verilog Simultion Algorithms Prllel Simultion Trdeoffs on GPU Chllenges Synopsys

3 Verilog Hrdwre Desription Lnguge Ojetives Model Hrdwre Modern hips run into 100s of Millions of Gtes Gtes in the rel world n e thought s prllel loks in simultion Model Testenh to test Hrdwre Hrdwre Models Multiple Implementtion Levels Gte, Register Trnsfer Input Output Behvior Behviorl Testenh Generte Input Dt, Expeted Results Drive nd Compre Input Output Behvior Level SystemVerilog Testenh Extensions Synopsys

4 Verilog Models Gte Level Interonnet Comintionl logi Stte holding gtes: Lthes, Flip Flops Lrgely Bit level Register Trnsfer Level (RTL) Interonnet Gurded Proesses Word Level Proess hs Multi line ehvior Some Proess dvne lok y one Cloks, Seuenes re expliit Behviorl Level Proess enompsses mny lok yles Proess my e longer reg [31:0],, ; reg, ; ) if () <= ; else <= ; Comintionl Logi Seuentil Logi reg [31:0],, ; reg, ; ) if () ); <= ; else <= ; Gurded Proess Behviorl sttements Synopsys

5 How Verilog Models Prllelism reg [31:0],,y; ) if (reset) <= y; reg [31:0],,; or ) = ^ ; reg [31:0],,,y; ) if (reset) y <= & ^ ; Gurded Proesses Wkeup or B) hnge on A or hnge on B C) 0 to {1,x,z} or {x,z} to 1 hnge on C #10; 10 time units hve elpsed Proess ody - Seuentil ode with Assignments Glol Stte Simultion Time Vlues of Vriles Proess Stte Glol Stte Simultion Time Vrile Vlues Proess Stte Where to ontinue? Bloked on gurd? Exeuting? Colletion of Exeuting Proesses: Prllel Worklod HDL Simultors n implement Prllel Worklod with: Seril Simultion Algorithms Prllel Simultion Algorithms Synopsys

6 Seril Simultion Algorithms Event Driven Simultion with Dynmi Sheduling Eh lok gurded y hnge-hek Funtionl evlution dynmilly sheduled, exeutes only wht is needed Mny optimiztions for seril simultion, works in norml senrios of low event tivity Bloks evluted in Current lok yle But: not esy to expose prllelism Bloks intive in Current lok yle Synopsys

7 Seril Simultion Algorithms Olivious simultion All prllel loks evluted on ny hnge No event gurds reuired: simplifies implementtion On the surfe, looks suitle for fine grined prllel implementtion Bloks evluted in Current lok yle But: high overhed in the se of low event tivity % Bloks intive in Current lok yle Synopsys

8 Prllel Simultion Algorithms Tsk Bsed Prllelism Prtition 1 Prtition 2 Design (nd / or testenh) split into prtitions Eh prtition mpped into n exeution unit More suitle for igger ores Speedup depends on reltive nd lned tivity in prtitions Bloks evluted in Current lok yle Bloks intive in Current lok yle Synopsys

9 Prllel Simultion Algorithms Fine Grin Prllelism + Olivious simultion All prllel loks evluted on ny hnge No event gurds reuired: simplifies implementtion Lots of Prllel Bloks Bloks evluted in Current lok yle Bloks intive in Current lok yle Synopsys

10 Prllel Simultion Algorithms Mpping Olivious simultion to GPU Level 1 Level 2 Level 3 Level 1 Level 2 Level 3 Synopsys

11 Prllel Simultion Complexity Hypothetil Medium Sized Chip RTL Dt Dependent Ativity Dt flow Til Model: 1 Million+ user proesses Worklod: 10K+Trgeted Tests Eh test trgets hip feture Simultion Dt Dependene etween prtitions Dt Dependent Ativity 0.5 3% Ativity per Test Phse Low Effetive Prllelism Ativity Til Region Synopsys Dt dependene etween prtitions

12 Summry Chllenges / Benefits in using GPU for RTL Sim Wht Works? A lot of potentil prllelism in the model Fermi / CUDA thred sheduling A lot of memory esses per lok yle Fermi provides 144 GBps CUDA softwre eosystem is roust nd improving Wishlist Glol Brrier Lteny Optimized Core Lower lunh overhed CUDA profiler for lrge dtsets Synopsys

13 Referenes Mry L. Biley, Jk V. Briner, Jr., nd Roger D. Chmerlin Prllel logi simultion of VLSI systems. ACM Comput. Surv. 26, 3 (Septemer 1994), Kekler, S.W.; Dlly, W.J.; Khilny, B.; Grlnd, M.; Glso, D.;, "GPUs nd the Future of Prllel Computing," Miro, IEEE, vol.31, no.5, pp.7-17, Sept.- Ot Synopsys

14 Questions? Synopsys