Advanced Topic in Pipeline: Pipeline scheduling

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Kevin Montgomery
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1 Contents dvanced Topic in Pipeline: Pipeline scheduling Linear Pipelines Nonlinear pipelines Instruction Pipelines rithmetic Operations esign of Multifunction Pipeline Linear Pipeline Processing Stages are linearly connected Perform fixed function Synchronous Pipeline Clocked latches between Stage i and Stage i+ qual delays in all stages synchronous Pipeline (Handshaking) No latches between stage i and i+ Special signals are required for acknowledgement Quick Review: loating Point We need a way to represent numbers with fractions, e.g.,. very small numbers (in absolute value), e.g., very large numbers (in absolute value), e.g.,. * 0 Representation: scientific: sign, exponent, significand form: ( ) sign * significand * exponent..g., * 00 more bits for significand gives more accuracy more bits for exponent increases range binary point if significand<0 two (= ten ) then number is normalized, except for number 0 which is normalized to significand 0.g., * 00 =.0000 * 0 (normalized)

2 I loating-point Standard I floating point standard: single precision: one word double precision: two words loating Point ddition lgorithm: Start. Compare the exponents of the two numbers. Shift the smaller number to the right until its exponent would match the larger exponent. dd the significands sign bits 0 to 8-bit exponent bits to 0 -bit significand. Normalize the sum, either shifting right and incrementing the exponent or shifting left and decrementing the exponent sign bits 0 to 0 -bit exponent bits 9 to 0 upper 0 bits of -bit significand bits to 0 Overflow or underflow? No es. Round the significand to the appropriate number of bits xception lower bits of -bit significand No Still normalized? es one loating Point ddition Sign xponent Significand Sign xponent Significand loating Point ddition Hardware: Small LU xponent difference Compare exponents Control Shift right Shift smaller number right ig LU dd 0 Increment or decrement 0 Shift left or right Normalize Rounding hardware Round Sign xponent Significand

3 Latches Reservation Table Time (clock cycle) ach row corresponds to a stage in the pipeline. L Slowest stage determines delay qual delays clock period L ach column corresponds to a pipeline cycle. n at the intersection of the i th row and j th column indicates that stage i is busy at cycle j. S tasks on stages Non Linear Pipelines Time Variable functions eed-orward eedback S

4 stages & functions Reservation Tables for & Linear Instruction Pipelines Pipeline Instruction xecution ssume the following instruction execution phases: etch () ecode () Operand etch (O) xecute () Write results (W) O I I I I W I

5 ependencies ata ependency (Operand is not ready yet) -- dd R, R, R -- Sub R, R, R ata ependency Instruction ependency (ranching) Will that Cause a Problem? O W Solutions STLL orwarding Write and Read in one cycle. Instruction ependency ranch O W

6 STLL Predict ranch taken Predict ranch not taken. Solutions loating Point Multiplication Inputs (Mantissa, xponenet ), (Mantissa, xponent ) dd the two exponents xponent-out Multiple the mantissas Normalize mantissa and adjust exponent Round the product mantissa to a single length mantissa. ou may adjust the exponent Linear Pipeline for floating-point multiplication Linear Pipeline for floating-point ddition dd xponents Multiply Mantissa Normalize Round dd xponents Partial Products ccumulator Normalize Round Subtract xponents Partial Shift dd Mantissa ind Leading Partial Shift Re normalize Round Re normalize

7 Combined dder and Multiplier Reservation Table for Multiply Partial Products xponents Subtract / C G H Partial Shift dd Mantissa ind Leading Partial Shift C Round Re normalize G H Reservation Table for ddition Nonlinear Pipeline esign C 8 9 Latency The number of clock cycles between two initiations of a pipeline Collision Resource Conflict orbidden Latencies Latencies that cause collisions G H

8 Nonlinear Pipeline esign Latency Sequence sequence of permissible latencies between successive task initiations Latency Cycle sequence that repeats the same subsequence Collision vector C = (C m, C m-,, C, C ), m <= n- n = number of column in reservation table C i = if latency i causes collision, 0 otherwise Mul Mul Collision (lunch after cycle) H G C Mul Mul Collision (lunch after cycles) H G C Mul Mul Collision (lunch after cycles) H G C

9 Collision Vector for Multiply after Multiply orbidden Latencies:, Collision vector ( ) Latency xample: Reservation for Maximum forbidden latency = m = xample: Reservation Tables for orbidden Latencies after after after after

10 after after Collision Vector after orbidden Latencies: {,,, } Collision Vector = ( 0 0 0)

11 Collision Vector HW ind the collision vector orbidden Latencies: {, } Collision Vector = ( 0 0) C Pipeline Control Pipeline Control Place collision vector (CV) in shift register (SR) If LS of CV in SR is - do not initiate an operation at that cycle - shift the CV right once - insert 0 at the MS lse - initiate an operation at that cycle - shift the CV right once - insert 0 at the MS - perform CV org + CV shift Stage Stage State xample + CV org CV shift State State Reduced state diagram

12 State iagram for Cycles Simple cycles each state appears only once (), (), (8), (, 8), (, 8), and (,8) * * 8 + Greedy Cycles simple cycles whose edges are all made with minimum latencies from their respective starting states (,8), () one of them is ML (Minimal verage Latency) verage latency for (,8) = (+8) / =. verage latency for () = / =

Chapter 03: Computer Arithmetic. Lesson 09: Arithmetic using floating point numbers

Chapter 03: Computer Arithmetic Lesson 09: Arithmetic using floating point numbers Objective To understand arithmetic operations in case of floating point numbers 2 Multiplication of Floating Point Numbers