Chap. 9 Pipeline and Vector Processing
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1 9-1 Parallel Processing = Simultaneous data processing tasks for the purpose of increasing the computational speed Perform concurrent data processing to achieve faster execution time Multiple Functional Unit : Parallel Processing xample Separate the execution unit into eight functional units operating in parallel Computer rchitectural Classification Data-nstruction Stream : Flynn Serial versus Parallel Processing : Feng Parallelism and Pipelining : Händler Flynn s Classification 1) SSD (Single nstruction - Single Data stream)» for practical purpose: only one processor is useful» xample systems : mdahl 470V/6, M 360/91 S To Memory Processor registers dder-subtractor nteger multiply Logic unit Shift unit ncrementer Floatint-point add-subtract Floatint-point multiply Floatint-point divide CU S PU DS MM Computer System rchitecture
2 9-2 2) SMD (Single nstruction - Multiple Data stream)» vector or array operations PU 1 DS 1 Shared memmory MM 1 one vector operation includes many operations on a data stream» xample systems : CRY -1, LLC-V CU S PU 2 DS 2 MM 2 PU n DS n MM n 3) MSD (Multiple nstruction - Single Data stream)» Data Stream ottle neck DS S S 1 CU 1 S 1 PU 1 Shared memory S 2 CU 2 S 2 PU 2 MM n MM 2 MM 1 S n CU n S n PU n DS Computer System rchitecture
3 9-3 4) MMD (Multiple nstruction - Multiple Data stream)» Multiprocessor System S 1 CU 1 S 1 PU 1 DS Shared memory MM 1 S 2 CU 2 S 2 PU 2 MM 2 v v S n CU n S n PU n MM n Main topics in this Chapter Pipeline processing :» rithmetic pipeline :» nstruction pipeline : Vector processing :adder/multiplier pipeline rray processing : array processor» ttached array processor :» SMD array processor : Large vector, Matrices, rray Data Computer System rchitecture
4 9-4 Pipelining Pipelining Decomposing a sequential process into suboperations ach subprocess is executed in a special dedicated segment concurrently Pipelining xample Multiply and add operation : i* i Ci ( for i = 1, 2,, 7 ) 3 Suboperation Segment»1) R1 i, R2 i : nput i and i»2) R3 R1* R2, R4 Ci : Multiply and input Ci»3) R5 R3 R4 : dd Ci Computer System rchitecture
5 9-5 Pipelining General considerations 4 segment pipeline :» S : Combinational circuit for Suboperation» R : Register(intermediate results between the segments) Space-time diagram :» Show segment utilization as a function of time Task : T1, T2, T3,, T6 Clock cycles » Total operation performed going through all the segment Segment T 1 T 2 T 3 T 4 T 5 T 6 T 1 T 2 T 3 T 4 T 5 T 6 T 1 T 2 T 3 T 4 T 5 T 6 4 T 1 T 2 T 3 T 4 T 5 T 6 Computer System rchitecture
6 9-6 Speedup S : Nonpipeline / Pipeline With pipeline: k-segment pipeline with a clock time t p to execute n tasks Without pipeline: ach task takes t n S = n t n / ( k + n - 1 ) t p = 6 6 t n / ( ) t p = 36 t n / 9 t n = 4» n : task number ( 6 )» t n : time to complete each task in nonpipeline ( 6 cycle times = 6 t p )» t p : clock cycle time ( 1 clock cycle )» k : segment number ( 4 ) Clock cycles T 1 T 2 T 3 T 4 T 5 T 6 Segment 2 3 T 1 T 2 T 3 T 4 T 5 T 6 T 1 T 2 T 3 T 4 T 5 T 6 4 T 1 T 2 T 3 T 4 T 5 T 6 Computer System rchitecture
7 9-7 nstruction Pipeline nstruction Cycle 1) Fetch the instruction from memory 2) Decode the instruction 3) Calculate the effective address 4) Fetch the operands from memory 5) xecute the instruction 6) Store the result in the proper place Computer System rchitecture
8 9-8 nstruction Pipeline xample : Four-segment nstruction Pipeline Four-segment CPU pipeline :» 1) F : nstruction Fetch» 2) D : Decode nstruction & calculate» 3) FO : Operand Fetch» 4) X : xecution Timing of nstruction Pipeline :» nstruction 3 ranch Step : nstruction : 1 F D FO X 2 F D FO X (ranch) 3 F D FO X 4 F F D FO X 5 F D FO X 6 F D FO X 7 F D FO X No ranch ranch Computer System rchitecture
9 9-9 Pipeline Conflicts : 3 major difficulties 1) Resource conflicts» memory access by two segments at the same time 2) Data dependency» when an instruction depend on the result of a previous instruction, but this result is not yet available 3) ranch difficulties» branch and other instruction (interrupt, ret,..) that change the value of PC Data Dependency Hardware» Hardware nterlock previous instruction Hardware Delay» Operand Forwarding previous instruction Software» Delayed Load previous instruction No-operation instruction Computer System rchitecture
10 9-10 Delayed ranch» 1) No-operation instruction Clock cycles : 1. Load 2. ncrement » 2) nstruction Rearranging 3. dd 4. Subtract 5. ranch to X 6. No-operation 7. No-operation 8. nstruction in X (a) Using no-operation instructions Clock cycles : Load 2. ncrement 3. ranch to X 4. dd 5. Subtract 6. nstruction in X (b) Rearranging the instructions Computer System rchitecture
11 RSC Pipeline RSC CPU nstruction Pipeline Single-cycle instruction execution Compiler support xample : Three-segment nstruction Pipeline 3 Suboperations nstruction Cycle» 1) : nstruction fetch» 2) : nstruction decoded and LU operation» 3) : Transfer the output of LU to a register, memory, or PC Delayed Load :» nstruction(dd R1 + R3) Conflict» Delayed Load No-operation Delayed ranch : Conflict Clock cycles : Load R1 2. Load R2 3. dd R1+R2 4. Store R3 (a) Pipeline timing with data conflict Clock cycles : Load R1 2. Load R2 3. No-operation 4. dd R1+R2 5. Store R3 (b) Pipeline timing with delayed load 7 Computer System rchitecture
12 RSC Pipeline xample : Three-segment nstruction Pipeline 3 Suboperations nstruction Cycle» 1) : nstruction fetch» 2) : nstruction decoded and LU operation» 3) : Transfer the output of LU to a register, memory, or PC Delayed ranch : Computer System rchitecture
13 Vector Processing Science and ngineering pplications Long-range weather forecasting, Petroleum explorations, Seismic data analysis, Medical diagnosis, erodynamics and space flight simulations, rtificial intelligence and expert systems, Mapping the human genome, mage processing Vector Operations rithmetic operations on large arrays of numbers Conventional scalar processor» Machine language» Fortran language nitialize = 0 20 Read () Read () Store C() = () + () ncrement = + 1 f 100 go to 20 Continue DO 20 = 1, C() = () + () Vector processor» Single vector instruction C(1:100) = (1:100) + (1:100) Computer System rchitecture
14 9-14 Vector nstruction Format : Operation code DD C 100 Matrix Multiplication ase address source 1 ase address source 2 3 x 3 matrices multiplication : n 2 = 9 inner product a a a a a a a a a b b b b b b c c c» c11 a11 b11 a12 b21 a13 b31 : inner product 9 b b b c c c c c c ase address destination Vector length Cumulative multiply-add operation : n 3 = 27 multiply-add c c a b nitialize C 11 = 0» c c a b a b a : multiply-add b31 9 X 3 multiply-add = 27 Computer System rchitecture
15 9-15 Source Pipeline for calculating an inner product : Floating point multiplier pipeline : 4 segment Floating point adder pipeline : 4 segment C k k» after 1st clock input Source» after 4th clock input Source Source Multiplier pipeline» after 8th clock input dder pipeline Source Source Multiplier pipeline dder pipeline» after 9th, 10th, 11th, Source Multiplier pipeline dder pipeline Source Multiplier pipeline dder pipeline» Four section summation C ,,, Computer System rchitecture
16 9-16 Memory nterleaving : ddress bus Simultaneous access to memory from two or more source using one memory bus system R R R R ven / Odd ddress Memory ccess Memory array Memory array Memory array Memory array DR DR DR DR Supercomputer Supercomputer = Vector nstruction + Pipelined floating-point arithmetic Performance valuation ndex» MPS : Million nstruction Per Second» FLOPS : Floating-point Operation Per Second megaflops : 10 6, gigaflops : 10 9 Cray supercomputer : Cray Research» Clay-1 : 80 megaflops, 4 million 64 bit words memory» Clay-2 : 12 times more powerful than the clay-1 VP supercomputer : Fujitsu» VP-200 : 300 megaflops, 32 million memory, 83 vector instruction, 195 scalar instruction» VP-2600 : 5 gigaflops Data bus Computer System rchitecture
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