EE 435. Lecture 26. Data Converters. Architectures. Characterization

Transcription

1 EE 435 Lecture 26 Data Coverters Architectures Characterizatio

2 . Review from last lecture. Data Coverters Types: A/D (Aalog to Digital) Coverts Aalog Iput to a Digital Output D/A (Digital to Aalog) Coverts a Digital Iput to a Aalog Output A/D is the world s most widely used mixed-sigal compoet D/A is ofte icluded i a FB path of a A/D A/D ad D/A fields will remai hot idefiitely techology advaces make data coverter desig more challegig embedded applicatios desigs ofte very applicatio depedet

3 . Review from last lecture. D/A Coverters DAC C 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7 For this ideal DAC X X b b b b b OUT=X REF b -j OUT=XREF j j=1 2 Number of outputs gets very large for large Spacig betwee outputs is X REF /2 ad gets very small for large

4 . Review from last lecture. A/D Coverters Quatizatio Errors ADC X T1 =X LSB C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0 X LSB 2X LSB 3X LSB 4X LSB 5X LSB 6X LSB 7X LSB ε Q X T1 X T2 X T3 X T4 X T5 X T6 X T7 X REF X -X Q OUT IN X T1 X T2 X T3 X T4 X T5 X T6 X T7 X REF -X LSB Magitude of ε Q bouded by X LSB for a ideal A/D

5 . Review from last lecture. Data Coverter Architectures ADC DAC Nyquist Rate Flash Charge Redistributio Pipelie Two-step ad Multi-Step Iterpolatig Algorithmic/Cyclic Successive Approximatio (Register) SAR Sigle Slope / Dual Slope Subragig Folded Iterleaved Over-Sampled (Delta-Sigma) Discrete-time First-order/Higher Order Cotiuous-time Curret Steerig R-strig Charge Redistributio Algorithmic R-2R (ladder) Pipelied Subragig Discrete-time First-order/Higher Order Cotiuous-time

6 . Review from last lecture. Data Coverter Architectures ADC Flash V REF V IN R R R R Thermometer to Biary Decoder R

7 . Review from last lecture. Data Coverter Architectures ADC Successive Approximatio Register (SAR) C LK V IN V REF DAC DAC Cotroller

8 Data Coverter Architectures Charge Redistributio ADC V ICOMP 1 C 2 C -1 C -2 C C -4 C C C C C C C 0 S 1 f A V X d-1 φb d-1 φb f f A d d -1 φb -1 φb A f A d-2 φb d -2 φ B f A d-3 φb d-3 φb f A d0 φb d 0 φ B f A φ B f A V IN V REF Successive Approximatio Block Redistribute charge with switches to drive Vx to 0 f A t 1 1 ' C C QSAM VIN Ci C 0 VIN V i INC i0 i C Q V d REDIS REF i i i0 2 f B d -1 VCOMP=0 T CONV t VCOMP=1 t Q SAM Q REDIS d -2 T CLK VCOMP=0 1 C V d V C V REF i i IN i0 2 d 1 i IN VREF i i0 2 d 0 VCOMP=1 VCOMP=0 VCOMP=1 t t

9 Data Coverter Architectures Sigle Slope ADC R S R S C LK V REF Itegrator V OUT V IN V E E Biary Couter c Comparator Chages States whe t TR V I V dt I t V IN 0 REF 0 TR REF 0 V IN f CLK Couter stops whe VIN ttrvrefi 0 COUNTTCLK VREFI 0 COUNT VREF I0 If calibrate so that fclk 2 I0 V IN COUNT 2 VREF V IN COUNT 2 V REF

10 Data Coverter Architectures DAC R-Strig V RFF R R S 1 S 2 R V OUT R S N-2 R S N-1 S N is decoded to close oe switch

11 Data Coverter Architectures DAC Curret Steerig V RFF I 1 I 2 I k S 1 S 2 S k R V OUT

12 Data Coverter Architectures DAC R-2R (4-bits) R R R R V OUT 2R 2R 2R 2R R d 3 d 2 d 1 d 0 V REF By superpositio: d V =V d +V d +V d +V d = V V 3 4 k 4-k OUT REF 3 REF 2 REF 1 REF 0 REF 4-k REF k k=0 2 k=1 2 d

13 Data Coverter Architectures Charge Redistributio DAC 1 C 2 C -1 C -2 C C -4 C C C 1 C C 2 2 C C 0 S 1 f A f B d-1 φa d-1 φa f B d-1 φa d-1 φa f B d-2 φ d -2 φ A A f B d d-3 φ -3 φa A f B d0 φa d 0 φ A φ B f A f A V OUT V REF Successive Approximatio Block 1 Q V d C SET REF i i i ' C C QRDIS VOUT Ci C 0 VOUT V i OUTC i0 i0 2 2 f A t Q SET Q RDIS T CONV f B 1 C V d V C V REF i i OUT i0 2 d 1 i OUT VREF i i0 2 t

14 Data Coverter Architectures May more data coverter architectures have bee proposed May are some variat of those listed above Recall: All typically are perfect if compoets are ideal The major oideal effects are usually due to oe of two issues: Matchig performace is ot acceptable Speed is limited by parasitics Most data coverter desig ivolves sequetially idetifyig domiat oideal effect ad developig ways to lower it Importat to observe methods for mitigatig oideal effects as they are ofte used repeatedly With data coverter desig, the devil is i the detail

15 Performace Characterizatio of Data Coverters ADC X DAC IN A very large umber of parameters (2 ) characterize the static performace of a ADC! Ad eve more parameters eeded to characterize the dyamic performace of a ADC A large (but much smaller) umber of parameters are ivariably used to characterize a data coverter Performace parameters of iterest deped strogly o the applicatio Very small umber of parameters of iterest i may/most applicatios Catalog data coverters are geerally iteded to satisfy a wide rage of applicatios ad thus have much more striget requiremets placd o their performace Custom applicatio-specific data coverter will geerally perform much better tha a catalog part i the same applicatio

16 Performace Characterizatio of Data Coverters Static characteristics Resolutio Least Sigificat Bit (LSB) Offset ad Gai Errors Absolute Accuracy Relative Accuracy Itegral Noliearity (INL) Differetial Noliearity (DNL) Mootoicity (DAC) Missig Codes (ADC) Low-f Spurious Free Dyamic Rage (SFDR) Low-f Total Harmoic Distortio (THD) Effective Number of Bits (ENOB) Power Dissipatio

17 Performace Characterizatio of Data Coverters Dyamic characteristics Coversio Time or Coversio Rate (ADC) Settlig time or Clock Rate (DAC) Samplig Time Ucertaity (aperture ucertaity or aperture jitter) Dyamic Rage Spurious Free Dyamic Rage (SFDR) Total Harmoic Distortio (THD) Sigal to Noise Ratio (SNR) Sigal to Noise ad Distortio Ratio (SNDR) Sparkle Characteristics Effective Number of Bits (ENOB)

18 Dyamic characteristics Degradatio of dyamic performace parameters ofte due to oideal effects i time-domai performace Dyamic characteristics of high resolutio data coverters ofte challegig to measure, to simulate, to uderstad source of cotributios, ad to miimize Example: A -bit ADC would ofte require SFDR at the 6+6 bit level or better. Thus, cosiderig a 14-bit ADC, the SFDR would be expected to be at the -90dB level or better. If the iput to the ADC is a 1V p-p siusoidal waveform, the secod harmoic term would 90 db / 20dB eed to be at the 10 32μV level. A 32uV level is about 1part i 30,000. Sigals at this level are difficult to accurately simulate i the presece of a 1V level sigal. For example, covergece parameters i simulators ad sample (strobe) poits used i data acquisitio adversely affect simulatio results ad observig the time domai waveforms that cotribute to oliearity at this level ad relatioships betwee these waveforms ad the sources of oliearity is ofte difficult to visualize. Simulatio errors that are at the 20dB level or worse ca occur if the simulatio eviromet is ot correctly established.

19 Performace Characterizatio of Data Coverters What is meat by low frequecy? Operatio at frequecies so low that further decreases i frequecy cause o further chages i a parameter of iterest Low frequecy operatio is ofte termed Pseudostatic operatio

20 Low-frequecy or Pseudo-Static Performace Paramater Pseudo-Static Regio f

21 Performace Characterizatio of Data Coverters Static characteristics Resolutio Least Sigificat Bit (LSB) Offset ad Gai Errors Absolute Accuracy Relative Accuracy Itegral Noliearity (INL) Differetial Noliearity (DNL) Mootoicity (DAC) Missig Codes (ADC) Low-f Spurious Free Dyamic Rage (SFDR) Low-f Total Harmoic Distortio (THD) Effective Number of Bits (ENOB) Power Dissipatio

22 Performace Characterizatio Resolutio Number of distict aalog levels i a ADC Number of digital output codes i A/D I most cases this is a power of 2 If a coverter ca resolve 2 levels, the we term it a -bit coverter 2 aalog outputs for a -bit DAC 2-1 trasitio poits for a -bit ADC Resolutio is ofte determied by architecture ad thus ot measured Effective resolutio ca be defied ad measured If N levels ca be resolved for a DAC the logn EQ= log2 If N-1 trasitio poits i a ADC, the logn EQ= log2

23 Performace Characterizatio Least Sigificat Bit Assume N = 2 Geerally Defied by Maufacturer to be X LSB =X REF /N Effective Value of LSB ca be Measured For DAC: X LSB is equal to the maximum icremet i the output for a sigle bit chage i the Boolea iput For ADC: X LSB is equal to the maximum distace betwee two adjacet trasitio poits

24 Offset Performace Characterizatio For DAC the offset is (assumig 0 is ideal value of (<0, 0>) (<0,, 0>) - absolute X OUT 0,...,0 X LSB - i LSB X REF Offset C 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7 (If ideal value of (<0, 0>) 0, offset is shift from ideal value at <0, 0>)

25 Offset Performace Characterizatio (for DAC) X REF Offset C 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7 Offset strogly (totally) depedet upo performace at a sigle poit Probably more useful to defie relative to a fit of the data

26 Offset Performace Characterizatio (for DAC) X REF Offset C 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7 Offset relative to fit of data

27 Offset Performace Characterizatio For ADC the offset is X T1 -X LSB X X X T1 LSB LSB C 7 (assumig X LSB is the ideal first trasitio poit) - absolute - i LSB C 6 C 5 C 4 C 3 C 2 C 1 X LSB C 0 X T1 X X REF OFFSET (If ideal first trasitio poit is ot X LSB, offset is shift from ideal)

28 Performace Characterizatio Offset For ADC the offset is C 7 C 6 C 5 C 4 C 3 C 2 C 1 X LSB C 0 X T1 X OFFSET X REF Offset strogly (totally) depedet upo performace at a sigle poit Probably more useful to defie relative to a fit of the data

29 Performace Characterizatio Offset For ADC the offset is C 7 C 6 C 5 C 4 C 3 Fit Lie C 2 C 1 C 0 X LSB X OFFSET X REF Offset relative to fit of data

30 Performace Characterizatio Gai ad Gai Error For DAC X REF Ideal Output Actual Output Gai Error C 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7 Gai error determied after offset is subtracted from output

31 Performace Characterizatio Gai ad Gai Error For ADC C 7 C 6 Actual Output Ideal Output C 5 C 4 C 3 Gai Error C 2 C 1 C 0 X LSB X REF Gai error determied after offset is subtracted from output

32 Ed of Lecture 26

33 Performace Characterizatio Gai ad Offset Errors Fit lie would give better idicator of error i gai but less practical to obtai i test Gai ad Offset errors of little cocer i may applicatios Performace ofte early idepedet of gai ad offset errors Ca be trimmed i field if gai or offset errors exist.

34 Itegral Noliearity (DAC) Noideal DAC X REF C 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7

35 Itegral Noliearity (DAC) Noideal DAC X REF Ed Poit Fit LIe X OF (k) C 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7 X OF X m= N-1 -X 0 OUT OUT N-1 OUT k = mk+ X 0

36 Itegral Noliearity (DAC) Noideal DAC X REF (k)-x OF (k) C 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7 k OUT OF INL = X k -X k INL= max 0kN-1 INL k

37 Itegral Noliearity (DAC) Noideal DAC X REF INL C 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7

38 Itegral Noliearity (DAC) Noideal DAC INL ofte expressed i LSB X REF INL = X k INL= max k - X OUT OF 0kN-1 X LSB INL k k INL C 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7 INL is ofte the most importat parameter of a DAC INL 0 ad INL N-1 are 0 (by defiitio) There are N-2 elemets i the set of INL k that are of cocer INL is almost always omially 0 (i.e. desigers try to make it 0) INL is a radom variable at the desig stage INL k is a radom variable for 0<k<N-1 INL k ad INL k+j are almost always correlated for all k,j (ot icl 0, N-1) Fit Lie is a radom variable INL is the N-2 order statistic of a set of N-2 correlated radom variables

39 Itegral Noliearity (DAC) Noideal DAC X REF INL C 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7 At desig stage, INL characterized by stadard deviatio of the radom variable Closed-form expressios for INL almost ever exist because PDF of order statistics of correlated radom variables is extremely complicated Simulatio of INL very time cosumig if is very large (large sample size required to establish reasoable level of cofidece) Model parameters become radom variables Process parameters affect multiple model parameters causig model parameter correlatio Simulatio times ca become very large INL ca be readily measured i laboratory but ofte domiates test costs because of umber of measuremets eeded whe is large Expected value of INL k at k=(n-1)/2 is largest for may architectures Major effort i DAC desig is i obtaiig acceptable yield!

40 ENOB of DAC Noideal DAC X REF INL C 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7 Cocept of Equivalet Number of Bits (ENOB) is to assess performace of a actual DAC to that of a ideal DAC at a equivalet resolutio level Several differet defiitios of ENOB exist for a DAC Here will defie ENOB as determied by the actual INL performace Will use subscript to defie this ENOB, e.g. ENOB INL

41 ENOB INL of DAC Noideal DAC X REF Premise: A good DAC is ofte desiged so that the INL is equal to ½ LSB. Thus will assume that if a -bit DAC has a INL of ½ LSB that the ENOB INL =. INL C 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7 Thus defie the effective umber of bits, EFF by the expressio INL V REF EFF EFF where INL is i volts 1 EFF VREF ENOBINL log2 1 INL Thus, if a -bit DAC has a INL of ½ LSB VREF 2 V LSB 1 ENOBINL log2 1 log2 1 log2 2 1 INL VLSB 2