Chapter 3. Floating Point Arithmetic

Transcription

1 COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Iterface 5 th Editio Chapter 3 Floatig Poit Arithmetic Review - Multiplicatio = 6 multiplicad 32-bit ALU shift product right multiplier add Cotrol = 5 add add add add = 30 Chapter 3 Arithmetic for Computers 1

2 Review - Divisio = 2 divisor 32-bit ALU shift divided left remaider quotiet subtract Cotrol = sub rem eg, so iet bit = restore remaider sub rem eg, so iet bit = restore remaider sub rem pos, so iet bit = sub rem pos, so iet bit = 1 = 3 with 0 remaider Floatig Poit What ca be represeted i N bits? Usiged 0 to 2 N -1 2 s Complemet - 2 N-1 to 2 N-1-1 But, what about-- Very large umbers? 9,349,398,989,787,762,244,859,087, x Very small umbers? x Fractioal values? 0.35 Mixed umbers? Irratioals? p Chapter 3 Arithmetic for Computers 2

3 Floatig Poit The essetial idea of floatig poit represetatio is that a fixed umber of bits are used (usually 32 or 64) ad that the biary poit "floats" to where it is eeded. Some of the bits of a floatig poit represetatio must be used to say where the biary poit lies. The programmer does ot eed to explicitly keep track of it. IEEE (Istitute of Electrical ad Electroics Egieers) created a stadard for floatig poit. This is the IEEE 754 stadard, released i 1985 ad sice updated i All mai stream hardware ad software follows this stadard. Floatig Poit Floatig Poit provides represetatio for o-itegral umbers. Like scietific otatio, we eed to ormalize I biary ±1.xxxxxxx 2 2 yyyy ormalized ot ormalized This is the represetatio for Types float ad double i C. Chapter 3 Arithmetic for Computers 3

4 Sig ad Magitude Represetatio Sig Expoet Fractio 1 bit 8 bits 23 bits S E F More expoet bits è wider rage of umbers More fractio bits è higher precisio For ormalized umbers, we are guarateed that the umber is of the form 1.xxxx. Hece, i IEEE 754 stadard, the 1 is implicit. IEEE Floatig-Poit Format sigle: 8 bits double: 11 bits S Expoet sigle: 23 bits double: 52 bits Fractio S: sig bit (0 Þ o-egative, 1 Þ egative). Normalize sigificad: 1.0 sigificad < 2.0 Always has a leadig pre-biary-poit 1 bit, so o eed to represet it explicitly. This bit is referred to as the hidde bit. Sigificad is Fractio with the 1. restored. Expoet: excess represetatio: actual expoet + Bias x = (-1) S (1+ Fractio) 2 Esures expoet is usiged. Sigle: Bias = 127; Double: Bias = 1023 (Expoet -Bias) Chapter 3 Arithmetic for Computers 4

5 Sigle-Precisio Rage Expoets ad are reserved for exceptios. Smallest value Expoet: Þ actual expoet = = 126 Fractio: Þ sigificad = 1.0 ± ± Largest value expoet: Þ actual expoet = = +127 Fractio: Þ sigificad 2.0 ± ± Double-Precisio Rage Expoets ad reserved. Smallest value Expoet: Þ actual expoet = = 1022 Fractio: Þ sigificad = 1.0 ± ± Largest value Expoet: Þ actual expoet = = Fractio: Þ sigificad 2.0 ± ± Chapter 3 Arithmetic for Computers 5

6 Floatig-Poit Example What umber is represeted by the sigle-precisio float ? S = 1 Expoet = = 129 Fractio = x = ( 1) 1 ( ) 2 ( ) = ( 1) = 5.0 Floatig-Poit Example What is the FP bit represetatio for ? Represet = ( 1) S = 1 Fractio = Expoet = 1 + Bias Sigle: = 126 = Double: = 1022 = Sigle: Double: Chapter 3 Arithmetic for Computers 6

7 Code Example Degree Coversio MIPS has a secod set of bit registers reserved for floatig poit operatios. float f2c (float fahr) { retur ((5.0/9.0) * (fahr 32.0)); } (argumet fahr is stored i $f12) lwc1 $f16, cost5($gp) lwc1 $f18, cost9($gp) div.s $f16, $f16, $f18 lwc1 $f18, cost32($gp) sub.s $f18, $f12, $f18 mul.s $f0, $f16, $f18 jr $ra Floatig-Poit Additio Additio (ad subtractio) (±F1 2 E1 ) + (±F2 2 E2 ) = ±F3 2 E3 Step 0: Restore the hidde bit i F1 ad i F2. Step 1: Alig fractios by right shiftig F2 by E1 - E2 positios (assumig E1 ³ E2) keepig track of the lower (or higher) order bits shifted out. Step 2: Add the resultig F2 to F1 to form F3. Step 3: Normalize F3 (so it is i the form 1.XXXXX ) - If F1 ad F2 have the same sig, shift F3 ad icremet E3 (check for overflow). - If F1 ad F2 have differet sigs, F3 may require may left shifts each time decremetig E3 (check for uderflow). Step 4: Roud F3 ad possibly ormalize agai. Step 5: Rehide the most sigificat bit of F3 before storig the result. Chapter 3 Arithmetic for Computers 7

8 Floatig-Poit Additio Cosider a 4-digit decimal example Alig decimal poits Shift umber with smaller expoet Add sigificads = Normalize result & check for over/uderflow Roud ad reormalize if ecessary FP Adder Hardware Much more complex tha iteger adder. Doig it i oe clock cycle would take too log Much loger tha iteger operatios. Slower clock would pealize all istructios. FP adder usually takes several cycles Ca be pipelied. Chapter 3 Arithmetic for Computers 8

9 FP Adder Hardware Step 1 Step 2 Step 3 Step 4 Floatig-Poit Multiplicatio Cosider a 4-digit decimal example Add expoets For biased expoets, subtract bias from sum. New expoet = = 5 2. Multiply sigificads = Þ Normalize result & check for over/uderflow Roud ad reormalize if ecessary Determie sig of result from sigs of operads Chapter 3 Arithmetic for Computers 9

10 Deormal Numbers Expoet = Þ hidde bit is 0 x = (-1) S (0+ Fractio) 2 -Bias Deormal umbers are smaller tha ormal umbers. Deormal with fractio = x = (-1) S (0+ 0) 2 -Bias = ±0.0 Two represetatios of 0.0! Ifiities ad NaNs Expoet = , Fractio = ±Ifiity Ca be used i subsequet calculatios, avoidig eed for overflow check. Expoet = , Fractio Not-a-Number (NaN). Idicates illegal or udefied result e.g., 0.0 / 0.0 Ca be used i subsequet calculatios. Chapter 3 Arithmetic for Computers 10

11 Accurate Arithmetic IEEE Std 754 specifies additioal roudig cotrol Extra bits of precisio (guard, roud, sticky). Choice of roudig modes. Allows programmer to fie-tue umerical behavior of a computatio. Not all FP uits implemet all optios Most programmig laguages ad FP libraries just use defaults. Trade-off betwee hardware complexity, performace, ad market requiremets. Roudig (except for trucatio) requires the hardware to iclude extra bits durig calculatios Guard bit used to provide oe bit whe shiftig left to ormalize a result (e.g., whe ormalizig after divisio or subtractio). Roud bit used to improve roudig accuracy. Sticky bit used to support Roud to earest eve; is set to a 1 wheever a 1 bit shifts (right) through it (e.g., whe aligig durig additio/subtractio). x86 FP Istructios Data trasfer Arithmetic Compare Trascedetal FILD mem/st(i) FISTP mem/st(i) FLDPI FLD1 FLDZ FIADDP mem/st(i) FISUBRP mem/st(i) FIMULP mem/st(i) FIDIVRP mem/st(i) FSQRT FABS FRNDINT FICOMP FIUCOMP FSTSW AX/mem FPATAN F2XMI FCOS FPTAN FPREM FPSIN FYL2X Optioal variatios I: iteger operad. P: pop operad from stack. R: reverse operad order. But ot all combiatios allowed. Chapter 3 Arithmetic for Computers 11

12 Subword Parallelism ALUs are typically desiged to perform 64-bit or 128-bit arithmetic. Some data types are much smaller, e.g., bytes for pixel RGB values, half-words for audio samples. Partitioig the carry-chais withi the ALU ca covert the 64-bit adder ito 4 16-bit adders or 8 8-bit adders. A sigle load ca fetch multiple values, ad a sigle add istructio ca perform multiple parallel additios, referred to as subword parallelism. Cocludig Remarks Bits have o iheret meaig Iterpretatio depeds o the istructios applied. Computer represetatios of umbers Fiite rage ad precisio. Need to accout for this i programs. ISA s support arithmetic Siged ad usiged itegers. Floatig-poit approximatio to real umbers. Bouded rage ad precisio Operatios ca overflow ad uderflow. MIPS ISA strogly supports IEEE-754. Chapter 3 Arithmetic for Computers 12