EE 505. CMOS and BiCMOS Data Conversion Circuits

Transcription

1 EE 505 CMOS ad BiCMOS Data Coversio Circuits

2 Course Iformatio: Lecture Istructor: Rady Geiger 2133 Coover Voice: WEB: Laboratory Istructor: TBD

3 Course Iformatio: Aalog VLSI Circuit Desig Course Descriptio: Lecture: MW 2:10-3:30 Rm 1226 Howe Labs: W 8:00 10:50 Rm 2046 Coover Course WEB Site: Theory, desig ad applicatios of data coversio circuits (A/D ad D/A coverters) icludig: architectures, characterizatio, quatizatio effects, coversio algorithms, spectral performace, elemet matchig, desig for yield, ad practical comparators, implemetatio issues.

4 Course Iformatio: Key Referece Texts: Data Coverters, Maloberti, Spriger, 2007 Aalog-to-Digital Coversio 3 rd Editio by Marcel Pelgrom, Spriger, 2016

5 Course Iformatio: Other Referece Texts: Advaced Data Coverters by G. Magaaro, Cambridge, 2012 CMOS Itegrated Aalog-to-Digital ad Digital-to-Aalog Coverters 2 d Editio by Rudy va de Plassche, Kluwer, 2003

6 Course Iformatio: Other Referece Texts: Priciples of Data Coversio System Desig by B. Razavi, IEEE Press, 1995 High Speed Data Coverters by A. Ali, IET, 2016

7 Course Iformatio: Other Referece Texts: CMOS Mixed-Sigal Circuit Desig, 2 d Editio, R. Jacob Baker, Wiley, 2008

8 Course Iformatio: Other Referece Texts: Data Coversio Hadbook by Aalog Devices, 2005 The Art of Aalog Layout by A. Hastigs, Pretice Hall, 2001

9 Course Iformatio: Other Referece Texts: Uderstadig Delta-Sigma Data Coverters by R. Schreier ad G. Temes, Wiley, 2005 by Pava, Schreier ad Temes, Wiley, 2017 Delta-Sigma Data Coverters Theory, Desig, ad Simulatio edited by S. Norsworthy, R. Schreier ad G. Temes, Wiley, 1997

10 Course Iformatio: Referece Texts: Oversamplig Delta-Sigma Data Coverters: Theory, Desig, ad Simulatio 1st Editio By Cady ad Temes, CMOS Aalog Circuit Desig by Alle ad Holberg, Oxford, 2011.

11 Course Iformatio: Referece Texts: CMOS: Circuit Desig, Layout, ad Simulatio Secod Editio by J. Baker, Wiley, Fudametals of Microelectroics by B. Razavi, McGraw Hill, 2008

12 Course Iformatio: Referece Texts: Desig of Aalog CMOS Itegrated Circuits 2 d editio by B. Razavi, McGraw Hill, 2016 Aalysis ad Desig of Aalog Itegrated Circuits-Fifth Editio Gray,Hurst,Lewis ad Meyer, Wiley, 2009 Aalog Itegrated Circuit Desig -2 d Editio by D. Johs ad K. Marti, Wiley, 2011

13 Referece Materials: Course Iformatio:

14 Course Iformatio: Gradig: Poits will be allocated for several differet parts of the course. A letter grade will be assiged based upo the total poits accumulated. The poits allocated for differet parts of the course are as listed below: 1 Exam 100 pts 1 Fial 100 pts. Homework 100 pts.total Lab ad Lab Reports 100 pts.total Desig Project 100 pts. Note: I the evet that oe of the exams is ot give, the weight of the remaiig exam will be icreased to somewhere betwee 100 pts ad 200 pts.

15 Course Iformatio: Desig Project: The desig project will be assiged by mid-term. Additioal details about the desig project will be give after relevat material is covered i class. The optio will exist to have this project fabricated through the MOSIS program. The desig should be ready for fabricatio ad post-layout simulatios are to be icluded as a part of the project.

16 Course Iformatio: I ecourage you to take advatage of the system o campus to commuicate about ay issues that arise i the course. I typically check my e- mail several times a day. Please try to iclude EE 505" i the subject field of ay message that you sed so that they stad out from what is ofte large volumes of routie messages.

17 Topical Coverage Data Coverter Operatio, Characterizatio ad Specificatios Trasfer Characteristics Noise Spectral characterizatio Compoet Matchig ad Yield Nyquist-Rate Data Coverter Desig DACs Architectures Buildig Blocks Aalysis, Simulatio, ad Yield ADCs Architectures Buildig Blocks Aalysis, Simulatio, ad Yield Over-Sampled Data Coverters Operatio Architectures Buildig Blocks

18 Sigals Types of sigals: Cotiuous amplitude vs discrete amplitude Cotiuous time vs discrete time Fiite resolutio vs ifiite resolutio Probability of ay cotiuous-amplitude sigal value beig exactly equal to a specific value is 0 Probability of ay time beig exactly equal to a specific time value is 0 If x is a cotiuous variable (time, voltage, curret,.) the i the cotext of data coverters, there is o distictio i the followig sets of umbers (x 1,x 2 ) [x 1,x 2 ] (x 1,x 2 ] [x 1,x 2 ) It may be more coveiet to iclude boudary poits whe usig programs such as Matlab to characterize data coverters but results should ot deped upo whether ed poits are icluded or excluded

19 Sigals Digital represetatios (may exist) uary (thermometer), biary, decimal, gray (RBC),BCD, hexadecimal, I the cotext of data coverters, the digital represetatio is almost always represeted by sets whose elemets are {0,1} Biary ad occasioally uary are ivariable the codes that are used whe buildig ADCs ad DACs Uless specifically stated to the cotrary, it will be assumed throughout this course that the iput or output codes i a data coverter are biary

20 Types: Data Coverters A/D (Aalog to Digital) Coverts Aalog Iput to a Digital Output D/A (Digital to Aalog) Coverts a Digital Iput to a Aalog Output A/D is the world s most widely used mixed-sigal compoet D/A is ofte icluded i a FB path of a A/D A/D ad D/A fields will remai hot idefiitely techology advaces make data coverter desig more challegig embedded applicatios desigs ofte very applicatio depedet

21 Data Coverters Data coverters are ratio-metric devices ad outputs are all relative to a referece (i.e. traceability to a primary or secodary stadard is ot a issue) Ca be thought of as a amplifier where the output is a ratio-metric versio of the iput Uits of output of ADC are dimesioless ad uits of iput to DAC are dimesioless Uits of iput to ADC ca be arbitrary ad uits of output of DAC ca be arbitrary

22 The comparator is the basic aalog to digital coversio elemet i all ADCs The switch is the basic digital to aalog coversio elemet i all DACs Data coverters icorporate oe or more basic ADC or DAC cells Desig of comparator or switch is ofte critical i data coverters Performace of data coverters ofte depedet upo performace of comparator, switch, ad matchig Data Coverters Electroic Data Coversio Process: V d V OUT d d V OUT V OUT V OXX 0 d V OUT V XX 0 d 1 V d ADC DAC

23 D/A Coverters Basic structure: DAC X REF Basic structure with differetial outputs:: XIN DAC X + OUT X - OUT X + REF X - REF

24 D/A Coverters Notatio: DAC DAC X REF DAC X REF Referece always exists eve i ot explicitly show

25 D/A Coverters DAC (assumig biary codig) =<b -1,b -1,...b 1,b 0> b 0 is the Least Sigificat Bit (LSB) b -1 is the Most Sigificat Bit (MSB) Note: some authors use differet idex otatio A Ideal DAC is characterized at low frequecies by its static performace

26 D/A Coverters DAC =<b -1,b -1,...b 1,b 0> A Ideal DAC trasfer characteristic (3-bits) (Nyquist Rate) X - REF <0 0 0> <0 0 1> <0 1 0> <0 11> <1 0 0> <1 010> <1 1 0> <1 1 1> C 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7 Code C k is used to represet the decimal equivalet of the biary umber <b -1.. b 0 )>

27 D/A Coverters DAC =<b -1,b -1,...b 1,b 0> A Ideal DAC trasfer characteristic (3-bits) X REF 7 X REF 8 C 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7

28 D/A Coverters =<b -1,b -1,...b 1,b 0> DAC A Ideal DAC trasfer characteristic (3-bits) X - REF C 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7 All poits of this ideal DAC lie o a straight lie

29 D/A Coverters DAC C 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7 Most D/A ideally have a liear relatioship betwee biary iput ad aalog output Output represets a discrete set of cotiuous variables Typically this umber, N, is a itegral power of 2, i.e. N=2 is always dimesioless could have may differet dimesios A ideal oliear characteristic is also possible (waveform geeratio ad compadig) Will assume a liear trasfer characteristic is desired uless specifically stated to the cotrary

30 D/A Coverters DAC C 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7 For this ideal DAC b b b b b X =X b-j =XREF j OUT REF -1 j=1 Number of outputs gets very large for large Spacig betwee outputs is X REF /2 ad gets very small (relative to X REF ) for large

31 D/A Coverters DAC X REF X LSB X REF 2 C 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7 Ideal steps all equal ad termed the LSB X LSB gets very small for small X REF ad large e.g. If X REF =1V ad =16, the N=2 16 =65,536, X LSB =15.25μV

32 D/A Coverters DAC A alterate ideal 3-bit DAC C 0 C 1 C 2 C 3 C4 C5 C6 C7 Irrespective of which form is cosidered, the icremet i the output for oe Boolea bit chage i the iput is X LSB ad the total rage is 1LSB less tha X REF

33 Applicatios of DACs Waveform Geeratio Voltage Geeratio Aalog Trim or Calibratio Idustrial Cotrol Systems Feedback Elemet i ADCs.

34 Waveform Geeratio with DACs Ramp (Saw-tooth) Geerator Period CLK Geerator -bit Biary Couter D/A A Example: For =3 X REF X REF t Example: For large X REF t

35 Waveform Geeratio with DACs Sie Wave Geerator Period CLK Geerator -bit Biary or Couter D/A A m ROM RAM Example: For =3 X REF X REF t Distortio of the desired waveforms occurs due to both time ad amplitude quatizatio Ofte a filter precedes or follows the buffer amplifier to smooth the output waveform

36 A/D Coverters Basic structure: ADC X REF Iput rage is X REF Basic structure with differetial iputs/refereces: ADC X + IN ADC X - IN X + REF X - REF Iput rage is X + REF - X - REF X + REF X - REF Typically Iput rage is 2(X + REF - X - REF)

37 A/D Coverters Notatio: ADC ADC X REF ADC X REF Referece always exists eve i ot explicitly show

38 A/D Coverters (assumig biary codig) ADC =<d -1,d -2,...d 0> d 0 is the Least Sigificat Bit (LSB) d -1 is the Most Sigificat Bit (MSB) A Ideal ADC is characterized at low frequecies by its static performace

39 A/D Coverters A Ideal ADC trasfer characteristic (3-bits) (Nyquist Rate) ADC =<d -1,d -2,...d 0> C 7 <1 1 1> X LSB X = 2 REF C 6 <1 1 0> C 5 <1 01> C 4 C 3 <1 0 0> <0 11> X LSB C 2 <0 1 0> C 1 C 0 <0 0 1> <0 0 0> X REF X REF -X LSB

40 A/D Coverters A Ideal ADC trasfer characteristic (3-bits) ADC =<d -1,d -2,...d 0> X REF X LSB X = 2 REF 7X LSB C 7 6X LSB C 6 5X LSB C 5 4X LSB 3X LSB C 4 C 3 X LSB 2X LSB C 2 X LSB C 1 C 0 X REF -X LSB X REF The secod vertical axis, labeled is the iterpreted value of

41 A/D Coverters ADC C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0 For this ideal ADC d-1 d-2 d-3 d1 d X 0 OUT= XREF X - X = ε OUT IN where ε is small (typically less tha 1LSB) d -j XIN= XREF - ε j j=1 2 Number of bis gets very large for large Spacig betwee break poits is X REF /2 ad gets very small for large X REF ε is the quatizatio error ad is iheret i ay ADC

42 A/D Coverters ADC C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0 Trasitio Poits X T1 X T2 X T3 X T4 X T5 X T6 X T7 X REF Actual values of where trasitios occur are termed trasitio poits or break poits For a ideal -bit ADC, there are 2-1 trasitio poits Ideally the trasitio poits are all separated by 1 LSB -- X LSB =X REF /2 Ideally the trasitio poits are uiformly spaced I a actual ADC, the trasitio poits will deviate a little from their ideal locatio Labelig Covetio: We will defie the trasitio poit X Tk to be the break poit where the trasitio i the code output to code C k occurs. This seemigly obvious orderig of break poits becomes ambiguous, though, whe more tha oe break poits cause a trasitio to code C k which ca occur i some oideal ADCs

43 A/D Coverters Quatizatio Errors ADC A ideal ADC C 7 C 6 X T1 =X LSB C 5 C 4 C 3 C 2 C 1 C 0 X LSB 2X LSB 3X LSB 4X LSB 5X LSB 6X LSB 7X LSB Q XOUT -XIN ε Q X T1 X T2 X T3 X T4 X T5 X T6 X T7 X REF X T1 X T2 X T3 X T4 X T5 X T6 X T7 X REF -X LSB Magitude of ε Q bouded by X LSB for 0< X LSB < X REF

44 A/D Coverters Quatizatio Errors ADC Aother Ideal ADC X T1 =X LSB /2 C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0 X LSB 2X LSB 3X LSB 4X LSB 5X LSB 6X LSB 7X LSB Q XOUT -XIN X T1 X T2 X T3 X T4 X T5 X T6 X T7 ε Q X REF X T1 X T2 X T3 X T4 X T5 X T6 X T7 X REF Magitude of ε Q bouded by ½ X LSB

45 A/D Coverters ADC C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0 Quatizatio Errors X REF d d d d d ε = Q XREF -1 XIN The oly way to reduce p-p quatizatio errors is to icrease umber of levels A lower boud o the quatizatio errors i 0 < < X REF is ±½ X LSB The static performace of a ADC is completely determied by the fiite sequece of the trasitio poits < X T1, X T1 >

46 A/D Coverters May types: Successive Approximatio Register (SAR) Pipelied Sigma-Delta Flash Sigle-slope Dual-slope Wide rages of performace: Speed Resolutio Power Cost Large umber of vedors of catalog parts: Texas Istrumets Aalog Devices (Liear Techology) Maxim Embedded applicatios probably much larger: May SoCs cotai a large umber of data coverters of with varyig performace

47 A/D Coverters What types are really used? Cosider catalog parts from oe vedor Aalog Devices (Ja 2017) Flash 2 SAR 233 Pipelied 242 Sigma-Delta 81 Total 559

48 What do ADCs cost?

49 What do ADCs cost? Resolutio? 3 bits to 24 bits (oe at 32 bits)

50 $2.58 i 1000 s

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52 $120 i 1000 s

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56 Performace Characterizatio of Data Coverters ADC DAC A large umber of parameters are used to characterize a data coverter Performace parameters of iterest deped strogly o the applicatio Very small umber of parameters of iterest i may/most applicatios Catalog data coverters are geerally iteded to satisfy a wide rage of applicatios ad thus have much more striget requiremets placd o their performace Custom applicatio-specific data coverter will geerally perform much better tha a catalog part i the same

57 Performace Characterizatio of Data Coverters Static characteristics Resolutio Least Sigificat Bit (LSB) Offset ad Gai Errors Absolute Accuracy Relative Accuracy Itegral Noliearity (INL) Differetial Noliearity (DNL) Mootoicity (DAC) Missig Codes (ADC) Quatizatio Noise Low-f Spurious Free Dyamic Rage (SFDR) Low-f Total Harmoic Distortio (THD) Effective Number of Bits (ENOB) Power Dissipatio

58 Performace Characterizatio of Data Coverters Dyamic characteristics Coversio Time or Coversio Rate (ADC) Settlig time or Clock Rate (DAC) Samplig Time Ucertaity (aperture ucertaity or aperture jitter) Dyamic Rage Spurious Free Dyamic Rage (SFDR) Total Harmoic Distortio (THD) Sigal to Noise Ratio (SNR) Sigal to Noise ad Distortio Ratio (SNDR) Sparkle Characteristics Effective Number of Bits (ENOB)

59 Dyamic characteristics Degradatio of dyamic performace parameters ofte due to oideal effects i time-domai performace Dyamic characteristics of high resolutio data coverters ofte challegig to measure, to simulate, to uderstad source of cotributios, ad to miimize Example: A -bit ADC would ofte require SFDR at the 6+6 bit level or better. Thus, cosiderig a 14-bit ADC, the SFDR would be expected to be at the -90dB level or better. If the iput to the ADC is a 1V p-p siusoidal waveform, the secod harmoic term would eed to be at the 90 db / 20dB 10 32μV level. A 32uV level is about 1part i 30,000. Sigals at this level are difficult to accurately simulate i the presece of a 1V level sigal. For example, covergece parameters i simulators ad sample (strobe) poits used i data acquisitio adversely affect simulatio results ad observig the time domai waveforms that cotribute to oliearity at this level ad relatioships betwee these waveforms ad the sources of oliearity is ofte difficult to visualize. Simulatio errors that are at the 20dB level or worse ca occur if the simulatio eviromet is ot correctly established.

60 Characterizatio of Data Coverter Performace Almost all ADC architectures will work perfectly if oideal effects are igored!! Most data coverter desig effort ivolves maagig oideal properties of compoets Devil is ofte i the detail whe desigig a ADC Critical to kow how to accurately characterize a ADC What may appear to be mior differeces i performace are ofte differetiators i both the marketplace ad i the profit potetial of a part

61 Performace Characterizatio of Data Coverters What is meat by low frequecy? Operatio at frequecies so low that further decreases i frequecy cause o further chages i a parameter of iterest Low frequecy operatio is ofte termed Pseudostatic operatio

62 Low-frequecy or Pseudo-Static Performace Parameter Pseudo-Static Regio f

63 Performace Characterizatio Resolutio Number of distict aalog levels i a ADC Number of digital output codes i A/D I most cases this is a power of 2 If a coverter ca resolve 2 levels, the we term it a -bit coverter 2 aalog outputs for a -bit DAC 2-1 trasitio poits for a -bit ADC Resolutio is ofte determied by architecture ad thus ot measured Effective resolutio ca be defied ad measured If N levels ca be resolved for a DAC the logn EQ= log2 If N-1 trasitio poits i a ADC, the logn EQ= log2

64 Performace Characterizatio Least Sigificat Bit Assume N = 2 Geerally Defied by Maufacturer to be X LSB =X REF /N Effective Value of LSB ca be Measured For DAC: X LSB is equal to the maximum icremet i the output for a sigle bit chage i the Boolea iput For ADC: X LSB is equal to the maximum distace betwee two adjacet trasitio poits

65 Ed of Lecture 1