Lesson 1. The datapath

Transcription

1 Lesso. Computers Structure ad Orgaizatio Graduate i Computer Scieces / Graduate i Computers Egieerig Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig Automatic Departmet Lesso : Cotets Slide: 2 / 5 ALU structure ad implemetatio ALUs circuits ad algorithms Logic ad shifts operators Siged operatios Fixed poit add Floatig poit add Guard digits Roudig methods Iteger multiply ad divide operatios Floatig poit multiply ad divide operatios ALU ad vo Neuma architecure: datapath ad fuctioal uits MC68 executio uit Bibliography Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig

2 Lesso : ALU STRUCTURE AND IMPLEMENTATION (I) Slide: 3 / 5 ARITHMETIC-LOGIC UNIT (ALU): is a set of avaiable operators i the computer Made of: Arithmetic, logic ad shift operators Registers for storig temporal data Flag register Program couter register Iterrupt addresses register ALU types: Fixed Poit Floatig Poit Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig Lesso : Estructura e implemetació de la ALU (y II) Slide: 4 / 5 Operators classificatio: Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig

3 Lesso : ALU circuits ad algorithm (I) Shifts operatios(i) Slide: 5 / 5 Logic shifts: Right / Left zero itroductio. It does t deped o the represetatio system Last bit of the shift operatio is copied o the carry flag Left shift Right shift Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig Lesso : ALU circuits ad algorithm (II) Shifts operatios (II) Slide: 6 / 5 Arithmethic shifts: These operatios are equivalet at multiply or divide by powers of two. Represetatio system must be take ito accout Last bit of the shift operatio is copied to the carry flag Complemet 2 left arithmetic shift Complemet 2 Right arithmetic shift Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig

4 Lesso : ALU circuits ad algorithm (III) Shifts operatios(iii) Slide: 7 / 5 Rotatio operatio / Rotatio throught carry flag operatio: Bits of the ed / begiig come ito the begiig / ed of the register i a circular way. If the rotatio is throught the crry flag, this bit is also take ito accout to perform the operatio Last bit of the rotatio operatio is copied i the carry flag Left rotatio Right rotatio Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig Lesso : ALU circuits ad algorithms (V) Logic operatios (I) Slide: 8 / 5 Logic operatios are performed o each idividual bit of the operads OR XOR a b a + b a b a b a b a OR b a b a XOR b Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig

5 Lesso : ALU circuits ad algorithms (VI) Logic operatios (ad II) Slide: 9 / 5 AND NOT a b a * b a a a b a AND b a a Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig Lesso : ALU circuits ad algorithms (VII) Atirhmetic operatios (I) Slide: / 5 Siged operatio. Chage Sig Magitude Complemet 2 E a - a -2,..., a a - a -2 a a E a* - a -2,..., a... Complemet a* - a* -2 a* a* E a -, a -2,..., a... a* -, a* -2,..., a* Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig

6 Lesso : ALU circuits ad algorithms (VIII) Atirhmetic operatios (II) Slide: / 5 Siged operatio. Sig extetio To fill empty bits whe data pass from less bits to more bits elemets. Sig Magitude Complemet ad 2 Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig Lesso : ALU circuits ad algorithms (IX) Atirhmetic operatios (III) Slide: 2 / 5 ADD: the add operatio is the most importat operatio. It s used to: To calculate ext istructio addresses To calculate operads addresses It s employed by multiply ad divide operatios Elemetal bit adder A i B i Si = Ai Bi Ci- Ci = Ai Bi + Bi Ci- + Ai Ci- C i- S i C i Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig

7 Lesso : ALU circuits ad algorithms (X) Atirhmetic operatios (IV) Slide: 3 / 5 Carry propagatio adder of bits by usig bit full adders Drawbacks: Very slow adder. Carry must be propagate from the firs adder to the fial oe to get the result of the operatio. Delay of 2 r (maximu level gates to pass throught) N is the umber of adders R is the delay of each gate Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig Lesso : ALU circuits ad algorithms (XI) Atirhmetic operatios (V) Slide: 4 / 5 Iteger add aceleratio: Additioal circuits are added to aticipate to ed carry calculus Geeratio fuctio (g i = a i b i ) Propagatio fuctio (p i = a i b i ) Output carry (c i+ = g i + p i c i- ) Problem: variable fa-i Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig

8 Lesso : ALU circuits ad algorithms (XII) Atirhmetic operatios (VI) Slide: 5 / 5 Iteger add acceleratio: To homogeise fa-i by usig 4 bits full adders such as basic compoet Block Geeratio ad Propagatio fuctios must be defied E.g. 6 bits Look-ahead adder Block level fuctios P = p 3 p 2 p p G = g 3 +(g 2 p 3 )+(g p 3 p 2 )+(g p 3 p 2 p ) C = G + P c e C 2 = G + (G P ) + (c e P P ) Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig Lesso : ALU circuits ad algorithms (XIII) Atirhmetic operatios (VII) Slide: 6 / 5 Iteger add acceleratio. Carry Skip Adder (CSK) It s betwe a full adder ad a look ahead oe. Oly calculate Pi (it s easyer). K bits Carry Skip Adder: First full adder: 2k + (plus oe level) Number of gates: 2(/k-2) Last full adder: 2k Total: levels umber= 4k + 2/k -3 E.g. = 2, K = 4 um. Niveles = 23 Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig

9 Lesso : ALU circuits ad algorithms (XIV) Atirhmetic operatios (VIII) Slide: 7 / 5 Iteger add acceleratio. Carry select It s eeded to duplicate hardware items. Add with ad carry-i is paralel performed. Whe the correct carry is kow, right result is selected via multipexors. Sumador Sumador S umador S um ador S umador Mult ipl ex or Sumador Sumador Multiplex or T + 2tp Sumador M ul tiplexor S umador Mult iplexor T + 4t p T + 6tp Supoiedo bloques de k bits T3 = M xi mo(tiempo del m ul tiplexor, 2t p) T2 = T + 2á(/k -2)átp (co / k et apas exluidos el primero y el œltim o sumador) T= (2ák + )átp Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig Lesso : ALU circuits ad algorithms (XV) Atirhmetic operatios (IX) Slide: 8 / 5 Differet Adders time ad space required Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig

10 Lesso. Computers Structure ad Orgaizatio Graduate i Computer Scieces / Graduate i Computers Egieerig Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig Achademic course 2-22 Automatic Departmet Lesso : Cotets Slide: 2 / 5 ALU structure ad implemetatio ALUs circuits ad algorithms Logic ad shifts operators Siged operatios Fixed poit add Floatig poit add Guard digits Roudig methods Iteger multiply ad divide operatios Floatig poit multiply ad divide operatios ALU ad vo Neuma architecure: datapath ad fuctioal uits MC68 executio uit Bibliography Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig

11 Lesso : ALU circuits ad algorithms (XVI) Atirhmetic operatios (X) Slide: 2 / 5 Multiplicatio. Add-Shift algorithm (A x B) Iitiate P = B Oly usiged umbers Multiplicad Multiplexor bit + bits Shift register P P reloj Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig Lesso : ALU circuits ad algorithms (XVII) Atirhmetic operatios (XI) Slide: 22 / 5 E..g. A = y B = Multiplexor bit + bits reloj Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig

12 Lesso : Slide: 23 / 5 ALU circuits ad algorithms (XVIII) Atirhmetic operatios (XII) E.g. A = y B = Multiplexor bit + bits reloj Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig Lesso : ALU circuits ad algorithms (XIX) Atirhmetic operatios (XIII) Slide: 24 / 5 E.g. A = y B = Multiplexor bit + bits reloj Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig

13 Lesso : ALU circuits ad algorithms (XX) Atirhmetic operatios (XIV) Slide: 25 / 5 E.g. A = y B = Multiplexor bit + bits reloj Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig Lesso : ALU circuits ad algorithms (XXI) Atirhmetic operatios (XV) Slide: 26 / 5 E.g. A = y B = Multiplexor bit + bits reloj Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig

14 Lesso : ALU circuits ad algorithms (XXII) Atirhmetic operatios (XVI) Slide: 27 / 5 E.g. A = y B = Multiplexor bit + bits reloj Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig Lesso : Slide: 28 / 5 ALU circuits ad algorithms (XXIII) Atirhmetic operatios (XVII) E.g. A = y B = Multiplexor bit + bits reloj Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig

15 Lesso : Slide: 29 / 5 ALU circuits ad algorithms (XXIV) Atirhmetic operatios (XVIII) E.g. A = y B = Multiplexor bit + bits reloj Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig Lesso : ALU circuits ad algorithms (XXV) Atirhmetic operatios (XIX) Slide: 3 / 5 E.g. A = y B = Multiplexor bit + bits reloj Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig

16 Lesso : ALU circuits ad algorithms (XXVI) Atirhmetic operatios (XX) Slide: 3 / 5 Complemet ad complemet 2 adjusts for the algorithm Complemet 2: if B is a egative umber, Subtract A whe last bit arrives to multiplexor. Complemet :if B is a egative umber, Subtract A whe last bit arrives to multiplexor. Moreover, P must be iitiated to A istead of. Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig Lesso : Slide: 32 / 5 ALU circuits ad algorithms (XXVII) Atirhmetic operatios (XXI) Multiplicatio. Booth Algorithm (C2) For avoidig zero additios. These adds operatios oly cosume clock cycles because operad is oly shifted Search s ad s strigs to code the multiplier ad powerig by the power of them A =, B = A x B = +Ax2 3 Ax2 + Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig

17 Lesso : Slide: 33 / 5 ALU circuits ad algorithms (XXVIII) Atirhmetic operatios (XXII) Divisio. Usiged With Remaider Restoratio Divisio Algorithm Startig poit: Take as may bits of the divided as the divisor has. Divided ad divisor must be usiged Add complemet 2 of the divisor to the divided If positive: Take a ew bit of the divided Write a i the quotiet If egative: Add divisor to divided agai or restore previous value from a register Take a ew bit of the divided Write a i the quotiet Repeat the process util we have o more divided bits to take If fial quotiet is egative the restore it Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig Lesso : Slide: 34 / 5 ALU circuits ad algorithms (XXIX) Atirhmetic operatios (XXIII) Divisio. Usiged With Remaider Restoratio Divisio Algorithm A =, B =, Quotiet =, Remaider = + + Restauració + + Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig

18 Lesso : ALU circuits ad algorithms (XXX) Atirhmetic operatios (XXIV) Slide: 35 / 5 Divisio. Usiged Without Remaider Restoratio Divisio Algorithm Startig poit: Take as may bits of the divided as the divisor has Divided ad divisor must be usiged Add complemet 2 of the divisor to divided If positive: Take a ew bit of the divided Write a i the quotiet If egative: Add the divisor to the last result Take a ew bit of the divided Write a i the quotiet Repeat util we have o more divided bits If the fial quotiet is egative the restore it. Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig Lesso : ALU circuits ad algorithms (XXXI) Atirhmetic operatios (XXV) Slide: 36 / 5 Divisio. Usiged Without Remaider Restoratio Divisio Algorithm A =, B =, Quotiet=, Remaider= Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig

19 Lesso : Slide: 37 / 5 ALU circuits ad algorithms (XXXII) Atirhmetic operatios (ad XXVI) Floatig poit multiplicatio ad divisio Use fixed poit algorithms Algorithms are applied to matissas Expoet are added (multiplicatio) or subtract (divisio) Result of the operatio must be ormalized ad rouded It s possible to employ guard digits to improve the accurate of the result Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig Lesso : Slide: 38 / 5 ALU circuits ad algorithms (XXXIII) Circuits (I) Biary Subtract-Adder a 7 a 6 a 5 a 4 a 3 a 2 a a b 7 b 6 b 5 b 4 b 3 b 2 b b S/R C - C - CF + Overflow = c S _ R S Sig-Magitude Subtract-Adder Uses a biary subtract-adder ad a siged circuit is eeded to determie operatio Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig

20 Lesso : Slide: 39 / 5 ALU circuits ad algorithms (XXXIV) Circuits (II) Complemet 2 Subtract-Adder a 7 a 6 a 5 a 4 a 3 a 2 a a b 7 b 6 b 5 b 4 b 3 b 2 b b S/R C - C - CF + S Overflow = c c 2 Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig Lesso : Slide: 4 / 5 ALU circuits ad algorithms (XXXV) Circuits (III) Complemet Subtract-Adder a 7 a 6 a 5 a 4 a 3 a 2 a a b 7 b 6 b 5 b 4 b 3 b 2 b b S/R C - C - + S CF Overflow = c c 2 Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig

21 Lesso : Slide: 4 / 5 ALU circuits ad algorithms (XXXVI) Circuits (IV) Excess Subtract-Adder Result operatio adjust is eeded: If ADD operatio subtract M If SUBTRACT operatio add M IF M = 2 - is easy: º Most Sigificat Bit must be iverted for each operad 2º ADD or SUBTRACT as Complemet 2 represeted operads 3º Ivert Most Sigificat Bit of the result Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig Lesso : Slide: 42 / 5 ALU circuits ad algorithms (XXXVII) Circuits (ad V) BCD Subtract-Adder Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig

22 Lesso : Slide: 43 / 5 ALU circuits ad algorithms (XXXIX) FLOATING POINT ADDITION-SUBTRACTION (I) How to Add-Subtract Floatig Poit Number Algorithm:. Split matissas ad expoets 2. Compare expoets ad: Keep greatest expoet. It will be the result expoet except if result must be ormalized Subtract both expoets ad take the absolute value. It will be the umber of lowest matissa right shift required 3. matissas alig is required by right shiftig the lower oe 4. Add or subtract aliged matissas 5. Check if result is ormalized. If ot, ormalize it. 6. Roud the result if required Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig Lesso : Slide: 44 / 5 ALU circuits ad algorithms (XXXX) FLOATING POINT ADDITION-SUBTRACTION (ad II) Floatig poit additio example: Lets A ad B floatig poit represeted umbers. Excess 2 - expoet (8 bits) matissa (8 bits to), complemet 2, ormalized ad without implicit bit expressed EA = MA = EB = MB = Expoets comparatio EA(4) > EB(3). Result expoet EA Shift MB EA-EB times, 4 3 = + ER = MR = Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig

23 Lesso : ALU circuits ad algorithms (XXXXI) Guard Digits Slide: 45 / 5 Guard Digits are oly added ad used iside Arithmetic-Logic Uit Guard Digits are used for helpig i roudig ad ormalizig umbers ad icreasig the accurate of operatios. Usually, two guard digits ad oe sticky bit are added to the ed of the operads. b 8 b 7 b 6 b 5 b 4 b 3 b 2 b b b g b g2 b r Bits b 8 to b are 8 bits data bits b g first guard digit used for ormalizatio purposes b g2 secod guar digit employed i roudig techiques b r the sticky bit. Keep a oe if durig shift phases a oe pass through it i order of avoid accurate losig i subtract operatios Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig Lesso : Slide: 46 / 5 ALU circuits ad algorithms (XXXXII) Roudig Methods Guard digits ad sticky bit must be removed whe passig from ALU to computer register or memory positios. These iformatio must be take ito accout before removig. Most frequet roudig techiques are the followig: Trucatio: guard digits ad sticky bits are removed. LSB forced to : guard digits ad sticky bit are removed ad the least sigificat bit of the operad is forced to. Nearest roudig: It s the more difficult to implemet but the oe which better results obtai. If digits are above the half of combiatio the trucate ad add oe. If digits are bellow the half of combiatio trucate. If digits are exactly i the half trucate ad add the LSB to the LSB 3 guar digits:,,, trucate., y trucate ad add. Fially add if LSB s or trucate if LSB is Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig

24 Lesso : Slide: 47 / 5 ALU ad Vo Neuma s Architecure (I) The Datapath vo Neuma arithmetic uit is called the data path It s composed of arithmetic-logic uits, shifters, registers ad buses to commuicate them Flags register belogs to the data path Program couter register (PC) ad Iterrupt Addresses register also belogs to the data path Data path determies the cost of the processor. It requires the half of the umber of trasistors ad the half i the silico area of the processor Data path is the bottleeck of the processor because the slowest circuits determie the time clock cycle Keys to desig the data path: Choose the umber ad port umbers for the register bak Choose the type of ALU or ALUs tu be icluded Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig Lesso : Slide: 48 / 5 ALU ad Vo Neuma s Architecure (II) The Flag Register. There are flip-flop related to the result of the arithmetic ad logic operatio performed i the computer. All of them are collected i oe register called the Flags Register The aim of the flag register is to show some importat characteristics of the operatio results. Most frequet flags are: Zero, Siged, Overflow ad Carry Parity, Auxiliar Carry, Trap, Iterrupt Eable, Exceptio coditios. Some of them are based o the cotet of the flags register. E.g. overflow, parity memory error, Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig

25 Lesso : Slide: 49 / 5 Ejemplo de hardware real (I) Alpha 264. Aceleració de la suma (I) Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig Lesso : Slide: 5 / 5 Ejemplo de hardware real (II) Alpha 264. Aceleració de la suma (y II) Alpha 264 iteger ad floatig poit adder is a 64 bits adder which performs to add per clock cycle. It s two segmeted stages. Three methods are combied: 8 bits full adders Carryselct i 2 blocks of 32 bits 32 bits blocks carry look ahead Latches are used to keep temporal results betwee phases Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig

26 Lesso : Slide: 5 / 5 Bibliography Estructura y diseño de computadores David A. Patterso y Joh L. Heessy. Reverté, 2 Capítulo 4 Arquitectura de computadores. U efoque cuatitativo Joh L. Heessy y David A. Patterso. Mc Graw Hill, 3ª ed, 22 Apédices A: aritmética de computadores Orgaizació y arquitectura de computadores William Stalligs. Pretice Hall. 996 Capítulo 8 Automatic Departmet Computers Structure ad Orgaizatio. Graduate i Computer Scieces / Graduate i Computer Egieerig