CMSC Computer Architecture Lecture 3: ISA and Introduction to Microarchitecture. Prof. Yanjing Li University of Chicago

Transcription

1 CMSC Computer Architecture Lecture 3: ISA ad Itroductio to Microarchitecture Prof. Yajig Li Uiversity of Chicago

2 Lecture Outlie ISA uarch (hardware implemetatio of a ISA) Logic desig basics Sigle-cycle uarch Evaluatio of the sigle-cycle uarch 2

3 Recap: Lecture 2 ISA basics Istructios Opcodes, operads, data types, processig styles, classes, formats, istructio legth, uiform vs. o-uiform decode, addressig modes Memory ad registers Address space, addressability, aliged vs. ualiged access Others I/O, privilege modes, exceptio hadlig, etc. ISA tradeoffs RISC vs. CISC, load/store vs. mem/mem, etc. Case study: ARMv8/LEGv8 ISA Mappig C code all the way to machie code Ecode/Decode machie code 3

4 B Format Istructios opcode BR_address 6 bits 26 bits Example: B L1 brach ucoditioally to istructio labeled L1; B opcode: 0A0 16-0BF 16 I ARMv8, it is Effect: PC = PC + BrachAddr **Based o origial figure from [P&H CO&D, COPYRIGHT 2016 Elsevier. ALL RIGHTS RESERVED.]

5 Do You Always Brach? C code: if (i==j) f = g+h; else f = g-h; **Based o origial figure from [P&H CO&D, COPYRIGHT 2016 Elsevier. ALL RIGHTS RESERVED.]

6 CB Format Istructios Brach to a labeled istructio if a coditio is true Otherwise, cotiue seuetially Examples opcode CBZ register, L1 COND_BR_address 8 bits 19 bits 5 bits if (register == 0) brach to istructio labeled L1; CBNZ register, L1 if (register!= 0) brach to istructio labeled L1; Effect: if take, PC = PC + CodBrachAddr; else PC=PC+4 Rt 18 **Based o origial figure from [P&H CO&D, COPYRIGHT 2016 Elsevier. ALL RIGHTS RESERVED.]

7 C to Assembly 301 C code: if (i==j) f = g+h; else f = g-h; f, g,h,i,j i X19, X20, X21, X22, X23, Compiled code: SUB X9,X22,X23 CBNZ X9,Else ADD X19,X20,X21 B Exit Else: SUB X19,X20,x21 Exit: Assembler calculates addresses **Based o origial figure from [P&H CO&D, COPYRIGHT 2016 Elsevier. ALL RIGHTS RESERVED.]

8 More Coditios? Coditioal Codes (CC) CC: set by a set of arithmetic istructios with the S-suffix (ADDS, ADDIS, ANDS, ANDIS, SUBS, SUBIS) egative (N): result had 1 i MSB zero (Z): result was 0 overflow (V): result overflowed carry (C): result had carryout from MSB Coditioally brach based o CC: B.cod (B format) How to evaluate cod **Based o origial figure from [P&H CO&D, COPYRIGHT 2016 Elsevier. ALL RIGHTS RESERVED.]

9 B.cod Example if (a > b) a += 1; a i X22, b i X23 SUBS X9,X22,X23 // use subtract to make compariso B.LE Exit // coditioal brach ADDI X22,X22,#1 Exit: **Based o origial figure from [P&H CO&D, COPYRIGHT 2016 Elsevier. ALL RIGHTS RESERVED.]

10 WI Format Istructios Most costats are small opcode op2 immediate 12-bit immediate is sufficiet For the occasioal large costats MOVZ: move wide with zeros MOVK: move wide with keep Set ay of the 4 16-bit portios i register Rd with the immediate field Rd 9 bits 2 bits 16 bits 5 bits **Based o origial figure from [P&H CO&D, COPYRIGHT 2016 Elsevier. ALL RIGHTS RESERVED.]

11 WI Format Istructios: Example Opcode: MOVZ two ; MOVK two Op2: 0àbit 0-15 of Rd gets the immediate value 1àbit of Rd gets the immediate 2àbit of Rd gets the immediate 3àbit of Rd gets the immediate (All other bits of Rd set to 0 for MOVZ, or preserve their values for MOVK ) Iitially, X9 == FFFFFFFFFFFFFFFF MOVZ X9,255, op2= MOVK X9,255,op2= **Based o origial figure from [P&H CO&D, COPYRIGHT 2016 Elsevier. ALL RIGHTS RESERVED.]

12 LEGv8 Ecodig Summary

13 ISA Support for Fuctios Brach ad Lik (call): BL ProcedureAddress (B format) PC PC + BrachAddr retur address = PC + 4 GPR[X30] retur address O a fuctio call, the callee eeds to kow where to go back to afterwards X30 is also called LR or lik register Brach to Register (ret): BR R (R format) target = GPR [R] PC target Allows the same istructio to jump to ay locatio specified by Rd (X30 for retur)

14 Dealig with a Chai of Fuctios Caller... code A... BL _myfx... code C... BL _myfx... code D... Callee _myfx:... code B... BR X30... A call B retur C call B retur D... How do you pass argumet betwee caller ad callee? If A sets X16 to 1, what is the value of X16 whe B returs to C? What registers ca B use? What happes to X30(LR) if B calls aother fuctio

15 Review Callee-saved vs. caller saved Register usage covetio E.g., special geeral-purpose registers (eax, ebp, esp i x86) Callig covetios Fuctio prologue/epilogue

16 Caller ad Callee Saved Registers Callee-Saved Registers Caller says to callee, The values of these registers should ot chage whe you retur to me. Callee says, If I eed to use these registers, I promise to save the old values to memory first ad restore them before I retur to you. Caller-Saved Registers Caller says to callee, If there is aythig I care about i these registers, I already saved it myself. Callee says to caller, Do t cout o them stayig the same values after I am doe.

17 Register Usage Covetio **Based o origial figure from [P&H CO&D, COPYRIGHT 2016 Elsevier. ALL RIGHTS RESERVED.]

18 Callig Covetio caller saves caller-saved registers 2. caller loads argumets ito X0-X7 3. caller jumps to callee usig BL 4. callee allocates space o the stack (dec. stack poiter) 5. callee saves callee-saved registers to stack (X19-X27, also old X28 or old X29, X30)... body of callee (ca est additioal calls) callee loads results to X0-X7 7. callee restores saved register values 8. BR X30 9. caller cotiues with retur values i X0-X7... prologue epilogue

19 Review: Memory Usage Covetio Text: program code Static data: global variables e.g., static variables i C, costat arrays ad strigs Dyamic data: heap e.g., malloc i C, ew i Java Stack automatic storage stack space free space dyamic data static data text grow dow grow up high address stack poiter GPR[X28] biary executable reserved low address

20 C to Assembly 401 C code: it fact (it ) { if ( < 1) retur 1; else retur * fact( - 1); } Argumet i X0 Result i X1

21 C to Assembly 401 Compiled code: fact: SUBIS XZR,X0,#1 //test for <1 B.GE L1 //if >=1, go to L1 ADDI X1,XZR,#1 //put 1 i result register X1 BR LR //retur L1: SUBI SP,SP,#16 //adjust stack for 2 items STUR LR,[SP,#8]//save retur address STUR X0,[SP,#0] //save argumet (X0: caller saved) SUBI X0,X0,#1 // Argumet X0 gets -1 BL fact //call fact LDUR X0,[SP,#0] //fact returs, restore value to X0 LDUR LR,[SP,#8] //restore retur address to LR(X30) ADDI SP,SP,#16 //pop stack MUL X1,X0,X1 //put *fact(-1) ito result register X1 BR LR //retur C code: it fact (it ) { if ( < 1) retur 1; else retur * fact( - 1); } Argumet i X0 Result i X1

22 Now That We Have a ISA How do we implemet it? i.e., how do we desig a hardware system that obeys the hardware/software iterface? 22

23 Logic Desig Basics 23

24 Termiologies Digital systems, iformatio ecoded i biary Oe wire per bit: Low voltage = 0, High voltage = 1 Combiatioal logic (CL) Calculate the output of a logic fuctio based o iputs State (seuetial) elemets Store iformatio, tightly coupled with CL Memory elemets Less expesive tha seuetial elemets Stores a large amout of iformatio that may ot eed to be accessed as ofte as the iformatio i seuetial elemets

25 Combiatioal Logic Examples AND-gate Y = A & B Adder Y = A + B A B + Y A B I0 I1 M u x S Y Multiplexer Y = S? I1 : I0 Y Arithmetic/Logic Uit Y = F(A, B) A ALU Y B F **Based o origial figure from [P&H CO&D, COPYRIGHT 2016 Elsevier. ALL RIGHTS RESERVED.]

26 Seuetial Elemets Register: stores data i a circuit Uses a clock sigal to determie whe to update the stored value Edge-triggered: update whe Clk chages from 0 to 1 Called a flip-flop D Clk Q Clk D Q **Based o origial figure from [P&H CO&D, COPYRIGHT 2016 Elsevier. ALL RIGHTS RESERVED.]

27 Critical Path ad Clock Cycle Time Combiatioal logic (CL) computes ad trasforms data Betwee clock edges Iput from state elemets, output to state elemet Logest delay determies clock cycle time Logest CL is also referred to as the critical path What if CL is loger tha clock cycle time? Add seuetial elemets! **Based o origial figure from [P&H CO&D, COPYRIGHT 2016 Elsevier. ALL RIGHTS RESERVED.]

28 Memory Elemets Iputs: address, read eable (re), write eable (we), write data (ofte comig from seuetial elemets) Output: read data (ofte will be stored i seuetial elemets) Ca have multiple read/write ports Sychroous with clock E.g., issue read/write i cycle i, data is outputted/writte i cycle i+1 address Data i re we Data out Clk

29 Implemetig the ISA: Microarchitecture Basics 29

30 How Does a Machie Process Istructios? What does processig a istructio mea? AS = Architectural (programmer visible) state before a istructio is processed Process istructio AS = Architectural (programmer visible) state after a istructio is processed Processig a istructio: Trasformig AS to AS accordig to the ISA specificatio of the istructio 30

31 Remember: Programmer Visible (Architectural) State M[0] M[1] M[2] M[3] M[4] Registers - give special ames i the ISA (as opposed to addresses) - geeral vs. special purpose M[N-1] Memory array of storage locatios idexed by a address Program Couter memory address of the curret istructio Istructios (ad programs) specify how to trasform the values of programmer visible state 31

32 Istructio Processig ISA specifies abstractly what AS should be, give a istructio ad AS It defies a abstract fiite state machie where Curret State: programmer-visible state Next State: istructio executio specificatio From ISA poit of view, there are o itermediate states betwee AS ad AS durig istructio executio Oe state trasitio per istructio Microarchitecture implemets how AS is trasformed to AS There are may choices i implemetatio We ca have programmer-ivisible state to optimize the speed of istructio executio: multiple state trasitios per istructio Choice 1: AS à AS (trasform AS to AS i a sigle clock cycle) Choice 2: AS à AS+MS1 à AS+MS2 à AS+MS3 à AS (take multiple clock cycles to trasform AS to AS ) 32

33 A Very Basic Istructio Processig Egie Each istructio takes a sigle clock cycle to execute Oly combiatioal logic is used to implemet istructio executio No itermediate, programmer-ivisible state updates AS = Architectural (programmer visible) state at the begiig of a clock cycle Process istructio i oe clock cycle AS = Architectural (programmer visible) state at the ed of a clock cycle 33

34 A Very Basic Istructio Processig Egie Sigle-cycle machie Combiatioal Logic AS Seuetial Logic / memory (State) AS What is the clock cycle time determied by? The slowest istructio determies cycle time à log clock cycle time 34

35 What Is To Come **Based o origial figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.] 35

36 Datapath vs. Cotrol Logic A istructio processig egie cosists of two compoets Datapath: Cosists of hardware elemets that deal with ad trasform data sigals fuctioal uits that operate o data hardware structures (e.g. wires ad muxes) that eable the flow of data ito the fuctioal uits ad registers storage uits that store data (e.g., registers) Cotrol logic: Cosists of hardware elemets that determie cotrol sigals, i.e., sigals that specify what the datapath elemets should do to the data 36

37 A Sigle-Cycle Microarchitecture A Closer Look 37

38 Remember Sigle-cycle machie Combiatioal Logic AS Seuetial Logic (State) AS 38

39 Let s Start with the State Elemets What are the architecture (programmer visible) states for LEGv8? **Based o origial figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.] 39

40 State Elemets Data ad cotrol iputs PC Read register 1 Read register 2 Registers Write register Write data Read data 1 Read data 2 RegWrite MemWrite Istructio address Istructio Address Read data Istructio memory Write data Data memory MemRead **Based o origial figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.] 40