Fully Parallel Window Decoder Architecture for Spatially-Coupled LDPC Codes

Transcription

1 Fully Parallel Widow Decoder Architecture for Spatially-Coupled LDPC Codes Najeeb Ul Hassa, Marti Schlüter, ad Gerhard P. Fettweis Vodafoe Chair Mobile Commuicatios Systems, Dresde Uiversity of Techology (TU Dresde), Dresde, Germay, ajeeb Abstract Spatially-coupled low-desity parity-check (SC- LDPC) codes have bee show to be superior i performace tha LDPC block codes. I order to comply with the practical costraits o latecy, SC-LDPC codes are decoded usig a slidig widow decoder that reduces the latecy ad complexity of decodig compared to traditioal block-wise decodig. However, so far the literature oly cosiders the structural decodig latecy of widow decoder, igorig the processig latecy. Note that the processig latecy directly impacts the decoder s throughput ad is a importat parameter i ay moder commuicatio system. The throughput of a iterative decoder is directly iflueced by the umber of iteratios ad hece i this paper we propose a fully parallel widow decoder architecture for SC-LDPC codes where the decodig iteratios are performed i parallel. This guaratees a high throughout while fulfillig the low latecy requiremets. The overall decodig latecy (structural ad processig latecy) of widow decoder architectures is also compared. I. INTRODUCTION Gallager itroduced a class of liear codes which are described by a sparse parity-check matrix [1] referred as low-desity parity-check (LDPC) codes. Sice these codes are costructed from sparse matrices, these ca be decoded usig a simple ad practical iterative decoder. Hece as a result, i geeral, the decodig complexity per decoded bit is idepedet of the legth of the code whe the umber of decodig iteratios is fixed. Thaks to this property of LDPC codes, various stadards that deals with high data rate, e.g., DVB, WiMAX, WiGig, propose LDPC codes which allow them to operate close to the Shao limit usig log block legths. Spatially-coupled LDPC (SC-LDPC) codes were first iveted by Jimeez Felström ad Zigagirov i [2]. Sice these are characterized by a semi-ifiite diagoal type paritycheck matrix, these were referred to as LDPC covolutioal codes. Like LDPC block codes they are defied by a sparse parity-check matrix, which allows to decode them with belief propagatio algorithms. The differece betwee SC-LDPC ad LDPC block codes is the memory. For LDPC block codes, codewords of differet time istats are ecoded ad decoded idepedetly of each other. A codeword (v [1,L] ) of a termiated SC-LDPC code cosists of L coupled code blocks v t, t = 1,..., L. The origial block-wise decodig approach waits util all L blocks are received ad the performs belief This work was i part supported by the DFG i the CRC 912 HAEC. The authors are grateful for the use of the high performace computig facilities of the ZIH at TU Dresde. propagatio. I [2] ad [3] a pipelied block-wise decoder is cosidered. For a large L, SC-LDPC codes are kow to achieve superior bit error rate (BER) performace compared to LDPC block codes. However, the drawback of havig a large L is the icrease i latecy ad decodig complexity [4] [5]. Hece, the pipelie decoders preseted i [2] [3] have large iitial delay, e.g., equal to the legth of the coupled code L. Aother approach is a slidig widow decoder of size W. The widow decoder operates o W L code blocks, ad the resultig decodig latecy ad decodig complexity becomes idepedet of L. The slidig widow decoder is detailed i Sectio III. It has bee show i [4] ad [6] that biary ad o-biary SC-LDPC codes decoded with the widow decoder outperform their couterpart LDPC block codes uder same latecy, respectively. However, the compariso was solely based o the structural latecy of the codes. The structural latecy of the code depeds o the structure of code ad reflects the fact that the mappig operatio at decoder ca be doe oce a certai umber of symbols (or bits) are available at the iput [7]. Hece decoder processig latecy for LDPC block codes ad SC-LDPC codes decoded usig widow decoder was assumed to be equal. This assumptio was based o the followig argumet; sice the umber of symbols ad the iterative message passig algorithm i two decoders is same, the processig latecy of the LDPC block decoder ad widow decoder is equal. Note that this argumet iheretly assume that the implemetatio of LDPC block decoder ad widow decoder ca be doe i same way. I a iterative decoder, processig latecy depeds o the umber of iteratios. I case of block codes, i.e, whe blocks are ecoded ad decoded idepedetly, the processig latecy ca be reduced by parallelizig the iteratios or also kow as iteratio urollig. I [8], a ultra high speed LDPC decoder architecture has bee preseted achievig a throughput up to 160 Gbit/s based o this priciple. Note that the pipelie decoder for SC-LDPC decoder proposed i [3], reduces to the oe proposed i [8] whe applied to block codes. However, due to the memory read access required i the widow decoder, these architectures are ot suitable ad up to ow, o such architecture has bee proposed for the slidig widow decoder. We propose a way to adapt the high throughput architecture from [8] ad desig a slidig widow decoder i Sectio IV that performs all iteratios i parallel ad approaches the performace of the classical widow decoder. We show the challeges i urollig the

2 iteratios of the widow decoder. The BER results are show i Sectio V. II. SPATIALLY-COUPLED LDPC CODES I order to describe spatial couplig, let us cosider a trasmissio of a sequece of LDPC code blocks v t, t = 1,..., L of legth c bits, i.e., code block v t = [v t (1),..., v t (c)] geerated from a ucoded iformatio block u t = [u t (1),..., u t (b)]. A essetial feature of SC- LDPC code is that the blocks at differet time istats are itercoected. Istead of ecodig all codewords idepedetly, the blocks v t are coupled by the ecoder to other time istats. The largest distace betwee a pair of coupled blocks defies the memory m cc of the coupled code. Cosiderig a SC-LDPC code C, the parity-check matrix of a termiated code is give as H [1,L] = H 0 (1).. H mcc (1)... H 0 (L).... H mcc (L) where the elemets of matrix H [1,L] are the sub-matrices of dimesio (c b) c defied as h (1,1) i (t) h (1,c) i (t) H i (t) =... (2) h (c b,1) i (t) h (c b,c) i (t) The correspodig sequece of coupled code blocks forms a codeword v [1,L] = [v 1,..., v t,..., v L ] of a termiated spatially-coupled code. We assume H i (t) = H i (t ) i = 0,..., m cc, t = t = 1,..., L, i.e., a time-ivariat code. I [9] ad [10], authors provide a way to geerate codes that provide a easy/fast ecodig. A alterate represetatio of a SC-LDPC code is by usig a bipartite graph or Taer graph. A Taer graph for a SC- LDPC code cosists of M = (L+m cc )(c b) check odes ad N = Lc variable odes. The check odes correspod to the set of parity-check costraits ad the variable odes correspod to the code bits. Referrig to the parity-check matrix i (1), check odes ad variable odes represet the rows ad colums of (1), respectively. Each 1 i H [1,L] represets a edge coectig the correspodig variable ad check ode i the Taer graph. III. DECODING OF SC-LDPC CODES We cosider a additive white Gaussia oise (AWGN) chael with received symbols havig the followig form, (1) y(i) = x(i) + (i), i = 1,..., N (3) where x(i) are BPSK symbols, obtaied from iput symbols v(i) as x(i) = 2v(i) 1 {+1, 1} ad (i) are idepedet ad idetically distributed Gaussia radom variables with zero mea ad variace σ 2 = N 0 /2, ad N 0 is the sigle sided power spectral desity of the oise. yt mcc m cc yt 1 yt W yt+w 1 y t+w L out(y [t mcc,t 1]) L out(y t) L ch (y [t,t+w 1] ) û t BP Decoder Variable Nodes VN2CN CN2VN Check Nodes Fig. 1. Widow Decoder of size W decodig the symbols i y t. A. Block-wise Decodig Oe of the beefits of havig low desity of oes i the parity-check matrix is that LDPC codes ca be decoded usig a iterative message passig decoder. The decodig complexity icreases with the desity of oes i H, hece a low desity is desirable. I case of AWGN chael, messages i the form of log-likelihood ratios (LLR) are exchaged betwee the coected check ad variable odes i every iteratio. Sice the absolute value of a LLR represets the stregth (belief) of the message, this message passig algorithm is kow as belief propagatio (BP). The decodig for a SC-LDPC code ca be performed by ruig BP algorithm over the complete chai of L coupled blocks v [1,L]. Sice the coupled code is treated i this case as a block code, we refer to such a decoder as a block-wise decoder. However, ruig BP algorithm over the complete chai of L coupled blocks v [1,L] is ot optimum i terms of decodig latecy ad complexity. Aother way of decodig the coupled code is by usig a slidig widow decoder [11]. It has bee show i [4] that SC-LDPC codes decoded usig a widow decoder outperforms LDPC block codes uder equal latecy. B. Widowed Decodig The covolutioal structure of coupled codes allows to defie a latecy costraied widow decoder of size W. Cosider the blocks v t ad v t i the chai of coupled code, where t t + m cc + 1 ad t, t [1 L]. Sice t t + m cc + 1, v t ad v t do ot share ay parity-check equatio (check ode). Widow decoder exploits this property of the covolutioal parity-check matrix of SC-LDPC code to defie a decoder cosistig of W received blocks such that W m cc + 1. I order to decode symbols i y t, the widow cosists of W received blocks, y [t,t+w 1] ad m cc previously decoded blocks i memory of decoder. This is show i Fig. 1 as a shift register of size W code blocks for widow that holds the chael values of y [t,t+w 1]. Similarly a shift register of size m cc code blocks holds the output LLRs correspodig to the decoded code blocks y [t mcc,t 1] i the memory.

3 I terms of parity-check matrix, the slidig widow decoder of size W operates o a sectio of W (c b) rows ad W c colums of the matrix H [1,L], correspodig to W coupled blocks. Hece, widow decoder cosists M W = W (c b) check ad N W = W c variable odes. The BP decoder cosists of M W check ad N W variable odes. The VN2CN ad CN2VN modules defie the coectios from N W variable to M W check odes ad vice versa, respectively. Remark 1: Note that it is because of the time-ivariace of the SC-LDPC code that the VN2CN ad CN2VN stays fixed for the decodig of complete coupled codeword v [1,L]. Hece for implemetatio cosideratios of the widow decoder, a time-ivariat code is suitable. The calculatio of LLR values i variable ad check odes ad the decodig algorithm is detailed below. C. Decodig Algorithm Let v k, k = 1,..., N W ad c j, j = 1,..., M W deote the N W variable ad M W check odes withi a widow. The L ch (v k ) deote the iput chael LLR for variable ode v k ad N (v k ) deotes the set of check odes coected to the variable ode v k. Similarly N (c j ) represets the set of variable odes coected to the check ode c j. The message from the variable ode v k to the check ode c j i th iteratio is deoted as L () v k,c j. 1) Iitializatio: I the iitializatio phase, all variable odes v k seds L ch (v k ) to all its coected check odes, L (0) v k,c j = L ch (v k ). (4) 2) Iterative Process: I the succeedig iteratios, the extrisic LLRs from the variable ode v k to the check ode c j are calculated as follows, L () v k,c j = L ch (v k ) + l N (v k )\c j L ( 1) c l,v k. (5) Here L () c l,v k deotes the message from the check ode c l to the variable ode v k. Ad N (v k )\c j represets the set of check odes coectig to v k excludig c j. The exclusio of c j here precludes the iformatio received by v k from c j to be reused to calculate the message L vk,c j. Similarly the extrisic LLRs from the check ode c j to the variable ode v k are calculated as follows, L () c j,v k = 2 tah 1 l N (c j)\v k tah ( ) L ( 1) v l,c j. (6) 2 Similar to (5), the calculatio of L () c j,v k excludes the variable ode v k. The widow at time t, as show i Fig. 1, decodes the symbols i the received block y t oly, ad hece they are termed target symbols. The miimum size of the widow decoder must be at least m cc + 1 code blocks, such that the parity check equatios icludig the target symbols are i the widow. The BP algorithm is applied to the odes withi the widow oly, however, due to the memory of the coupled code, a read access to the m cc previously decoded blocks is also required. 3) After I max Iteratios: The iterative process cotiues util the maximum umber of iteratios I max is reached. The output LLR L out (v k ) for variable ode v k is the computed as L out (v k ) = L ch (v k ) + l N (v k ) L (Imax) c l,v k. (7) The output LLRs correspodig to the target symbols (L out (y t )) are the fed back to the memory shift register, as show i the Fig. 1. Oce the target symbols are decoded, c ew chael values correspodig to y t+w, eter the widow decoder from right ad the estimates of the iformatio bits û t leaves the decoder from left. The decodig process cotiues util all the code blocks are decoded. Remark 2: It is importat to ote here that the architecture i Fig. 1 allows to keep the output messages of all the variable odes i y [t+1,t+w 1] i the registers to be used for the decodig of succeedig code blocks. This implies that the messages alog the edges calculated for decodig the symbols i y t are kept for the decodig of succeedig code blocks. The widow decoder provides a way to icrease the termiatio legth L arbitrarily large ad is suitable for cotiuous decodig of iput blocks. Furthermore, sice message passig algorithm is applied oly to W received blocks, the memory ad hardware requiremets for such a decoder are far less compared to block-wise decodig of SC-LDPC codes. I geeral, the storage requiremets for the decoder reduces by a factor of L/W compared to the block-wise decoder. IV. FULLY PARALLEL WINDOW DECODER I the decoder architecture preseted i Fig. 1, a ew code block eters from right oly after I max iteratios are performed. Assumig that T p secods are required to perform a sigle decodig iteratio (updatig all N W variable ad M W check odes i a widow). The the decoder geerates a output every T p I max secods. Note that the update of all N W variable ad M W check odes are doe i parallel. I terms of processig latecy, the critical path 1 of the decoder depeds o the umber of iteratios I max. Oe way to reduce the decodig processig latecy or cosequetly icreasig the decodig throughput is to parallelize these I max iteratios. This will reduce the critical path to 1 iteratio. Cosiderig block codes, i.e., each code block is ecoded ad decoded idepedetly, these I max iteratios ca be urolled (pipelied) to obtai a fully parallel decoder. Hece a code block eters ad leaves the BP decoder every T p secods 2. This icreases the decoder throughput by a factor of I max. Such a decoder architecture to decode LDPC block codes was proposed i [8]. The architecture, however, requires that all the code blocks are ecoded ad decoded idepedetly ad does ot require a read access to the memory. I the followig we propose a urolled fully parallel widow decoder architecture. 1 Critical path is the path i the etire desig with the maximum delay. 2 Note that, the iitial processig latecy to decode the first block is still T pi max secods. However, after this iitial latecy, decoded blocks leaves the decoder every T p secods.

4 Shift Reg. SI/PO I 1 Chael value,[1,...,m cc] I i VN2CN = I out 1 Memory I 2 Check Nodes CN2VN Stage I I max Variable Nodes chael values Decoded bits I out = I i +1 Fig. 2. Urolled architecture for widow decoder. Fig. 3. Detail descriptio of a pipelie stage. A. Urollig the Iteratios of Widow Decoder Now cosiderig the widow decoder preseted i Sectio III, we aim at proposig a urolled architecture for the widow decoder i order to parallelize the decodig iteratios. As a result, the decoder geerates a output every T p secods. A obvious hurdle i directly applyig the architecture from [8] is the memory of the SC-LDPC code. As described i Sectio III, widow decoder eeds the read access to the m cc already decoded code blocks ad decodig of symbols i y t+1 starts oly after fiishig I max iteratios for the decodig of symbols i y t. This meas that the urolled widow decoder ca oly utilize the ufiished (itermediate) output LLRs of the target symbols from the previous widows. Figure 2 shows a top level view of the urolled widow decoder architecture with I max pipelie stages. A detailed view of each stage is show i Fig. 3. We ote the similarities with the pipelie SC-LDPC decoder i [3], however, the major differece lies i the fact that we start with a widow decodig schedule. Whereas, the architecture i [3] rus the BP algorithm over the etire coupled codeword, resultig i a very large iitial latecy. 3 The chael values i Fig. 2 are stored i a serial-iput/parallel-output shift register. O receivig a ew code block, the iput register shifts oe to left, takes i c ew values correspodig to oe code block. Similar to Fig. 1, each stage cosists of N W variable odes, M W check odes, VN2CN ad CN2VN etworks. The iputs to each stage are the results from the previous stage I i = I 1, out ad the chael values of W received code blocks. The chael values has to be available for all iteratios ad thus are stored i the pipelie registers (). The output I out cotai the results of th iteratio for all the W code blocks i the widow. Memory Maagemet: I additio to this, the followig iput ad output operatios to the memory are also required at each stage; memory,,[1,...,m cc] : read LLRs of m cc code blocks from the 3 Here iitial latecy meas the latecy to decode symbols i y 1. I target : write the values of target symbols i the memory. Let us explai the memory read ad write operatio by usig a example. Cosider a SC-LDPC code with m cc = 2 decoded usig I max = 5 iteratios. The horizotal wires at the bottom ad upper part of Fig. 4 show the memory write ad read operatio for every pipelie stage, respectively. At time t, a th pipelie stage reads two memory iputs (m cc = 2), oe from itself but writte at time t T p ad oe from the (+1) th pipelie stage also writte at time t T p. This is because, the two precedig code blocks have bee target blocks T p secods before i th pipelie stage ad i ( + 1) th pipelie stage. As a example, for the first pipelie stage the two reads are, 1,[1] = 1 delay = T p 1,[2] = 2 delay = T p The memory read ad write operatio here for the last pipelie stage is differet. Sice, the last iteratio has o ext pipelie stage, which meas all m cc = 2 precedig code blocks are decoded. Hece, m cc memory reads, 5,[1] = 5 delay = T p 5,[2] = 5 delay = 2T p I geeral, whe m cc > 2, earlier pipelie stages also require the target values of already decoded code blocks. The memory read ad write operatio is accomplished by storig the target values from each pipelie stage ito its pipelie registers. I geeral for ay m cc ad I max, each stage requires to read m cc memories. At time t, the k th iput from memory for stage, I,[k] mem, is give as, { I target I,[k] mem = +k 1 (t T p), + k 1 < I max I max (t ( + k I max )T p ), + k 1 I max (8) where k = 1,..., m cc ad = 1,..., I max. Remark 3: It is importat to ote here that for the urolled widow decoder, every T p secods the N W variable odes i the first pipelie stage sed the chael values (see (4)) to all coected check odes. This is differet to the architecture

5 I 1 (t) : I 2 (t) : I 3 (t) : I 1 (t + T p ) : I 2 (t + T p ) : I 3 (t + T p ) : Fig. 5. Sapshot of the code blocks beig processed i I max = 3 pipelie stages at clock cycle t ad t + 1. The code blocks i gree ad red represet the memory ad target blocks at each stage, respectively. Memory for stage I I 5 I 4 I 3 I 2 I 1 delay=2t p 1,[1,2] 2,[1,2] 3,[1,2] 4,[1,2] 5,[1,2] Fig. 4. Memory read ad write operatio for the urolled widow decoder, m cc = 2 ad I max = 5. from Fig. 1, where the messages are kept alog the edges emaatig from variable odes i registers ad the iitializatio step is ot doe for all N W variable odes rather oly for the ew c variable odes eterig i the shift register. Remark 4: Also ote that i the urolled widow decoder, time-ivariace ature of code is a ecessity. Sice a pipelie stage performs the th iteratio o a widow, CN2VN ad VN2CN etworks must be same i all I max pipelie stages. Hece for a high throughout, low latecy widow decoder implemetatio, a time-ivariat SC-LDPC code must be desiged. B. Circular Pipelie Widow Decoder As explaied i Remark 3, the ewly computed results are ot cosumed i the followig widows whe the iteratios are urolled. To explai this further, let us take a example of a widow decoder of size W = 6 performig I max = 3 iteratios o a SC-LDPC code with m cc = 2. The Fig. 5 shows a sapshot of the code blocks beig processed withi all pipelie stages at time t ad t+t p. I the first pipelie stage I 1, symbols i y t ad y t+1 are the target symbols at time t ad t + T p, respectively. The symbols i y t are also the target symbols i the secod pipelie stage at time t + T p, which takes all the computed messages for the odes withi the widow at the begiig of time t+t p from the first stage, i.e., I2 i = I1 out. Now at time t, I max iteratios are processed o the code blocks y [t 2,t+3]. The output LLRs correspodig to y t 2 are stored i the memory ad the results computed for code blocks y [t 1,t+3] are discarded. However, i this example the results for code blocks y [t+1,t+3] ca be fed back to the first pipelie stage, makig it a circular pipelie widow decoder. As a result, the variable odes i code blocks y [t+1,t+3] i the first pipelie stage at time t + T p are ot iitialized with the chael values. Ad oly the variable odes i code blocks y [t+4,t+6] are iitialized with the chael values. C. Overall Latecy Compariso Fially, let us compare the overall latecy of the widow decoder architectures preseted i this paper. Let us deote T r as the time to receive oe code block y t of c bits ad T p deotes the time to perform oe decodig iteratio. i.e., updatig N W variable ad M W check odes. Assumig the trasmissio starts at t = 0, the first code block is received at the iput of the decoder at time t = T r. Now for the classical widow decoder i Fig. 1, the overall decodig latecy for the first code block iitial WD is give as, iitial WD = (W 1)T r + I max T p, (9) where (W 1)T r is the structural latecy ad I max T p is the processig latecy. For a received block y l, l = 2,..., L, the decodig starts after l 1 blocks are processed. Hece the overall decodig latecy is a fuctio of block umber l ad

6 is give as, WD (l) = (W l)t r + (l + 1) (I max T p ). (10) Now cosiderig the widow decoder architecture i Fig. 2, the iitial latecy is the same as i (9), iitial Pipe. WD = (W 1)T r + I max T p. (11) Cosiderig T p T r, the overall latecy for a received block y l, l = 2,..., L, is fixed ad is give as, Pipe. WD (l) = T p, (12) which is cosiderably less as compared to (10) ad also, importatly, idepedet of W. I the ext sectio, we demostrate usig simulatio the beefit i terms of BER whe feedig these computed results from the last stage to the first stage. V. SIMULATION RESULTS I this sectio, we compare the BER curves for the widow decoder from Sectio III ad the two pipelie widow decoder architectures preseted i Sectio IV. The time-ivariat SC- LDPC code has bee geerated followig the method from [10]. Note that i this work, we focus o the decoder architecture ad do ot aim to optimize the SC-LDPC code. A rate 1/2 SC-LDPC code with memory m cc = 23 is decoded with a widow size of W = 35. The widow decoder has N W = 840 variable ad M W = 420 check odes. The decoder performs I max = 10 iteratios. Figure 6 shows the BER curves for the three widow decoder architectures. It is evidet here that feedig back the calculated results from last pipelie stage to the first pipelie stage helps reduce the gap betwee the pipelie widow decoder ad classical widow decoder. The gap is reduced to 0.1 db at high SNR s but for low SNR values, there is o sigificat improvemet i performace for circular pipelie widow decoder compared to the pipelie widow decoder. This is because at low SNR, the code blocks further away from the target block show very little improvemet i terms of LLR values with iteratios. This has bee previously observed i [5]. Hece the last stage is ot able to provide much ew iformatio to the first stage at low SNR. VI. CONCLUSION We propose a fully parallel widow decoder architecture for widow decoder by pipeliig (urollig) the iteratios. Due to the memory read access required i the widow decoder, the already proposed fully parallel architectures are ot applicable. Compared to the classical widow decoder, egligible loss i performace was observed which is due to utilizig the ufiished (itermediate) values i the memory. The coectios betwee the pipelie stages (iput-output ad memory maagemet) are also detailed. To the best of authors kowledge, o such architecture for widow decoder has bee proposed i the literature. We further compare the overall decodig latecy of the widow decoder. With this architecture ow the assumptio regardig the decodig processig latecy, Bit Error Rate WD Pipe.-WD Circ-Pipe.-WD E b /N 0 [db] Fig. 6. BER compariso betwee the classical widow decoder (WD), pipelie widow decoder (Pipe.-WD) ad the circular pipelie widow decoder (Circ-Pipe.-WD). For all three decoders, I max = 10 iteratios are performed. detailed i Sectio I, is valid. Sice, for both block decoder ad widow decoder, iteratios ca be urolled to icrease the decodig throughput by a factor of I max. The results are also verified usig Verilog simulatio, with FPGA implemetatio left as a future work. REFERENCES [1] R. G. Gallager, Low desity parity check codes, Ph.D. dissertatio, Massachussetts Istitute of Techology (MIT), [2] A. Jimeez Felstrom ad K. Zigagirov, Time-varyig periodic covolutioal codes with low-desity parity-check matrix, IEEE Tras. If. Theory, vol. 45, o. 6, pp , Sep [3] A. Pusae, A. Feltstrom, A. Sridhara, M. Letmaier, K. Zigagirov, ad D. Costello, Implemetatio aspects of LDPC covolutioal codes, IEEE Tras. Commu., vol. 56, o. 7, pp , Jul [4] N. Ul Hassa, M. Letmaier, ad G. Fettweis, Compariso of LDPC block ad LDPC covolutioal codes based o their decodig latecy, i Proc. It. Symp. o Turbo Codes & Iterative If. Proc., Aug. 2012, pp [5] M. Letmaier, M. Preda, ad G. Fettweis, Efficiet message passig schedulig for termiated LDPC covolutioal codes, i Proc. IEEE It. Symp. Iform. Theory (ISIT), Aug. 2011, pp [6] K. Huag, D. G. M. Mitchell, L. Wei, M. Xiao, ad D. J. Costello Jr, Performace compariso of o-biary LDPC block ad spatially coupled codes, i Proc. IEEE It. Symp. Iform. Theory (ISIT), Ju. 2014, pp [7] T. Heh ad J. Huber, LDPC codes ad covolutioal codes with equal structural delay: A compariso, IEEE Tras. Commu., vol. 57, o. 6, pp , Ju [8] P. Schlafer, N. Weh, M. Alles, ad T. Lehigk-Emde, A ew dimesio of parallelism i ultra high throughput LDPC decodig, i IEEE Workshop o Sigal Processig Systems (SiPS), Oct 2013, pp [9] A. Pusae, K. Zigagirov, ad J. Costello, D.J., Costructio of irregular LDPC covolutioal codes with fast ecodig, i Proc. IEEE It. Cof. Commu. (ICC), vol. 3, Jue 2006, pp [10] I. Bocharova, B. Kudryashov, ad R. Johaesso, LDPC covolutioal codes versus QC LDPC block codes i commuicatio stadard scearios, i Proc. IEEE It. Symp. Iform. Theory (ISIT), Jue 2014, pp [11] M. Papaleo, A. Iyegar, P. Siegel, J. Wolf, ad G. Corazza, Widowed erasure decodig of LDPC covolutioal codes, i Proc. IEEE Iform. Theory Workshop (ITW), Ja. 2010, pp. 1 5.