Spice Subcircuit Support for Serial Link Channel Design Using IBIS [External Model]
|
|
|
- Frank Craig
- 5 years ago
- Views:
Transcription
![IBIS [External Model] IBIS Summit](/docs-images/89/97817864/images/1-1.jpg "Asian IBIS Summit, November 9,")
1 Spice Subcircuit Support for Serial Link Channel Design Using IBIS [External Model] IBIS Summit Asian IBIS Summit, November 9, 2010 Xiaoqing Dong, Huawei Technologies Shenzhen Zhangmin Zhong, Sigrity Ken Willis, Sigrity Nov 09, 2010 HUAWEI TECHNOLOGIES CO., LTD.
2 Agenda Review existing solutions for serial link IBIS models in channel design The advantages of using Spice-based IO models for serial links Support Spice-based models using IBIS [External Model] keyword HUAWEI TECHNOLOGIES CO., LTD. Page 2
3 IBIS-AMI Model Sub-Components Circuit part IO buffer stage Voltage swing Parasitics Spice or traditional IBIS format Algorithmic part On-chip Equalization functionality DLL + AMI file This presentation focuses on the circuit part HUAWEI TECHNOLOGIES CO., LTD. Page 3
4 Existing Solutions for Serial Link IBIS Circuit Models Most of the models use Spice-based subcircuits No standards for the description of the subcircuits May need much manual work to edit the netlist for specific EDA tools Specified (not standard) keywords in IBIS models Specifications are provided by specified EDA tool Don t need manual work to edit the netlist, but only appropriate for specified EDA tool HUAWEI TECHNOLOGIES CO., LTD. Page 4
5 Spice-Based IO Circuit Model Can easily represent the actual IO structure (ex. pullup resistor with pulldown current source for CML) HUAWEI TECHNOLOGIES CO., LTD. Page 5
6 Spice-Based IO Circuit Model (Cont.) Incorporate hookups for non-ideal power connections External power supply can be linked with the power node of the Spice subcircuit and used for non-ideal power analysis Incorporate on-chip parasitics easily, including PDS, S-params for RDL routing, etc. HUAWEI TECHNOLOGIES CO., LTD. Page 6
7 Spice-Based IO Circuit Model (Cont.) Usage of parameterized subcircuits, where these parameters can be swept in EDA tools HUAWEI TECHNOLOGIES CO., LTD. Page 7
8 Behavioral Spice/AMI vs. Transistor- Level Spice at 10 Gbps, EQ on (from telecomm chip company) Behavioral Spice/AMI Transistor-Level Spice HUAWEI TECHNOLOGIES CO., LTD. Page 8
9 IBIS [External Model] Used to reference an external file written in one of the supported languages containing an arbitrary circuit definition Can be used to support the Spice-based IO models Standard IBIS keyword Don t need manual work to edit the netlist Suitable for all EDA tools if the tool can support standard IBIS [External Model] keyword HUAWEI TECHNOLOGIES CO., LTD. Page 9
10 Ports Under [External Model] Refer to IBIS Specification HUAWEI TECHNOLOGIES CO., LTD. Page 10
11 Example of an [External Model] Output Buffer Using Spice Digital stimulus Defines voltage levels, input ramp rise and fall times Voltage stimulus for Spice subcircuit Spicebased model Output port, pull up and pull down reference ports HUAWEI TECHNOLOGIES CO., LTD. Page 11
12 [External Model] Description for Output [External Model] Language Spice Corner corner_name file_name circuit_name (.subckt name) Corner Typ tx_spice.sp tx_spice Ports List of port names (in same order as in Spice) Ports A_puref A_pdref A_signal my_drive D_to_A d_port port1 port2 vlow vhigh trise tfall corner_name D_to_A D_drive my_drive A_pdref n 0.020n Typ [End External Model] HUAWEI TECHNOLOGIES CO., LTD. Page 12
13 Example of an [External Model] Input Buffer Using Spice Digital state Defines input threshold voltage values Received voltage for Spice subcircuit Spicebased model Input port, power clamp and ground clamp reference ports HUAWEI TECHNOLOGIES CO., LTD. Page 13
14 [External Model] Description for Input [External Model] Language Spice Corner corner_name file_name circuit_name (.subckt name) Corner Typ rx_spice.sp rx_spice Ports List of port names (in same order as in Spice) Ports A_pcref A_gcref A_signal my_receive A_to_D d_port port1 port2 vlow vhigh corner_name A_to_D D_receive my_receive A_gcref -400m 400m Typ [End External Model] HUAWEI TECHNOLOGIES CO., LTD. Page 14
15 System Analysis HUAWEI TECHNOLOGIES CO., LTD. Page 15
16 Summary Spice-based subcircuits are convenient, fast, and accurate for serial link IO circuit modeling IBIS [External Model] keyword can be used to support Spice-based IO models, and don t require the [Pulldown], [Pullup], [POWER Clamp], [GND Clamp] data HUAWEI TECHNOLOGIES CO., LTD. Page 16
17 Thank You! HUAWEI TECHNOLOGIES CO., LTD. Page 17
Multi-lingual Model Support within IBIS
Multi-lingual Model Support within IBIS Bob Ross, Vice Chair. January 28, 2002 IBIS Summit, Santa Clara, CA Benefits of Multi-lingual Support Model advances beyond IBIS True differential buffers, current
Multi-Lingual Modeling Applications and Issues
Multi-Lingual Modeling Applications and Issues Bob Ross June 13, 2002 IBIS Summit Meeting New Orleans, Louisiana Benefits of Multi-Lingual Support Model advances beyond IBIS True differential buffers,
Supporting External circuit as Spice or S- parameters in conjunction with I-V/V-T tables
Supporting External circuit as Spice or S- parameters in conjunction with I-V/V-T tables Kent Dramstad, Adge Hawes IBM Microelectronics Taranjit Kukal, Feras Al-Hawari, Ambrish Varma, Terry Jernberg Cadence
Leveraging IBIS Capabilities for Multi-Gigabit Interfaces. Ken Willis - Cadence Design Systems Asian IBIS Summit, Shanghai, PRC November 13, 2017
Leveraging IBIS Capabilities for Multi-Gigabit Interfaces Ken Willis - Cadence Design Systems Asian IBIS Summit, Shanghai, PRC November 13, 2017 Overview In writing EDI CON paper Signal Integrity Methodology
IBIS Model Process For High-Speed LVDS Interface Products
IBIS Model Process For High-Speed LVDS Interface Products National Semiconductor Corp. Interface Products Group Overview With high-speed system designs becoming faster and more complicated, the need to
Concerns when applying Channel Simulation to DDR4 Interface
Concerns when applying Channel Simulation to DDR4 Interface Masaki Kirinaka mkirinaka@jp.fujitsu.com Akiko Tsukada tsukada.akiko@jp.fujitsu.com FUJITSU INTERCONNECT TECHNOLOGIES LIMITED Asian IBIS Summit
IBISCHK6 IBISCHK6 (IBIS Golden Parser) User Guide Version 6.1.4
IBISCHK6 IBISCHK6 (IBIS Golden Parser) User Guide Version 6.1.4 June 29, 2017 WIP1 Copyright 2017 IBIS Open Forum Contents 1 Introduction... 3 2 IBISCHK6 Usage... 4 2.1 Input File FLAGS... 4 2.2 Output
Inconsistency of EBD (Electrical Board Description) specification in DDR3 DIMM
Inconsistency of EBD (Electrical Board Description) specification in DDR3 DIMM Asian IBIS Summit Yokohama, Japan November 20, 2014 Shogo Fujimori Fujitsu Advanced Technologies s.fujimori@jp.fujitsu.com
Modeling Pre/de-emphasis buffers with [Driver Schedule]
![Modeling Pre/de-emphasis buffers with [Driver Schedule]](/thumbs/77/74906990.jpg "Modeling Pre/de-emphasis buffers with [Driver Schedule]")
Modeling Pre/de-emphasis buffers with [Driver Schedule] IBIS Summit at DesignCon 2005 Santa Clara Convention Center, CA January 31, 2005 Arpad Muranyi Signal Integrity Engineering Intel Corporation arpad.muranyi@intel.com
IBIS Model Simulation with R/L/C_dut. Xuefeng Chen Asian IBIS Summit Meeting Shanghai, China November 11, 2016
IBIS Model Simulation with R/L/C_dut Xuefeng Chen Asian IBIS Summit Meeting Shanghai, China November 11, 2016 Outline Introduction of IBIS R/L/C_dut subparameters IBIS algorithm enhancement for R/L/C_dut
IBIS PDN Feature Studies
IBIS PDN Feature Studies Randy Wolff Micron Technology Lance Wang IO Methodology DAC IBIS Summit San Diego, CA, USA based on 2011 European IBIS Summit presentation and updates 2010 Micron Technology, Inc.
Using IBIS-AMI in the Modeling of Advanced SerDes Equalization for Serial Link Simulation
Using IBIS-AMI in the Modeling of Advanced SerDes Equalization for Serial Link Simulation CDNLive Boston August 2013 Mark Marlett and Mahesh Tirupattur, Analog Bits Ken Willis and Kumar Keshavan, Cadence
AMI Applications in High-speed Serial Channel Analysis and Measurement Correlation
AMI Applications in High-speed Serial Channel Analysis and Measurement Correlation Jia Wei, Sunanbing, Zhu ShunLin Jia.wei@zte.com.cn, sun.anbing@zte.com.cn, Zhu.shunlin@zte.com.cn High-Speed System Lab,ZTE
AN-715 APPLICATION NOTE One Technology Way P.O. Box 9106 Norwood, MA Tel: 781/ Fax: 781/
APPLICATION NOTE One Technology Way P.O. Box 9106 Norwood, MA 02062-9106 Tel: 781/329-4700 Fax: 781/326-8703 www.analog.com A First Approach to IBIS Models: What They Are and How They Are Generated by
Parag Choudhary Engineering Architect
Parag Choudhary Engineering Architect Agenda Overview of Design Trends & Designer Challenges PCB Virtual Prototyping in PSpice Simulator extensions for Models and Abstraction levels Examples of a coding
IBIS Quality Review. IBIS Summit Meeting Design Automation Conference, San Francisco, California, July 28, 2009
IBIS Summit Meeting Design Automation Conference, San Francisco, California, July 28, 2009 IBIS Quality Review A status review of the IBIS Quality specification Mike LaBonte, Cisco Systems (Presented by
IBIS Package Proposal. Walter Katz Signal Integrity Software, Inc. IBIS Summit, Santa Clara January 31, 2014
IBIS Package Proposal Walter Katz Signal Integrity Software, Inc. IBIS Summit, Santa Clara January 31, 2014 Overview Decisions Made What These Decisions Mean Intent of this proposed syntax New Keywords
Automated AMI Model Generation & Validation
Automated AMI Model Generation & Validation José Luis Pino Amolak Badesha Agilent EEsof EDA Manuel Luschas Antonis Orphanou Halil Civit Asian IBIS Summit, Shenzhen China November 9, 2010 (Presented previously
PCB Design Tools User Guide
PCB Design Tools User Guide Intel Quartus Prime Pro Edition Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents 1. Signal Integrity
Interconnect Modeling Update - EMD Specification
Interconnect Modeling Update - EMD Specification Randy Wolff Micron Technology 2013 European IBIS Summit Paris, France 2013 Micron Technology, Inc. All rights reserved. Products are warranted only to meet
PARAMETER SYMBOL MIN MAX Address Access Time
TECHNICAL NOTE TN-00-17 TIMING SPECIFICATION DERATING FOR HIGH CAPACITANCE OUTPUT LOADING Introduction Memory systems are varied in the number of controllers, memory, and other devices that may share a
IBIS-AMI Modeling Using Scripts and Spice Models
IBIS-AMI Modeling Using Scripts and Spice Models Asian IBIS Summit Shanghai, China November 13th, 2017 (Previously presented October 18 th, 2017) Wei-hsing Huang, SPISim Wei-hsing.Huang@spisim.com 1 Agenda:
IBIS FORUM I/O BUFFER MODELING COOKBOOK
IBIS FORUM I/O BUFFER MODELING COOKBOOK Revision 2.0X (under development) Prepared By: The IBIS Open Forum Senior Editor: Stephen Peters Intel Corp. Sept 24, 1997 * Trademarks are the properties of their
Validating and Using IBIS Files
National Semiconductor Corp. Interface Products Group Overview The IBIS (Input/Output Buffer Information Specification) behavioral model is widely used for high- and faster, speed designs to evaluate Signal
IBIS 4.1 Macromodel Library for Simulator Independent Modeling
IBIS 4.1 Macromodel Library for Simulator Independent Modeling Arpad Muranyi, Mike LaBonte, Todd Westerhoff Sam Chitwood, Ian Dodd, Barry Katz, Scott McMorrow, Bob Ross, Ken Willis 1 Agenda History How
Extraction of Parasitic Capacitance and Resistances for HSPICE Simulation
Extraction of Parasitic Capacitance and Resistances for HSPICE Simulation Make the layout window active and select Calibre > Run PEX from the top menu bar to start a Parasitic EXtraction. You will need
IBIS QUALITY SPECIFICATION
IBIS QUALITY SPECIFICATION Version 2.0 Ratified October 30, 2009 IBIS Quality Specification Version 2.0 page 1 Purpose This document is a specification covering a methodology to enhance the quality of
IBIS-ISS: What It Is and What It Means to You
IBIS-ISS: What It Is and What It Means to You Michael Mirmak Intel Corporation Chair, IBIS Open Forum マイケルマ一マク インテルコ一ポレ一ション 会長, アイビス IBIS Summit Tokyo November 15, 2010 Originally presented in Shenzhen
Serial Link Analysis and PLL Model
25. July 2007 Serial Link Analysis and PLL Model September 11, 2007 Asian IBIS Summit, Beijing China Huang Chunxing huangchunxing@huawei.com www.huawei.com HUAWEI TECHNOLOGIES Co., Ltd. Agenda High-speed
Status Report IBIS 4.1 Macro Working Group
Status Report IBIS 4.1 Macro Working Group IBIS Open Forum Summit July 25, 2006 presented by Arpad Muranyi, Intel IBIS-Macro Working Group Intel - Arpad Muranyi Cadence Lance Wang, Ken Willis Cisco - Mike
Modeling DDR3 with IBIS
Modeling DDR3 with IBIS Randy Wolff, Micron Technology DesignCon 2008 IBIS Summit Products are warranted only to meet Micron s production data sheet specifications. Information, products and/or specifications
Product Information. IC Outputs Terms & Definitions
Product Information IC Outputs Terms & Definitions These terms and their definitions are taken from EIA/JEDEC Standard No. 99-A, Terms, Definitions, and Letter Symbols for Microelectronic Devices, clause
SystemVision Example: H-Bridge SPICE Motor Controller
SystemVision Example: H-Bridge SPICE Motor Controller Copyright Mentor Graphics Corporation 2003 All Rights Reserved. This document contains information that is proprietary to Mentor Graphics Corporation.
High-side Power Distribution Switch NCT3521U
High-side Power Distribution Switch NCT3521U -Table of Content- 1. GENERAL DESCRIPTION...1 2. FEATURES...1 3. APPLICATIONS...2 4. PIN CONFIGURATION AND DESCRIPTION...2 5. TYPICAL APPLICATION CIRCUIT...3
Predicting BER with IBIS-AMI: experiences correlating SerDes simulations and measurement
Predicting BER with IBIS-AMI: experiences correlating SerDes simulations and measurement Todd Westerhoff (SiSoft) Mike Steinberger (SiSoft) Walter Katz (SiSoft) Barry Katz (SiSoft) Adge Hawes (IBM) Kent
Simulation Using IBIS Models and Pin Mapping Issues
Power/Gnd Simulation Using IBIS Models and Pin Mapping Issues Raj Raghuram Sigrity, Inc. IBIS Summit Meeting, Sep. 13, 2001 2/14/96 Outline Motivation automated Power/Gnd simulation Example of Power/Gnd
Adding scalability to IBIS using AMS languages. Paul R. Fernando
ABSTRACT FERNANDO, PAUL R. Adding scalability to IBIS using AMS languages. (Under the direction of Dr. Paul Franzon.) From 1993 to about 1998, IBIS remained THE digital IO buffer model format. But as the
PCI-3E. PCI Interface Card Page 1 of 7. Description. Features
Page 1 of 7 class="notice" style="color:#a82a2f;font-weight:bold">the PCI-3E does not support Windows 7 Operating System. Please see our USB4 interface product which is Windows 7 compatible. The PCI-3E
Using S-parameters for behavioral interconnect modeling
欢迎与会的各位专家! Using S-parameters for behavioral interconnect modeling Asian IBIS Summit Zhu ShunLin 朱顺临 High-Speed System Lab, EDA Dept. ZTE Corporation Zhu.shunlin@zte.com.cn October 27, 2006 Agenda Using
HEADER SECTION (.ibs,.pkg,.ebd) Version 1.1 Version 2.1 Version 3.2 Version 4.2 Version 5.1 Version 6.0. TOP-LEVEL KEYWORDS (with END Keywords)
IBIS EVOLUTION (IBIS, PACKAGE, ELECTRICAL BOARD DESCRIPTION, EMI, SSO, ALGORITHMIC MODELING INTERFACE) Bob Ross, July 25, 2006, updated September 14, 2007, September 8, 2013, April 20, 2014 HEADER SECTION
INTEGRATED CIRCUITS APPLICATION NOTE. AN252 Live Insertion Aspects of Philips Logic Families. Author: Mike Magdaluyo July Philips Semiconductors
INTEGRATED CIRCUITS APPLICATION NOTE Live Insertion Aspects of Philips Logic Families Author: Mike Magdaluyo July 1999 Philips Semiconductors Author: Mike Magdaluyo, Philips Semiconductors, Sunnyvale INTRODUCTION
HIPEX Full-Chip Parasitic Extraction. Summer 2004 Status
HIPEX Full-Chip Parasitic Extraction Summer 2004 Status What is HIPEX? HIPEX Full-Chip Parasitic Extraction products perform 3D-accurate and 2D-fast extraction of parasitic capacitors and resistors from
Hipex Full-Chip Parasitic Extraction
What is Hipex? products perform 3D-accurate and 2D-fast extraction of parasitic capacitors and resistors from hierarchical layouts into hierarchical transistor-level netlists using nanometer process technology
Simulation and Modeling for Signal Integrity and EMC
Simulation and Modeling for Signal Integrity and EMC Lynne Green Sr. Member of Consulting Staff Cadence Design Systems, Inc. 320 120th Ave NE Bellevue, WA 98005 USA (425) 990-1288 http://www.cadence.com
Addressing the Power-Aware Challenges of Memory Interface Designs
Addressing the Power-Aware Challenges of Memory Interface Designs One of the toughest challenges in designing memory interfaces is accurately measuring timing while also considering fluctuations in power
MC74C Digit BCD Display Controller/Driver. General Description. Ordering Code: Connection Diagram. Features. Version 1.0
6-Digit BCD Display Controller/Driver General Description The display controllers are interface elements, with memory, that drive a 6-digit, 8-segment LED display. The display controllers receive data
2-Wire, 5-Bit DAC with Three Digital Outputs
Rev 1; 6/4 2-Wire, 5-Bit DAC with Three Digital Outputs General Description The is a 5-bit digital-to-analog converter (DAC) with three programmable digital outputs. The communicates through a 2-wire,
Chapter 7 Using IBIS Models
Chapter 7 Using IBIS Models The Input/Output Buffer Information Specification (IBIS) is being developed by the IBIS Open Forum, which is affiliated with the Electronic Industries Alliance (EIA). IBIS specifies
Parameter Sweep. Description. Setup. Parameters. Modified by on 13-Sep-2017
Parameter Sweep Old Content - visit altium.com/documentation Modified by on 13-Sep-2017 Description The Parameter Sweep feature allows you to sweep the value of a device in defined increments, over a specified
A Tour of the IBIS Quality Specification DesignCon East IBIS Summit April 5, 2004
A Tour of the IBIS Quality Specification DesignCon East IBIS Summit April 5, 2004 Robert Haller rhaller@sisoft.com Signal Integrity Software, Inc. 6 Clock Tower Place Suite 250 Maynard MA. 01754 978-461
3. Implementing Logic in CMOS
3. Implementing Logic in CMOS 3. Implementing Logic in CMOS Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 27 September, 27 ECE Department,
2-Bit Bidirectional Voltage-Level Translator with Auto Direction sensing and ±15kV ESD Protection UM3302H CSP UM3302Q QFN
2-Bit Bidirectional oltage-level Tralator with Auto Direction seing and ±15k ESD Protection UM3302H CSP8 1.90 0.90 UM3302Q QFN8 1.40 1.20 General Description The UM3302, a ESD protected level tralator,
IBIS Model Validation Review. Lance Wang IBIS Asian Summit 2012 Nov. 16, 2012 Yokohama, Japan
IBIS Model Validation Review Lance Wang lwang@iometh.com IBIS Asian Summit 2012 Nov. 16, 2012 Yokohama, Japan TM Outlines Motivation History Method Review Common Mistakes Conclusion 2006-2012 IO Methodology
Chapter 23. Using Meta I/O
Chapter 23 Meta I/O converts I/O buffer models between Star-Hspice format and the I/O Buffer Information Specification (IBIS) Version 2.1 format. Meta I/O is not part of Star-Hspice, but is an optional
MAX9210/MAX9214/ MAX9220/MAX9222. Programmable DC-Balance 21-Bit Deserializers. Features. General Description. Applications. Ordering Information
General Description The MAX9210/MAX9214/ deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/ LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing
Cadence Tutorial A: Schematic Entry and Functional Simulation Created for the MSU VLSI program by Andrew Mason and the AMSaC lab group.
Cadence Tutorial A: Schematic Entry and Functional Simulation Created for the MSU VLSI program by Andrew Mason and the AMSaC lab group. Revision Notes: Aug. 2003 update and edit A. Mason add intro/revision/contents
RC Extraction. of an Inverter Circuit
RC Extraction of an Inverter Circuit Santa Clara University Department of Electrical Engineering Under Guidance of Dr Samiha Mourad & Dr Shoba Krishnan Date of Last Revision: February 1, 2010 Copyright
PDK-Based Analog/Mixed-Signal/RF Design Flow 11/17/05
PDK-Based Analog/Mixed-Signal/RF Design Flow 11/17/05 Silvaco s What is a PDK? Which people build, use, and support PDKs? How do analog/mixed-signal/rf engineers use a PDK to design ICs? What is an analog/mixed-signal/rf
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Lab #2: Layout and Simulation
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Lab #2: Layout and Simulation NTU IC541CA 1 Assumed Knowledge This lab assumes use of the Electric
Explore your design space including IBIS AMI models with Advanced Channel Simulation
Explore your design space including IBIS AMI models with Advanced Channel Simulation Heidi Barnes Vincent Poisson Presenter: May, 2013 Agenda How good is my PHY? Channel Simulation Options Spice (Circuit
The 3S Proposal: A SPICE Superset Specification for Behavioral Modeling
The 3S Proposal: A SPICE Superset Specification for Behavioral Modeling Michael Mirmak Intel Corporation June 5, 2007 Legal Disclaimer THIS DOCUMENT AND RELATED MATERIALS AND INFORMATION ARE PROVIDED "AS
BLOCK DIAGRAM PIN ASSIGNMENT ICS LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL- TO-LVDS FANOUT BUFFER PRELIMINARY ICS854210
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL- TO-LVDS FANOUT BUFFER ICS854210 GENERAL DESCRIPTION The ICS854210 is a low skew, high performance ICS dual 1-to-5 Differential-to-LVDS Fanout Buffer HiPerClockS and
DS2405. Addressable Switch PIN ASSIGNMENT
www.maxim-ic.com FEATURES Open-drain PIO pin is controlled by matching 64-bit, laser-engraved registration number associated with each device Logic level of open drain output can be determined over 1-Wire
TUTORIAL How to Use the SPICE Module
TUTORIAL How to Use the SPICE Module November 2017 1 1. Overview The SPICE Module is an add-on option in PSIM. Powered by CoolSPICE developed by CoolCAD Electronics LLC., the SPICE Module provides a SPICE
Sensitivity Analysis of IBIS-parameters with HSPICE
Sensitivity Analysis of IBIS-parameters with HSPICE Manfred Maurer Email: manfred.maurer@siemens.com DATE 2004 IBIS Summit Meeting Paris 2004 Overview Motivation Sensitivity analysis main focus of the
Solving the challenges posed by Chip/Package/Board Co-Design
Solving the challenges posed by Chip/Package/Board Co-Design Identify and locate sources of unwanted coupling Simulation link to EM: Critical Interconnect, Vias, Discontinuities, Embedded Passives, etc
I/O Simulations Using HSPICE Writer
I/O Simulations Using HSPICE Writer June 2006, ver. 1.0 Application Note 424 Introduction As edge rates and I/O speeds increase, traditional I/O design methodology (such as those methods that use approximate
TPZ013GV3 TSMC 0.13um Standard I/O Library. Databook
TPZ013GV3 TSMC 0.13um Standard I/O Library Databook Version 220C May 11, 2007 Copyright 2007 Taiwan Semiconductor Manufacturing Company Ltd. All Rights Reserved No part of this publication may be reproduced
ONYX-MM-XT PC/104 Format Counter/Timer & Digital I/O Module
ONYX-MM-XT PC/104 Format Counter/Timer & Digital I/O Module User Manual V1.4 Copyright 2009 Diamond Systems Corporation 1255 Terra Bella Avenue Mountain View, CA 94043 USA Tel (650) 810-2500 Fax (650)
DesignConEast 2005 Track 6: Board and System-Level Design (6-TA4)
DesignConEast 2005 Track 6: Board and System-Level Design (6-TA4) Performance Model for Inter-chip Busses Considering Bandwidth and Cost Authors: Brock J. LaMeres, University of Colorado / Sunil P. Khatri
FPGA Power Management and Modeling Techniques
FPGA Power Management and Modeling Techniques WP-01044-2.0 White Paper This white paper discusses the major challenges associated with accurately predicting power consumption in FPGAs, namely, obtaining
IBIS-AMI Modeling and Simulation of 56G PAM4 Link Systems
IBIS-AMI Modeling and Simulation of 56G PAM4 Link Systems Hongtao Zhang, hongtao@xilinx.com Fangyi Rao, fangyi_rao@keysight.com Xiaoqing Dong, dongxiaoqing82@huawei.com Geoff Zhang, geoffz@xilinx.com Outline
TITLE. Chip and Package-Level Wideband EMI Analysis for Mobile DRAM Devices. Jin-Sung Youn (Samsung Electronics)
TITLE Chip and Package-Level Wideband EMI Analysis for Mobile DRAM Devices Jin-Sung Youn (Samsung Electronics) Image Jin-Sung Youn, Jieun Park, Jinwon Kim, Daehee Lee, Sangnam Jeong, Junho Lee, Hyo-Soon
Conditional Expressions in IBIS-AMI (updated from Feb 2010)
Adge Hawes Development Architect, IBM 15 June 2010 Conditional Expressions in IBIS-AMI (updated from Feb 2010) IBIS Summit, DAC 2010, Anaheim, California The Need for Conditional Expressions AMI Configuration
SPISim StatEye/AMI User s Guide
SPISim StatEye/AMI User s Guide Latest Version: V20180315 SPISim LLC Vancouver, WA 98683, USA Tel. +1-408-905-6692 http://www.spisim.com This user s guide describes the SPISim s StatEye channel analysis
IBIS-ATM Update: SerDes Modeling and IBIS
IBIS-ATM Update: SerDes Modeling and IBIS (Originally presented at the Sept 11 th Summit in Beijing) Presented by: Todd Westerhoff, SiSoft twesterh@sisoft.com IBIS Summit Tokyo, Japan September 14, 2007
ICS548A-03 LOW SKEW CLOCK INVERTER AND DIVIDER. Description. Features. Block Diagram DATASHEET
DATASHEET ICS548A-03 Description The ICS548A-03 is a low cost, low skew, high-performance general purpose clock designed to produce a set of one output clock, one inverted output clock, and one clock divided-by-two.
Understanding IBIS-AMI Simulations
Understanding IBIS-AMI Simulations IBIS European Summit SPI, Turin, Italy May 11, 2016 Richard Allred, Signal Integrity Software Agenda IBIS-AMI Assumptions & Terminology IBIS-AMI Model Components Analysis
Model Connection Protocol extensions for Mixed Signal SiP
Model Connection Protocol extensions for Mixed Signal SiP Taranjit Kukal (kukal@cadence.com) Dr. Wenliang Dai (wldai@cadence.com) Brad Brim (bradb@sigrity.com) Presented by: Yukio Masuko Cadence Note:
Modeling Power Electronics Components Using SimElectronics and SimPowerSystems Vivek Raju Application Engineer
Modeling Power Electronics Components Using SimElectronics and SimPowerSystems Vivek Raju Application Engineer 2014 The MathWorks, Inc. 1 Key Takeaway Modeling Power Electronics Components Using SimElectronics
BIRD AMI Model New IBIS Support
Industrial Solutions and Services Your Success is Our Goal BIRD 104.1 AMI Model New IBIS Support Manfred Maurer manfred.maurer@siemens.com www.siemens.de/edh Manfred Maurer Folie 1 Classical Way of IBIS
A Proposal for Developing S2IBISv3
A Proposal for Developing S2IBISv3 Paul Franzon Michael Steer Automated Design Tools for Integrated Mixed Signal Microsystems (NeoCAD) Outline Background DARPA Program NeoCad Program Objectives Program
PIXI click PID: MIKROE Weight: 28 g
PIXI click PID: MIKROE-2817 Weight: 28 g PIXI click is equipped with MAX11300 IC from Maxim Integrated, which features Maxim Integrated's versatile, proprietary PIXI technology - it is the industry's first
GL116 ENCODER/DECODER MANUAL GLOLAB CORPORATION
GL ENCODER/DECODER MANUAL GLOLAB CORPORATION Thank you for buying our GL Encoder / Decoder Module. This device was developed in response to many requests for an encoder and decoder that would serialize
A Tale of Two Parsers
Page 1 A Tale of Two Parsers Bob Ross DesignCon 2012 IBIS Summit Santa Clara, California February 2, 2012 bob@teraspeed.com (Some content given at Asian Summits Nov. 15, 18, 21, 2011) 2012Teraspeed Consulting
DS kbit Add-Only Memory
1 kbit Add-Only Memory www.dalsemi.com FEATURES 1024 bits Electrically Programmable Read Only Memory (EPROM) communicates with the economy of one signal plus ground Unique, factory-lasered and tested 64-bit
Overvoltage-Protection Controllers with a Low RON Internal FET MAX4970/MAX4971/MAX4972
19-4139; Rev 1; 8/08 Overvoltage-Protection Controllers General Description The family of overvoltage protection devices features a low 40mΩ (typ) R ON internal FET and protect low-voltage systems against
Cadence Virtuoso Schematic Design and Circuit Simulation Tutorial
Cadence Virtuoso Schematic Design and Circuit Simulation Tutorial Introduction This tutorial is an introduction to schematic capture and circuit simulation for ENGN1600 using Cadence Virtuoso. These courses
PART TOP VIEW. TO LOAD SINGLE Li+ CELL TO IN LOGIC OUT. Maxim Integrated Products 1
19-224; Rev 2; 6/3 USB-Powered Li+ Charger General Description The is a single-cell lithium-ion (Li+) battery charger that can be powered directly from a USB port* or from an external supply up to 6.5V.
Logic Chip Tester User Manual SW Version /8/2012. Chapter 1 Introduction/Background
Logic Chip Tester User Manual SW Version 1.00 4/8/2012 Chapter 1 Introduction/Background In the 1970 s and 80 s, many digital devices were designed using a number of 14, 16, 20, or perhaps 24- pin logic
CHAPTER 4 I/O PORT PROGRAMMING
CHAPTER 4 I/O PORT PROGRAMMING I/O Port Pins The four 8-bit I/O ports P0, P1, P2 and P3 each uses 8 pins All the ports upon RESET are configured as input, ready to be used as input ports When the first
TUTORIAL 1. V1.1 Update on Sept 17, 2003 ECE 755. Part 1: Design Architect IC
TUTORIAL 1 V1.1 Update on Sept 17, 2003 ECE 755 Part 1: Design Architect IC DA-IC provides a design environment comprising tools to create schematics, symbols and run simulations. The schematic editor
DS2430A 256-Bit 1-Wire EEPROM
256-Bit 1-Wire EEPROM www.maxim-ic.com FEATURES 256-bit Electrically Erasable Programmable Read Only Memory (EEPROM) plus 64-bit one-time programmable application register Unique, factory-lasered and tested
EE 471: Transport Phenomena in Solid State Devices
EE 471: Transport Phenomena in Solid State Devices HW7 Due: 4/17/18 For this homework, you will download a free PC version of the industry standard SPICE circuit simulator called LTspice, provided by Linear
Parameter Symbol Min Max Unit
Features: Supports 9.95Gb/s to 11.3Gb/s bit rates Hot-pluggable XFP footprint Maximum link length of 20km 1310nm DFB laser transmitter. Duplex LC connector Power dissipation
±15kV ESD-Protected, Single/Dual/Octal, CMOS Switch Debouncers
19-477; Rev 1; 1/99 ±15k ESD-Protected, Single/Dual/Octal, General Description The are single, dual, and octal switch debouncers that provide clean interfacing of mechanical switches to digital systems.
M A S S A C H U S E T T S I N S T I T U T E O F T E C H N O L O G Y DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE
M A S S A C H U S E T T S I N S T I T U T E O F T E C H N O L O G Y DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE 6.004 Computation Structures Lab #4 In this laboratory exercise, we ll build
TUTORIAL How to Use the SPICE Module
TUTORIAL How to Use the SPICE Module February 2018 1 1. Overview The SPICE Module is an add-on option in PSIM. Powered by CoolSPICE developed by CoolCAD Electronics LLC., the SPICE Module provides a SPICE
Features VCC MIC1810 RESET RESET
Microprocessor Reset Circuit General Description The is an inexpensive microprocessor supervisory circuit that monitors power supplies in microprocessor based systems. The function of these devices is
Integrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 23-1 guntzel@inf.ufsc.br Semiconductor Memory Classification