DesignConEast 2005 Track 6: Board and System-Level Design (6-TA4)

Transcription

1 DesignConEast 2005 Track 6: Board and System-Level Design (6-TA4) Performance Model for Inter-chip Busses Considering Bandwidth and Cost Authors: Brock J. LaMeres, University of Colorado / Sunil P. Khatri Texas A&M University Performance Model for Inter-chip Busses 1

2 Problem Statement Performance in VLSI Systems is Limited by Noise from the Package An Analytical Model for System Performance is needed for: 1) CAD/CAE 2) Quick Hand Calculations Performance Model for Inter-chip Busses 2

3 Agenda 1) Problem Motivation 2) Analytical Model Development 3) Simulation Results 4) Example Use Model Performance Model for Inter-chip Busses 3

4 Problem : Packaging Limits Performance Transistor Technology is Faster than Package Technology IC Moore s Law - # of transistors will double every 18 months Package Rent s Rule - # of I/O will double in next 10 years Performance Model for Inter-chip Busses 4

5 Problem : Packaging Limits Performance Today s Packages Have Inductive Parasitics QFP Wire Bond (~4.5nH) BGA Wire Bond (~3.7nH) Performance Model for Inter-chip Busses 5

6 Problem : Packaging Limits Performance Inductive Interconnect Causes Noise When Signals Switch: 1) Supply Bounce 2) Pin-to-Pin Coupling Simultaneous Switching Noise (SSN) Performance Model for Inter-chip Busses 6

7 Problem : Packaging Limits Performance 1) Supply Bounce Switching current through inductive packaging induces voltage: V bnc di = L dt L = Inductance of pwr/gnd pin that current is being switched through. Multiple Signals Switching Increase the Problem: V bnc n di = L i dt n = # of drivers sharing the power/gnd pin (L). Performance Model for Inter-chip Busses 7

8 Problem : Packaging Limits Performance 2) Pin-to-Pin Coupling Switching Signals Couple Voltage onto Neighbors: V couple k = 1k Multiple Signals Switching Increase the Problem: V couple M di dt di k k = M1 k 1 dt M = Mutual Inductance between package interconnects. Performance Model for Inter-chip Busses 8

9 Problem : Packaging Limits Performance Package Inductance Creates Simultaneous Switching Noise SSN SSN in Package Limits di/di di SSN dt Performance Model for Inter-chip Busses 9

10 Problem : Packaging Limits Performance Aggressive Package Design will Reduce Inductance QFP Wire Bond : 4.5nH $0.22 / pin BGA Wire Bond : 3.7nH $0.34 / pin BGA Flip-Chip : 1.2nH $0.63 / pin But is Expensive - 95% of VLSI design-starts are wire-bond Performance Model for Inter-chip Busses 10

11 Problem : Packaging Limits Performance Modern Design Practice 1) Acceptable SSN Limits are Defined. 2) Fastest (di/dt) is selected that doesn t violate limits. Limitations of Approach SPICE is used to evaluate SSN. This takes too much time. The entire range of variables cannot be evaluated quickly (package, # of pwr/gnd, bus width, etc ). Performance Model for Inter-chip Busses 11

12 Problem : Packaging Limits Performance We need an Analytical Model to Evaluate Off-Chip Bus Performance 1) Package Parasitics 2) Package Cost 3) Bus Width 4) # of Power/Grounds This can be used to find Optimal Bus Configuration Desired Performance for the Least Cost Performance Model for Inter-chip Busses 12

13 Test Circuit Topology Analytical Model - 0.1um CMOS Tx/Rx v VDD, 0.35 Vt - 25mA Drive Strength - Series Terminated Performance Model for Inter-chip Busses 13

14 Analytical Model Failure Modes Power Supply Droop Signal Coupling Ground Bounce Power Supply Droop = Ground Bounce Performance Model for Inter-chip Busses 14

15 Analytical Model Bus Parameters P S S G S S P S S G S S P S S G S S P SIG SIG GND SIG SIG WBUS WBUS : # of Signals Per Bus Segment of Interest Performance Model for Inter-chip Busses 15

16 Analytical Model Bus Parameters P S S G S S P S S G S S P S S G S S P SIG SIG GND SIG SIG NG NG : # of Grounds Per Bus Segment of Interest Performance Model for Inter-chip Busses 16

17 Analytical Model Bus Parameters P S S G S S P S S G S S P S S G S S P Repetitive Pattern of Signal, Power, and Ground Pins SPG : (# of Signals) : (# of PWR s) : (# of GND s) SPR : SPG Ratio Performance Model for Inter-chip Busses 17

18 Analytical Model Bus Parameters P S S G S S P S S G S S P S S G S S P PWR SIG SIG GND SIG SIG Example: WBUS : 4 NG : 1 SPG : 4:1:1 SPR : 4 Performance Model for Inter-chip Busses 18

19 Analytical Model Bus Performance Description Slewrate v(t) dv dt slewrate dv di = = dt dt Z load t Performance Model for Inter-chip Busses 19

20 Analytical Model Bus Performance Description Risetime 90% v(t) (0.8) VDD VDD 10% t rise = (0.8) VDD slewrate t Performance Model for Inter-chip Busses 20

21 Analytical Model Bus Performance Description Minimum Unit Interval DATA DATA DATA UI UI min = (1.5) trise = 1 DR max Performance Model for Inter-chip Busses 21

22 Analytical Model Bus Performance Description Bus Throughput DATA DATA DATA DATA DATA DATA Tx WBUS Rx DATA DATA DATA TP = W DR max BUS max Performance Model for Inter-chip Busses 22

23 Bus Performance Limits Analytical Model P S S G S S P S S G S S P S S G S S P SIG SIG GND SIG SIG L11 L11 : Self Inductance of Ground Path V bnc self di Wbus 1 = L11 1 dt Performance Model for Inter-chip Busses 23

24 Bus Performance Limits Analytical Model P S S G S S P S S G S S P S S G S S P SIG SIG GND SIG SIG M12 M12 M1k M13 M13 : Mutual Inductance Between Pins Wbus dik Vbnc = M couple 1k 2 dt Performance Model for Inter-chip Busses 24

25 Bus Performance Limits Analytical Model Maximum Acceptable Ground Bounce v(t) p VDD VDD V NOISE = p V bnc MAX DD t (ptypical = 5%) Performance Model for Inter-chip Busses 25

26 Model Development Maximum Ground Bounce Analytical Model W W bus bus L 11 di di Vgnd bnc = p VDD = + M 1k N g dt k = 2 dt Self Contribution Coupling Contribution Performance Model for Inter-chip Busses 26

27 Model Development Maximum Slewrate Analytical Model dv pv = dt W L DD Z load Wbus max bus 11 + N g k = 2 M 1k - pull out (di/dt) - convert to (dv/dt) Performance Model for Inter-chip Busses 27

28 Model Development Minimum Risetime Analytical Model t rise min = W L N W bus bus 11 ( 0.8) + ( M ) g p Z load k = 2 1k - convert slewrate to risetime Performance Model for Inter-chip Busses 28

29 Model Development Maximum Datarate DR max = Analytical Model Wbus bus 11 + N g k = 2 ( 1.5) ( 0.8) p Z W load L M 1k - convert Risetime to Datarate Maximum Throughput TP = W DR max BUS max Performance Model for Inter-chip Busses 29

30 Experimental Results SPICE Simulations were Performed on Three Packages QFP Wire Bond BGA Wire Bond BGA Flip-Chip Performance Model for Inter-chip Busses 30

31 Experimental Results QFP Wire-Bond Package Simulations Per-Pin Data-Rate Bus Throughput Model Simulation - Throughput reaches an asymptotic limit as channels are added Performance Model for Inter-chip Busses 31

32 Experimental Results BGA Wire-Bond Package Simulations Per-Pin Data-Rate Bus Throughput - Level 1 : BGA Increases Performance Over QFP Performance Model for Inter-chip Busses 32

33 Experimental Results BGA Flip-Chip Package Simulations Per-Pin Data-Rate Bus Throughput - Level 2: Flip-Chip Increases Performance Over Wire-Bond Performance Model for Inter-chip Busses 33

34 Experimental Results Cost Must Also Be Considered in Analysis Bandwidth Per Cost BPC TP = 6 Costbus 1e Units = (Mb/$) This Metric Represents Cost Effectiveness of the Bus Performance Model for Inter-chip Busses 34

35 Cost per Bus Configuration Experimental Results $ Performance Increases with Cost (Package, SPG) Performance Model for Inter-chip Busses 35

36 Bandwidth Per Cost Results Experimental Results Faster Narrower Busses = More Cost Effective Performance Model for Inter-chip Busses 36

37 Example PACKAGE - Rent s Rule IC Core - Moore s Law On-Chip - 8 bit Data Bus Mb/s Package - Need (8)(300M) = 2400 Mb/s Performance Model for Inter-chip Busses 37

38 Example Need: 2400 Mb/s X X X X QFP Wire Bond BGA Wire Bond BGA Flip-Chip - 4 bits wide, SPG=2:1:1-1 bit wide, SPG=2:1:1-1 bit wide, SPG=2:1:1-16 bits wide, SPG=4:1:1-1 bit wide, SPG=4:1:1-1 bit wide, SPG=8:1:1 Performance Model for Inter-chip Busses 38

39 Example Cost of Each Bus Configuration Most Cost Effective: -BGA-WB -Wbus = 1 -SPG = 2:1:1 Performance Model for Inter-chip Busses 39

40 Example Bandwidth-per-Cost of Each Bus Configuration Higher BPC = More Headroom Performance Model for Inter-chip Busses 40

41 Summary 1) Package Noise Limits System VLSI Performance 2) An Analytical Model was Presented to Predict Bus Performance 3) Datarate Approaches an Asymptotic Limit as Channels are Added 4) Throughput Can be Achieved Using Different Bus Configurations Performance Model for Inter-chip Busses 41

42 Questions? Performance Model for Inter-chip Busses 42