Microprocessor and DSP Technologies for the Nanoscale Era

Transcription

1 Microprocessor and DSP Technologies for the Nanoscale Era Seminar 1 Ram Kumar Krishnamurthy Microprocessor Research Labs Intel Corporation, Hillsboro, OR ram.krishnamurthy@intel.com 1 July 5, 2005 Intel Labs

2 About Circuits Research Lab Established 1996 Belongs under Microprocessor Technology Labs Located in Hillsboro, Oregon, USA (primary) and Bangalore, India 75 researchers Charter: High-performance & low-power digital circuits Off-chip I/O signaling circuits Power delivery circuits >50 patents, >25 papers per year 2 Intel Labs

3 Motivation: Higher performance at lower power and cost MIPS Pentium 4 Architecture Pentium Pro Architecture Pentium Architecture Strong demand for > 1 TIPS performance beyond this decade How do you get there?

4 Our Research Agenda Outlook Technology Node (nm) Integration Capacity (BT) Delay = CV/I scaling ~0.7 >0.7 Delay scaling will slow down 8 Energy/Logic Op scaling Bulk Planar CMOS Alternate, 3G etc Variability >0.35 >0.5 >0.5 Energy scaling will slow down High Probability Low Probability Low Probability High Probability Medium High Very High ILD (K) ~3 <3 Reduce slowly towards RC Delay Metal Layers to 1 layer per generation Internal University FCRP(MARCO) 4

5 Intel s Research Focus 1 Technology Leadership Gate Length 1000 Industry 0.1 Intel nm Complete solution stack Technology Arch & Design Platforms Software 5

6 Architectures & Designs Back End Server Server Desktop Mobile Handheld Family Itanium Itanium Xeon Pentium Celeron Centrino Pentium Xscale Architecture IA64, VLIW IA64/ IA32 IA32 IA32 ARM Word 64 bit 64 bit Itanium 32 bit Xeon 32 bit 32 bit 32 bit Address Space Huge Huge/4 GB 4 GB 4 GB 4 GB Cache Performance 6 MB 6 MB, 2 MB 1 MB 1 MB 512 KB High High High Medium Low Power ~130W ~100 W < 100 W ~25 W < 1W Power Metric Watts/sq ft Watts/cu ft Watts Watt-hours Battery Life Cost High High Med Med Low 6 Our research agenda addresses all these platforms

7 Is Transistor a Good Switch? I = 0 I 0 On I = I = 1ma/u I = 0 I 0 Off I = 0 I 0 Sub-threshold Leakage 7

8 Sub-threshold Leakage MOS Transistor Characteristics Ids (log) Vt Exponential Increase in Ioff Vgs Ioff (na/u) Temp (C) SD Leakage (Watts) X Tr Growth 1.5X Tr Growth 0.25u 0.18u 0.13u 90nm 65nm 45nm Technology Transistors will not be switches,, but dimmers 8

9 Leakage Power Leakage Power (% of Total) 50% 40% 30% 20% 10% 0% Technology (µ) Leakage power limits Vt scaling Must stop at 50% A. Grove, IEDM

10 High Leakage Impacts Functionality Clock Pk 0 I Leak Dyn_out M 11 M 1j M 1K M 21 M 2j M 2K INV_out Keeper / pulldown ratio 1.6 Sub-70nm X 3X 5X 10X 20X Subthreshold + gate leakage 10 M. Anders, R. Krishnamurthy et al, 2001 Symp. VLSI Circuits Sub-65nm Dynamic Circuit Active Leakage Tolerance: Cache, RF, Arrays, Bitlines most affected Keeper sizes > 50% of pulldown strength High contention degraded performance Slow keeper shutoff high short-circuit power

11 Power Will be the Limiter Million Transistors Pentium 4 proc 386 Pentium proc 1 Billion Transistors MHz Pentium 4 proc 386 Pentium proc GHz B transistor integration capacity will exist Pentium 4 proc MIPS Pentium proc TIPS Power (Watts) Pentium 4 proc Pentium proc 1000's of Watts? Applications will demand TIPS performance But the Power Challenge: Highest performance in the power envelope

12 Power Trend Power (W) Pentium processor 386 Cooling Capacity Of Conventional System 486 Pentium II processor Pentium 4 processor Business As Usual is is Not an an Option C scales by by 30% per generation but Vcc scales by by 10-15% 15% only! Must maintain or or reduce power in in future

13 Gate Oxide is Near Limit CoSi 2 130nm Transistor 70 nm Si 3 N 4 Gate Leakage (Watts) 1.E+06 1.E+05 1.E+04 1.E+03 1.E+02 1.E+01 1.E+00 1.E-01 1.E-02 1.E X 2X During Burn-in 1.4X Vdd 0.25u 0.18u 0.13u 90nm 65nm 45nm Technology Poly Si Gate Electrode 1.5 nm Gate Oxide Si Substrate Intel s High K leadership is crucial for the industry 13

14 Power Density Will Get Even Worse 10,000 1,000 Power Density (W/cm2) Need to Keep the Junctions Cool Performance (Higher Frequency) Lower leakage (Exponential) Better reliability (Exponential) Pentium processors Pat Gelsinger, ISSCC 2001

15 Active Power Reduction Low Supply Voltage Slow Fast Slow High Supply Voltage Multiple Supply Voltages 15 Vdd Logic Block Replicated Designs Freq = 1 Vdd = 1 Throughput = 1 Power = 1 Area = 1 Pwr Den = 1 Vdd/2 Logic Block Logic Block Freq = 0.5 Vdd = 0.5 Throughput = 1 Power = 0.25 Area = 2 Pwr Den = Need high-speed multi-supply level converter techniques

16 Leakage Control Body Bias Stack Effect Sleep Transistor Vdd +Ve Vbp Equal Loading Logic Block -Ve Vbn 2-10X reduction X reduction X reduction Need low leakage and leakage tolerant techniques

17 Dual Vt Design for Active Leakage Reduction Number of paths High Vt Delay Technology provides two V t High V t with nominal I off (lower performance) Low V t with ~10X higher l off (higher performance) Employing high V t everywhere yields lower performance, and lower leakage (1X) Number of paths Low Vt Delay Employing low V t everywhere yields higher performance, but higher leakage (10X) Number of paths Dual Vt Delay Logic path between latch boundaries Selective usage of low and high V t yields higher performance, yet low leakage between 1X, and <<10X 17

18 Chip Multi-Processing C1 C3 Cache C2 C4 Relative Performance CMP ST Die Area, Power Multi-core, each core Multi-threaded Shared cache and front side bus Each core has different Vdd & Freq Core hopping to spread hot spots Lower junction temperature 18

19 Memory Latency CPU Small ~few Clocks Cache Memory Large ns Memory Latency (Clocks) Assume: 50ns Memory latency Freq (MHz) Cache miss hurts performance Worse at higher frequency Need power efficient high-speed I/O techniques

20 Increase on-die Memory Power Density (Watts/cm 2 ) Logic Memory 0.25µ 0.18µ 0.13µ 0.1µ 100% 80% 60% 40% 20% 0% Cache % of full chip area? Pentium Pentium Pentium Pro II Pentium III & 4 Pentium III Pentium 4 0.7µ 0.5µ 0.35µ 0.25µ 0.18µ 0.13µ 0.10µ Large on die memory provides: 1. Increased Data Bandwidth & Reduced Latency 2. Hence, higher performance for much lower power 20

21 Special Purpose Hardware Acceleration TCP Offload Engine 1.E+06 PLL OOO ROB Send buffer MIPS 1.E+05 1.E+04 GP TCB Exec Core TCB Exec Core ROM ROM Input seq CAM1 CLB 1.E+03 TOE 1.E mm X 3.54 mm, 260K transistors Opportunities for acceleration: Network processing engines MPEG Encode/Decode engines Speech engines Wireless communication/baseband Special purpose HW Best MIPS/Watt 21

22 Energy-efficient efficient Data-path Circuits Cache Processor thermal map Temp ( o C) Execution core Integer and FP ALUs and MACs 22 ALUs: performance and peak-current limiters High activity thermal hotspots Goal: high-performance energy-efficient design

23 23 130nm 9GHz 32-bit Integer ALU (ISSCC 02) 32-bit integer exec core Input FIFO Die Size Process Interconnect Transistors Maximum V CC Scan Ctl RF Clock Output FIFO ALU 1.61 x 1.44 mm 130nm CMOS 1 poly, 6 metal 160K 1.5 V Misc BB Ctl M. Anders, R. Krishnamurthy et al, Intl. Solid-state Circuits Conf & IEEE Journal of Solid-state Circuits 11/02 F max (GHz) Power (mw) Supply Voltage (V) Design target: 6.5GHz at 120mW Supply Voltage (V) Leakage Power (mw)

24 90nm 7GHz 64-bit Integer ALU (ISSCC 04) Clock Generator and Drivers Lower-order 32-bit ALU Upper-order 32-bit ALU I/O Circuits S. Mathew, R. Krishnamurthy et al, Intl. Solid-state Circuits Conf & IEEE Journal of Solid-state Circuits 01/05 Process Die area 64-bit ALU layout area 90nm Dual-Vt CMOS, 7 Metal 0.474mm mm 2 Total transistor count bit ALU average switching power (α=0.3)( 89mW at 4GHz, 1.3V, 25 o C 64-bit ALU active leakage power 9.6mW at 1.3V, 25 o C 64-bit ALU maximum frequency 7GHz at 2.1V, 25C 32-bit ALU average switching power (α=0.3)( 71mW at 7GHz, 1.3V, 25 o C 32-bit ALU active leakage power 4.4mW at 1.3V, 25 o C 64-bit ALU die microphotograph and measured performance summary 24 7GHz single-cycle 64-bit integer ALU ALU (measured in in 90nm CMOS) Simultaneous 9GHz single-cycle 32-bit integer ALU ALU mode Fastest reported single-cycle 64-bit integer ALU ALU performance

25 90nm 1GHz 9mW 16*16b Multiplier (ISSCC 05) Clock Generator and Drivers R-PLA Registers 16x16b Multiplier I/O Circuits 25 S. Hsu, R. Krishnamurthy et al, Intl. Solid-state Circuits Conf Process Die area 16b Multiplier and PLA layout area 90nm Dual-V CMOS t 0.474mm mm 2 16b Multiplier worst-case power 9mW at 1GHz, 1.3V, 50 o C (nominal) 16b Multiplier active leakage power 540µW W at 1.3V, 50 o C (nominal) 16b Multiplier peak performance 1.5GHz, 32mW at 1.95V, 50 o C 16b Multiplier low-voltage mode performance 50MHz, 79µW W at 0.57V, 50 o C Reconfigurable PLA peak performance 2.3GHz, 4.2mW at 1.3V, 50 C Reconfigurable PLA worst-case power 2mW at 1GHz, 1.3V, 50 o C (nominal) Stand-by mode power 75µW W (7X reduction vs. active leakage) 16*16-bit Multiplier die microphotograph and measured performance summary 1GHz single-cycle 16*16-bit DSP DSP multiplier (measured in in 90nm CMOS) Reconfigurable PLA PLA control engine 9pJ/Op or or 110GOPS/Watt Highest reported GOPS/Watt for for single-cycle 16-bit multiply

26 32-bit ALU architecture External operands External operands Mux control 6:1 Mux 6:1 Mux Shift control 5:1 Mux 2:1 Mux Adder core O/p Mux Sum Mux control Sign control Loopback bus 26 Multiple ALUs clustered together in the execution core High power density

27 Full-Adder Intro A B Cin Full adder Sum Cout 27

28 The Binary Adder A B Cin Full adder Sum Cout S = A B C i = ABC i + ABC i + ABC i + ABC i C o = AB + BC i + AC i 28

29 The Ripple-Carry Adder A 0 B 0 A 1 B 1 A 2 B 2 A 3 B 3 C i,0 C o,0 C o,1 C o,2 C o,3 FA FA FA FA (= C i,1 ) S 0 S 1 S 2 S 3 Worst case delay linear with the number of bits t d = O(N) t adder = (N-1)t carry + t sum Goal: Make the fastest possible carry path circuit 29

30 Static CMOS Full Adder V DD V DD C i A B A B A B A C i X B C i V DD C i A S C i A B B V DD A B C i A C o B 28 Transistors 30

31 Carry Look-ahead Sum i = A i B i Carry i-1 Carry i = A i B i + (A i +B i )Carry i-1 Intel Labs

32 Partial Sum Sum i = A i B i Carry i-1 Carry i = A i B i + (A i +B i )Carry i-1 Intel Labs

33 Partial Sum Sum i = A i B i Carry i-1 Carry i = A i B i + (A i +B i )Carry i-1 Generate Propagate Intel Labs

34 Partial Sum Sum i = A i B i Carry i-1 Carry i = A i B i + (A i +B i )Carry i-1 Generate Propagate Carry i = G i + P i Carry i-1 Intel Labs

35 High-performance Adders: Even input bits Kogge Stone PG Gen. CM1 CM2 CM3 CM4 CM5 XOR Sum even Odd input bits PG Gen. CM1 CM2 CM3 CM4 CM5 XOR Sum odd GG=G i +P i G i-1 GP=P i P i-1 Generate all 32 carries: 35 Full-blown binary tree energy-inefficient # Carry-merge stages = log 2 (32) 5 stages

36 Kogge-Stone Adder Carry-merge gates XOR PG Critical path = PG+5+XOR = 7 gate stages Generate,Propagate fanout of 2,3 Maximum interconnect spans 16b Energy inefficient

37 Sparse-tree Adder Architecture Generate every 4 th carry in parallel Side-path: 4-bit conditional sum generator 73% fewer carry-merge gates energy-efficient 37 C 27 C 23 C 19 C 15 C 11 C 7 C 3

38 Non-critical Sum Generator P i+3,g i+3 P i+2,g i+2 P i+1 G i+1 P i CM 1 0 CM CM CM CM XOR CM XOR XOR XOR XOR XOR Sum i,1 Sum i,0 38 2:1 Sum i+3 2:1 2:1 2:1 Sum i+2 Sum i+1 Sum i Carry Non-critical path: ripple carry chain Reduced area, energy consumption, leakage Generate conditional sums for each bit Sparse-tree carry selects appropriate sum

39 Adder Inputs 39 Adder Core Critical Path clk PG GG 1 clk2 GG 7 clk3 Single-rail dynamic sparse-tree path Sum 31_0 clk CM0 Latch GG 3 CM1 XOR GG 15 Static sum generator GG 27 Sum 31_1 C 27 Sum 31 Critical path: 7 gate stages same as KS Sparse-tree: single-rail dynamic Exploit non-criticality of sum generator Convert to static logic Semi-dynamic design

40 Sparse-tree Architecture Performance impact: (20% speedup) 33-50% reduced G/P fanouts 80% reduced wiring complexity 30% reduction in maximum interconnect Power impact: (56% reduction) 73% fewer carry-merge gates 50% reduction in average transistor size 40

41 Energy-delay Space 41 Worst-case Energy (pj) % 20% 130nm CMOS, 1.2V, 110 o C Dynamic Kogge-Stone 20 4GHz 0 Design Semi-dynamic Sparse-Tree Delay (ps) 20% speedup over Kogge-Stone 56% worst-case energy reduction Scales with activity factor

42 Semi-dynamic Design Average Energy ( (pj pj) % Dynamic Kogge-Stone Semi-dynamic Sparse-Tree Activity factor Static sum generators : low switching activity 71% lower average energy at 10% activity 42

43 So, How Do We Get There? Multi-Threaded, Multi-Core Multi Threaded MIPS Super Scalar Era of Thread & Processor Level Parallelism Speculative, OOO Era of Instruction Era of Special Level Pipelined Purpose HW Architecture Parallelism Significant Challenges Ahead Can only be solved with joint industry -university industry-university collaboration

44 Thank You for Your Attention Q&A Our publications can be found in: IEEE Intl. Solid-State State Circuits Conference, IEEE Journal of Solid-State State Circuits, Symposium on VLSI Circuits, Intl. Symposium on Low-power Design, Custom Integrated Circuits Conference, SOCC, etc.,

45 45 Backup

46 Optimized First-level Carry-merge CM 0 Conditional Carry for Cin=0 P i Cin=0 G i C#_0 i G i C#_0 G i P i Carry-merge stage reduces to inverter Conditional carry_0 = G i # 46

47 Optimized First-level Carry-merge CM 1 Conditional carry for Cin=1 Cin=1 P i P i C#_1 G i C#_1 G i G i P i A i B i P i G i C#_ P i C#_1 47 P i & G i correlated Conditional carry_1 = P i #

48 Optimized Sum Generator P i+3,g i+3 P i+2,g i+2 P i+1 G i+1 P i Optimized 1st-level carry-merge CM CM CM XOR CM XOR XOR XOR XOR XOR Sum i,1 Sum i,0 2:1 2:1 2:1 2:1 Carry Sum i+3 Sum i+2 Sum i+1 Sum i Optimized non-critical path: 4 stages 48