A Dual-Core Multi-Threaded Xeon Processor with 16MB L3 Cache

Transcription

1 A Dual-Core Multi-Threaded Xeon Processor with 16MB L3 Cache Stefan Rusu Intel Corporation Santa Clara, CA Intel and the Intel logo are registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. Other names and brands may be claimed as the property of others. All products, dates, and Copyright figures are 2006, preliminary Intel Corporation and are subject to change without any notice.. 1

2 Outline Processor Highlights 65nm Process Technology Block Diagram L3 Cache Overview Sleep and Shut-off Modes Long-Le Transistor Usage Clock and Power Distribution Package Details DFT/DFM Features Thermal sensors Frequency Shmoo Summary 2

3 Processor Highlights Core 1 1MB L2 1MB L2 Core 0 FSB TOP T A G Control Logic FSB BOT T A G 16MB L3 Dual core, four threads 1 MB unified L2 per core 16 MB unified L3 435 mm 2 die size B transistors 121 M transistors per core 3.4 GHz at 1.25 V and 150 W TDP 800 MT/s 3-load front-side bus interface Plugs in existing platforms Largest cache and transistor count for an x86 processor 3

4 65nm Process Technology M8 M7 M6 M5 1.2 nm gate oxide NiSi for low resistance Second generation strained silicon 8 Cu interconnect layers with low-k CDO dielectric M4 M3 M2 M1 4

5 Block Diagram 3-load System Bus External Front-Side Bus Interface Caching Front-Side Bus Controller Core 0 (1M L2) Core 1 (1M L2) 16MB L3 Cache Shared 16MB L3 cache Better efficiency - one core can use more than half of the total cache No need for coherency traffic between caches Support for Intel Virtualization Technology Hyper-Threading Technology Enhanced Intel SpeedStep Technology 5

6 L3 Cache Floorplan TAG (1 st 8K sets) TAG (2 nd 8K sets) Redundancy shift logic & horizontal clock spine 8M0 8M um 2 bit cell 0.75 Watts / MB average power Only 0.8% of all array blocks powered-up for each access 256 regular 64kB sub-arrays 32 redundancy 68kB sub-arrays Legend: Regular Sub-array (32 bits) Redundancy Sub-array (34 bits) Repeaters CLK Spine + Repeaters 6

7 L3 Sub-Array and Sleep Partitioning Word-line Driver Sense amp + write circuit M2, BL M3, WL Mid Logic Midlogic Bank3 Bank 2 Bank 0 Bank 1 blk7 blk6 blk5 blk4 blk0 blk1 blk22 blk33 Sleep Resolution Timer Reg SA: 128 cols Rdn SA: 136 cols PMOS-sleep NMOS-sleep 256 rows 7

8 Column Redundancy Features Data Array Two redundancy columns for each 290-bit chunk Repair up to two random defects in each cache line R ECC Data ECC Data 0 Tag Array One redundancy column for each 36-bit tag line Repair one random defect in each entry UR CR Upper tag ECC Lower tag State

9 L3 Cache Sleep and Shut-off Modes Active Mode Sleep Mode Shut-off Mode Sub-array Sub-array Sub-array Virtual VSS 1.1V Voltage Block Select Virtual VSS Sleep Bias Shut off 2x lower leakage X 250mV 2x lower leakage X X ~500mV 0V 0V 9

10 Leakage Shut-off Infrared Images 16MB SKU All 16MB in sleep mode 8MB SKU 8MB in sleep mode 8MB in shut-off mode Shut-off feature reduces the leakage of the 8MB disabled sub-arrays by about 3W 10

11 Leakage Mitigation: Long-Le Transistors Nominal Le All transistors can be either nominal or long-le Most library cells are available in both flavors Long-Le transistors are about 10% slower, but have 3x lower leakage All paths with timing slack use long-le transistors Long Le (Nom+10%) 11

12 Long-Le Transistors Usage Map Long-Le Usage (%) 100% 80% 60% 40% 20% 0% Cor 1 Control L3 Cache Core 0 12

13 Long-Le Transistors Summary Percentage of Long-Le device width excluding RAM arrays: Cores Uncore Nominal 46% Nominal 24% Long-Le 54% Long-Le 76% Moore s Law will continue to double transistors every 2 years New Trend To reduce sub-threshold leakage, most devices will be slower and only a handful of transistors will be fast 13

14 Clock Domains FSB TOP Core 1 1MB L2 T A G 16MB L3 System Clock (BCLK) 1MB L2 Core 0 T A G FSB BOT Legend: Core PLL Uncore I/O 14

15 Global Clock Skew Profile Worst-case global skew is 11ps More details on the clock distribution in paper

16 Voltage Domains FSB TOP Core 1 1MB L2 Control Logic T A G 16MB L3 1MB L2 Core 0 T A G FSB BOT Legend: Core PLL Uncore I/O 16

17 Voltage Profile Voltage Profile Cut Line 1.25V 1.10V Voltage 0V Cores Ctrl + Tag 16MB array 0.25V Virtual VSS Cache sleep function enables separate voltage knob 17

18 Power and Leakage Breakdown Total Power Breakdown Cores 74% Leakage Breakdown Cores 67% I/O 3% Ctrl 11% L3 Cache 12% I/O 2% Ctrl 9% L3 Cache 22% Leakage accounts for about 30% of the total power 18

19 Symmetric I/O Pre-driver Circuit Bidirectional Delay Control Din Mux R_1 Ron_1 R_2 Ron_2 R_3 Ron_3 Vtt Rodt 2 R_4 Ron_4 R_5 Ron_5 R_6 Ron_6 PAD 19

20 C4 Bump Map C4 bumps Perfectly uniform bump pitch over the entire die (including I/O buffers) to improve epoxy underfill 20

21 Package Details 12 layers organic substrate (53.3 mm/side) stacking Integrated heat spreader (38.5 mm/side) 604 total pins 366 signal I/Os System management components on package 21

22 Design for Test and Debug Features Die-level DFT/DFM Parallel structural core test with XOR Scan and observability registers (scan-out) Three TAP controllers (core0, core1, uncore) Within-die process monitors On-die clock shrink L3 cache DFT/DFM Built-in pattern generator (PBIST) Programmable weak-write test Low-yield analysis Stability test mode 32-entry cache line disable (Pellston) FSB DFT/DFM I/O loopback I/O test generator 22

23 Thermal Sensors Temperature Sensors Thermal Diode 23

24 Frequency Shmoo Core Voltage [V] Frequency [GHz] Target operating point 3.4GHz at 1.25V core voltage and 150W TDP envelope 24

25 Summary 65nm dual-core, four-thread Xeon Processor with on-die 16MB L3 cache Shared L3 cache best fit for server processors Virtualization and Hyper-Threading Technology Leakage reduction circuit techniques Massive Long-Le usage N and P sleep transistors in L3 cache L3 leakage shut-off mode saves power in lower cache size SKUs Multiple voltage and clock domains to reduce active power and leakage 25