Dynamic Verification of Low Power Design Intent. Suleiman Abu Kharmeh and François Cerisier Test and Verification Solutions

Transcription

1 Dynamic Verification of Low Power Design Intent Suleiman Abu Kharmeh and François Cerisier Test and Verification Solutions

2 Introduction Customer driven project Verification of Subsystem which includes: Complex Multimedia IP Functional & Low Power Control Simplified Arch DUT : Subsystem Media IP A B Ctrl Reg FSM

3 Low Power Specifications Top level Power Domains SubSys: On / Off Ctrl: almost always ON (except when SubSys is OFF) IP + block A: when needed Block B: when needed Simplified Arch DUT : Subsystem Media IP A B Ctrl Reg FSM

4 Lowe Power Intent Complexity Hierarchical Low Power Design Other SoC switched domains 12 different power domains Voltage aware supplies: A maximum of 6 different possible voltages Including undetermined (X) and OFF state 6^12=2176 million possible states Exponential complexity increase with respect to number of power domains

5 Project Goals RTL Verification Is the functional behavior meets specifications? Low Power Verification Is the power intent conforms to specifications? Is the functional behavior still meets specification once low power aspects are considererd? Power structure should not break functional behavior Active blocks should work when selected blocks are OFF

6 Low Power Techniques Power Switch switch OFF unnecessary blocks Isolation cells between switchable domains Reduced Power / Multivoltage Designs Implies Level Shifters between power domains Shifters could be bidirectional DVFS: Dynamic Voltage and Frequency Scaling Reduce/Increase voltage and frequency depending on processing demands

7 Low Power Verification Behavioral Intent RTL Power Intent UPF / CPF description Power Domains Isolations / Level Shifters Power States Static Checks Are power domains well isolated? RTL UPF Power aware dynamic simulation Sim Vcd / fsdb Reports logs

8 Static Low Power Verification Static Checks Multi-voltage rules checking Consistency checks Architectural checks, power structure violations Functional Checks Isolation cells Power Switches

9 Low Power Control FSM Behavioral functional verification Goals: verify the correct behavior of the power control Is the power switch sequence meets specifications? Are there any violations due to the power switching? Is the design able of reaching all the intended power states? Methodologies Stimulus / tests to exercise the power scenarios Assertions to check Transition violations (Xs?) The expected final state

10 Power States Table (PST) Develop tests to cover: Supply_A Power domains, power supplies states Example: OFF 0V 0.5V 0.8V 1.1V Transitions from a power state to the next one off off Supply_B Valid states Transition path State violation Invalid states may be reached during transitions!

11 Use Cases & Block interactions/isolation Structural low power design: Each functional block has an associated power domain Use Cases: Register access while other domains are OFF Block A should work while Domian B is OFF (correct behaviour of isolation/retention strategies) test: Switch Domain B OFF and then perform functional checks on Block A. Simplified Arch DUT : Subsystem Media IP A B Ctrl Reg FSM

12 When are we done? Verification Plan: Use cases & functional coverage Power Control FSM coverage Could be functionally verified PST coverage database Have we covered all intended states and transitions? Design of coverage metrics: > 2x10^9 possible power states? Exahstive verification of all possible states and transitions is not feasible

13 Future needs / thoughts Careful consideration to the design of the PSTs Include all essential target states Could perform automated test generation to cover all targeted power states PST coverage on targeted states (vs. all states) Assertions crossing the RTL/UPF boundary Ways to deal with intermediate states: Could introduce bugs in functional behaviour

14 Conclusion Power Intent verification is as essential as functional verification of RTL UPF specifications could be used in dynamic test based functional verification Careful consideration made to the selection of power scenarios EDA use: Power static checks Power aware simulator

15 Room for improvement Assertions crossing the behavioral/power intent boundary Automatic identification of interesting cases out of > 2x10^9 power states

16 Thank you Questions?