Verification of Power Management Protocols through Abstract Functional Modeling

Transcription

1 Verification of Power Management Protocols through Abstract Functional Modeling G. Kamhi, T. Levy, Niranjan M, M. Mhameed, H. Rawlani, R. B. Rajput, E. Singerman, V. Vedula, Y. Zbar

2 Motivation Microprocessor design methodologies becoming similar to those in SoC Use of multi/many cores Complex uncore to integrate the cores Aggressive system-level tradeoffs for power/performance result in significant challenges to validation High-level validation of system-level protocols (such as power management) using ESL modeling ESL models not reused for RTL validation Behavioral synthesis of protocols not viable Protocol validation dependent on RTL arrival and slow simulation speed Need a methodology to reuse the ESL model for RTL validation 2

3 Objectives Accelerate Arch/uArch definition closure Provide clean uarch spec early before RTL design using an Abstract Functional Model (AFM) Prevent RTL bugs through better specification Use AFM as an executable reference for implementation to reduce bugs that get in RTL due to ambiguity Accelerate validation collateral generation Pull in pre- and post-si validation collateral generation time (and quality) by using the AFM 3

4 Outline Power Management Basics Abstract Functional Modeling (AFM) RTL Validation using AFM Limitations and Future work Requirements for the EDA industry 4

5 Power Management Basics While running real applications, core(s) have many idle periods C-states (normal, inactive) have been introduced to vary power P-States used for varying frequency and Voltage OS/HW initiated P-State transitions used to optimize power/performance Changing frequency requires to stop and re-start the core (relock PLL to new ratio) Changing voltage done on-the-fly 5

6 Key Players in the Power Management Protocol Memory Controller (MC) Interrupt Controller (IC) Channel 4 IO Controller Channel 3 Channel 1 Power Core Slices Channel 2 Controller (PC) 6

7 Model Architecture Set of communicating FSMs representing the various agents Agent is a h/w unit responsible for power management Agents communicate through channels An action is a state transition as defined by Guard: Check if an action is enabled (read local variables) Result: Perform the action (write local variables) Values written to shared variables converted to messages on the various channels Agents have input/output handlers for each type of message 7

8 Implementation Developed in SystemC Industry (SoC) standard Essentially, some C++ template classes Adds concurrency, communication Event-based simulation kernel Developed and run in standard off the shelf C++ compilers/ide Integrated with an industry standard testbench 8

9 Key Details of the Model Number of Protocol Agents Number of FSMs Number of FSM states Number of FSM transitions Size of model (# of lines) Size of test bench (# of lines)

10 Validation Environment Test Env A M AFM Test plan S D S D Test Stimulus Driver M A Monitor and Debug Using Checkers and Debugging Aids Coverage Analysis 10

11 Execution Trace Collaterals Sequence of FSMs state transformations Messages being sent/received on the channel Coverage viewer for analysis of test results Specialized Debug Aids Dynamic Execution View Messages passed between various agents along timelines Static Model View Visualization of FSMs of each Agent Capture simulation for rerun 11

12 Coverage Coverage space is FSM centric Aggregated results are presented in an internal coverage viewer Total Tests Paths (as defined as an FSM transition pair) Tests that uniquely cover more than 20 paths Paths covered by more than 1000 tests Paths covered by more than tests

13 Debug Viewer 13

14 Deadlock Scenario Core0 IC PC Core1 IPI to Core1 IPI to Core1 Wake Up Core1 Not Enough Power Sleeping Waiting for Ack From Core1 Deadlock Initiates P-State Waiting for IC to Finish In-Flight Interrupts 14

15 RTL Validation using AFM 15

16 RTL Validation using AFM RTL Validation Environment AFM Testbench AFM Functional Checkers Stimuli RTL Tests RTL Functional Checkers AFM Ref Model Assertions Lock-step RTL-to-AFM Mapping Logic RTL DUT AFM-RTL Comparison Functional Checkers 16

17 Validation using Co-Simulation Both the models are set to run in parallel RTL events drive AFM injections via the test-bench interface Interesting AFM actions initialized to HOLD at the beginning of the co-simulation AFM HOLDs at lock-stepping point until RTL reaches equivalent state Action guard conditions are still computed based on the states/variables/messages in AFM RTL activity just controls forward progress (HOLD/GO) for actions Comparison checkers flag for mis-matches in simulation 17

18 ROI Re-use of AFM collaterals for RTL Validation Functional Checkers Checkers and assertions from AFM Functional Coverage Coverage analysis for RTL tests Specialized debug-aid Debug viewer for RTL Enables early development of RTL validation collaterals 18

19 Limitations and Future Work Difficult to model latencies accurately Lacks a good memory model makes it harder for RTL validation Existing approach requires the close involvement of architects Plan to use formal techniques/abv for validating the AFM Use AFM for post-silicon validation 19

20 Requirements for EDA Industry Formal analysis engines for SystemC Test generation tools Debug aids Faster co-simulation environment Abstract FEV: Use AFM as a golden model for equivalence checking with RTL 20

21 Summary Power management verification is a significant gap Challenges current methodology/tools Initiated a direction based on abstract executable models Created an abstract model with rich content and validation environment Demonstrated its effectiveness by catching fatal bugs in the design Successfully integrated with RTL for validation using co-simulation 21

22 Thank you