New Advancements in CPF 2.0 and the Path to Interoperability

Transcription

1 New Advancements in CPF 2.0 and the Path to Interoperability Qi Wang Chair of Format Working Group Vice Chair of Low Power Coalition October 2011 Innovation Through Collaboration

2 Agenda 2011 Overview CPF 2.0 Improvements Interoperability with IEEE 1801 Future Work Innovation Through Collaboration

3 Format WG Overview Active Members Nick English Si2 Susan Carver Si2 Anmol Mathur Calypto Prasad Subbarao LSI Steve Urish IBM Qi Wang Cadence Jon Worthington - Magma Weekly Meeting 9:00am 10:00 am PDT Every Friday Contact lpc_format@si2.org Innovation Through Collaboration

4 Format WG 2011 Highlights CPF 2.0 Released in March 2011 CPF 2.0 Tutorial Delivered the Webinar in May 2011 Open Low Power Methodology Contributed to IEEE in June 2011 Paper on Power Formats Submitted to IEEE Design & Test Journal in August 2011 Interoperability Guide Update Approved by LPC in October Innovation Through Collaboration

5 CPF 2.0 Highlights Macro modeling improvements IO PADs: improve usability Low Power Mixed-signal IP Voltage Regulator, Analog ports New low power IPs Power and ground level shifter, By-pass level shifter Clamp cell for isolation Isolation cell without primary pins multi-stage level shifters Simulation enhancements Misc. New command to control low power simulation behavior initial statement re-evaluation after power up level shifter requirement threshold specify inverted equivalent control pins specify different corner libraries for power estimation global cell (to replace always-on cell)

6 Voltage Regulator Example 2.5V input HAVDD C1 C2 1.1V input AVDD AVSS VBB variable output 1.1V, 1.2V, 1.3V simulation model may contain the output voltage behavior description but the CPF may not specify how the output voltage is controlled set_macro_mode regulator create_power_domain name PDVIN update_power_domain name PDVIN primary_power_net HAVDD primary_ground_net AVSS create_power_domain name PDVOUT -default base_domains {PDVIN} power_source update_power_domain name PDVOUT pmos_bias_net VBB create_power_domain name PDREF boundary_ports { C1 C2} update_power_domain name PDREF primary_power_net AVDD primary_ground_net AVSS create_nominal_condition name LDO_range voltage 1.1 pmos_bias_voltage 1.1:1.3 create_nominal_condition name HVDD voltage 2.45:2.55 voltage 0.0 create_nominal_condition name REF voltage 1.1 ground_voltage 0.0 create_power_mode name PM default domain_conditions \ { PDREF@REF PDVIN@HVDD PDVOUT@LDO_range } set_power_source_reference_pin AVDD domain PDVOUT voltage_range 1.1:1.1 end_macro_model regulator

7 Mixed-Signal IP Special requirements for analog ports of a mixed signal IP Must be connected to the analog ports of other IPs Does not require (digital) isolation and level shifter inserted Extend to macro model by introducing the new command set_analog_ports Semantics: The specified analog ports must be connected to ports that were declared as analog ports in either a macro or pad. Analog ports can be associated with a power domain of a macro. The implementation tools should not consider nets where the driver or receiver is an analog port for isolation or level shifter insertion. The verification tools should report an error if any isolation or level shifter logic is found on connections between ports specified with the set_analog_ports command.

8 New Low Power IPs By-pass level shifter A level shifter can be switched between level shifting path and normal buffer path define_level_shifter_cell -cells cell_list [ -bypass_enable expression ] create_level_shifter_rule [ -bypass_condition expression ] Specify the input and output PG connection Useful if the level shifter has fanouts in different domains but all have the same voltage or the level shifter is put in 3 rd domain so need a different input PG connection from the default create_level_shifter_rule [ -input_domain domain] [-output_domain domain]

9 New Low Power IPs Clamp Cell A simple NMOS/PMOS type of transistor to clamp a signal to 0/1 define_isolation_cell -cells cell_list [-library_set library_set] [-always_on_pins pin_list] [-power_switchable LEF_power_pin] [-ground_switchable LEF_ground_pin] [-power LEF_power_pin] [-ground LEF_ground_pin] [-valid_location { from to on off any}] { -enable pin [-clamp {high low}] -no_enable {high low hold} } [-non_dedicated] create_isolation_rule -name string [-isolation_condition expression -no_condition] {-pins pin_list -from power_domain_list -to power_domain_list}... [-exclude pin_list] [-isolation_target {from to}] [-isolation_output { low high hold tristate clamp_high clamp_low} [-secondary_domain power_domain] off on

10 New Verification Features Added Capability to Specify Simulator Action when Power Domain is Switched off or Restored To allow users to specify the immediate action to be taken when the power is switched off in power domains or restored to power domains New command set_sim_control Added Capability to Specify a CPF Model for a Testbench New option -testbench added to the set_design command. Added Control over Signal Values in a Power Off Domain Mainly targeted for emulation To control the signal values of elements in a power domain when this domain is being switched off New option -power_down_states option was added to the create_power_domain command

11 set_sim_control set_sim_control [-targets target_list [-exclude target_list]] {-action power_up_replay [-controlling_domain domain ] -action disable_corruption -type { real wreal integer reg module instance} -action {disable_isolation disable_retention} } [-domains domain_list -instances instance_list] [-modules module_list -lib_cells lib_cell_list] to disable the default corruption semantics on selected RTL objects to control the initial statement replay at power up to disable default inferencing of isolation and state retention in RTL and the corresponding simulation semantics

12 Status Review Path to Interoperability with IEEE In 2010, WG released the Interoperability Guide V1.0 Focusing on existing standard The proactive push by LPC for better interoperability New CPF 2.0 enhancements targeted for improved interoperability OpenLPM contribution to IEEE Interoperability Guide V2.0 Innovation Through Collaboration

13 Power domain CPF 2.0 New Features Targeted for Better Interoperability with IEEE 1801 Support pg_type Power mode more flexible mode specification functional model definition (in addition to power modes) Hierarchical flow Rules allow virtual output/inout ports forced isolation and shifter insertion state retention rule enhancements Simulation Better documentation of simulation semantics Flexibility to enable/disable power aware simulation semantics Innovation Through Collaboration

14 New Option Example Interoperability Driven Extensions create_isolation_rule... [-force] create_level_shifter_rule... [-force] Semantics When -force is specified, isolation or level shifter logic shall be inserted without checking the situations on CPF 1.1 LRM page 72 and 75. Implementation tools should be able to perform optimization to avoid redundant isolation or level shifter logic to be inserted. Innovation Through Collaboration

15 What is OpenLPM? A converged power methodology to facilitate complete interoperability between Si2 CPF and IEEE 1801 Emphasize 1801 supply set-based over UPF 1.0 P/G net-based methodology Deprecate old and incompatible UPF 1.0 constructs/methodologies Extend 1801 to include commonly used CPF features Hierarchical constructs: power design & macro model Advanced power domain concepts: disjoint domain, domain of pins Misc: Equivalent control pins, technology CPF

16 Industry Support of OpenLPM At Qualcomm, we have been using CPF and found that formal hierarchical design flow support, with both bottom-up and top-down capability, are critical to enable complex advanced low power designs, says Dr. Karim Arabi, Senior Director, Engineering, at Qualcomm. We appreciate Si2 for facilitating a converged power intent methodology by contributing these key aspects of CPF to It will enable an equivalent and consistent methodology in the 1801 format. As evidenced by the success of our OMAP applications processor platform, we believe that low power technology is critical to enabling the mobile market. As a result, we ve always advocated for a single industry standard for low-power design and were one of the originators of the unified power format (UPF) now IEEE We support the contribution of the unique CPF constructs that will facilitate the evolution of IEEE 1801 to improve interoperability and pave the way for future format convergence. Texas Instruments: David Peterman, Manager, EDA strategy, Wireless Business Unit

17 Interoperability Guide V2.0 Approved by LPC in October, 2011 Working with IEEE to obtain the copyright license before publication Reduced non-interoperable constructs from 50 to 36

18 Future Work Participate in IEEE 1801 WG to drive the interoperability Next CPF release (CPF 2.1) New features requested by LPC members Potential extensions to enable system level power intent specification Additional features to further improve the interoperability