DEVELOPMENT AND RESEARCH OF OPEN-LOOP MODELS THE SUBSYSTEM "PROCESSOR-MEMORY" OF MULTIPROCESSOR SYSTEMS ARCHITECTURES UMA, NUMA AND SUMA

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1 DEVELOPMENT AND RESEARCH OF OPEN-LOOP MODELS THE SUBSYSTEM "PROCESSOR-MEMORY" OF MULTIPROCESSOR SYSTEMS ARCHITECTURES UMA, NUMA AND SUMA A. I. Martyshkn Penza State Technologcal Unversty, Baydukov Proyezd / Gagarn Street, 1a/11, Penza, Penza regon, Russa E-Mal: dmtry.shkurkn@gmal.com ABSTRACT The artcles explore a problem of the synthess and analyze models of subsystem "processor-memory" multprocessor systems. The prme object s to study the archtecture of the subsystem "processor-memory" of modern hgh-performance computng systems, calculaton and comparson of the performance, as well as a concluson on the effect of conflct over access to shared resources on the overall performance of the whole system. The objects of study of ths work are the subsystem "processor-memory" multprocessor computer systems, exstng varetes of archtectural constructon of ths subsystem. Durng researches the comparatve analyss of systems wth archtecture UMA, NUMA and SUMA was carred out. Ther merts and demerts were revealed. In the nference the approprate conclusons on operaton are drawn. The consdered models allow makng an assessment of characterstcs of the multprocessor systems wthout creaton of a real prototype. At the expense of t economc effect as the assessment of characterstcs of the desgned systems and a choce of the most optmal varants can be carred out wthout creaton of real system s reached. Keywords: multprocessor system, subsystem "processor-memory", archtecture, mathematcal model, performance, queung system. 1. INTRODUCTION Increased productvty computng systems s drectly related to the ncreasng of speed and storage capacty. Although the rapd growth of memory bandwdth, whch s observed n recent years, the gap "CPU-Memory" s not reduced, but on the contrary s ncreasng. To research and the analyss of computng systems even more often apply elements of the queung theory, namely queung systems and networks (QS and NS). Any unt, any system module t s possble to present queung systems n the form, and set of devces of the computng system s represented a network of mass servce and qute easly gves n to research n case of the mnmum fnancal expenses t sn't requred to buld real system, there s enough ts model [1-3]. 2. GOAL SETTING Ths artcle s research character. To solve ths problem there were analyzed the lterature descrbng research n ths subject area to search for unsolved problems. Lterary sources have been analyzed [4-11]. However, a number of ssues related to the study of the subsystem "processor-memory" dd not adequately reflect. Open queung networks farly well studed and descrbed n detal n the sources [1-3, 12-14]. We present part of expressons and formulas are used n the generated software package n ths research, the non-necessty for the study of the developed models. 3. THE CALCULATION OF CHARACTERISTICS OF QUEUING NETWORK If the network settngs are set, you can defne the followng characterstcs of each QS and the network as a whole: the average length of the queue of applcatons n the -th QS - l and n the network - L; the average number of applcatons resdng n the -th QS - m and network - M; the average watng tme of servce applcatons -th QS - and network - W; the average resdence tme applcatons n the -th QS u and the network - U [1]. The average watng tme n the queue for the applcaton of sngle-channel queung equal to the quotent l of the average queue length on the ntensty of the nput at the -th QS flow [1] l. 1 For mult-channel QS [1] k l p0. 2 k! k 1 k The average tme of the applcaton n the system s determned by ts average delay n queue and the tme of servce n the -th QS. For sngle-channel queung [1] u. 1 For mult-channel QS [1] k u p. 2 0 k! k 1 k Based on the determned characterstcs of ndvdual queung network characterstcs n general. The average number of requests watng for servce n the network (that s, the average number of applcatons on the network lnes) n l 1 L

2 The average number of applcatons resdng on the network n m 1 M. Because each applcaton may receve the servce n the -th QS n the mean tme, the watng tme servce and stay n her system wll ncrease n tme. The average watng tme applcatons n the network lnes n W, 1 and the resdence tme n U. 1 u Development of a model of the subsystem "processor-memory" UMA s archtecture [4, 8, 9]. The structure of the UMA archtecture (Unfed Memory Access) and the count of transmssons s presented n Fgure-1(a) and (b). Fgure-1. The structure (a) and the transmsson graph (b) of UMA-system. The fgure shows: CPU/CACHE - n processng nodes; OPm m memory modules; S0 - source applcatons, representng the n processng nodes; S1 - m memory modules n the form of a mult-channel devce-servcng. It s consdered that applcatons create the smplest flows of requests, and holdng tmes submt to the exponental law. Ths dstrbuton wll allow recevng results of certanly worse real values that, n turn, wll allow makng an assessment of the receved results on top. It s consdered that memory has unform address space, and controllers of memory contan n the composton buffer regsters for data storage, wrtten n memory or read from memory, havng the volume suffcent n order that requests were not refused n servce. 4. AN EXAMPLE AND SIMULATION RESULTS To study ths archtecture we wll take the Intel Pentum IV. The volume of cache L2 of the processor seres Pentum MB. Intel Pentum seres have a bus frequency of 200 MHz (the quantum duraton T=5 ns) [15, 16], denoted by based technology Quad Pumped Bus as 800 MHz. Ths bus per cycle can transmt 4 ready to transfer 64-bt words. But f you are ready to transfer only one word and t wll be transmtted for 1 clock cycle. CPU clock frequency s taken to be Intel Pentum MHz. It s expected that the treatment wll be made n the memory of every clock cycle. The data cache memory, accordng to statstcs gets at least 99% of the requests. Therefore, based on the processor speed of 2, 8 GHz, we fnd that the frequency of queres n memory wll be 2,8 1% 0,028 query/ns. At the study of the CPU performance mpact on the operaton of the subsystem "processor-memory" dscussed Intel Pentum processor wth a clock frequency 2,8-3,8 GHz [17-19]. The calculatons use DDR memory wth a frequency of 200 MHz. Because DDR bus standard labeled as 400 MHz. Ths means that can transmt two 64- bt ready word n one cycle length of 5 ns memory bus [15]. Memory Tmngs CL-RCD-RP accordng to the chp are 15 ns each (3-3-3). The best case occurs when there s an appeal to open-lne memory module. It s necessary to submt only CAS sgnal, and the memory module to produce data at an nterval CL (15 ns). Statstcally, ths stuaton occurs n 55% of cases [20]. The worst case s when ths s n a dfferent row. At the same tme sgnals are RAS (actvaton of the lne) and after a tme RCD-CAS (column actvaton). Thus, the memory module wll requre a tme equal to CL + RCD (30 ns), to prepare the data. Ths embodment s obtaned wth a probablty of 40% [21]. Worst case, when the data s on an nactve page. In ths case, the current page should be closed. The preparaton of the data memory module requres a tme equal to CL + RCD + RPT (45 ns). Ths varant accounts for 5% of the cases [22]. We defne the mean tme OP module VOP 0, , , ,5 ns. Calculate how much you want to bus tme for the transmsson controller 32-bt address. Bt bus 64 bt. That s a 32-bt address wll be gven for 1 cycle ns. For a 64-bt word from the memory to the processor through the controller requres one bus cycle "memory controller" and 1 bus cycle "controller-processor" ns. By summng the values obtaned, we obtan the average tme to access memory: 22, = 37,5 ns. Thus, obtaned durng memory accesses of the processor. Analyss of the mpact of effcency of the cache on the real capacty of the subsystem "processor-memory". Intal data: the number of servce channels (OP unts) n the NS K = 12; Load the number of sources (CPUs) CPU = 4; Queung tme one channel (the OP module) = 37, 5 ns [23, 24]. The ntensty of the flow of requests n the smulaton was changed as follows: the probablty of a cache mss, % (CPU clock frequency). Range probablty of cache 13527

3 msses - 0, 5-3%. The smulaton results are shown n Fgure- 2. Fgure-2. The dependence of load factor (1), and the length of the queue n front of the devce (2) the probablty of a cache mss. When ht n the cache s 99 % of the requests the average queue length l s almost equal to 0, the response tme conssts of memory access tme to the memory u = 37,507. When the flow of requests 0,070 request/ns (sze of cache-msses s 2, 5 %) queue length l=3,974 applcatons, the watng tme of requests n the queue ( =14,098 ns) and a stay applcaton to the QS (response tme memory) u=51,598 ns),.e. ncreased by 28 % [25]. When the cache-mss s 3 % the system s overloaded ( =1,05), as t reduces the throughput of the subsystem "processor-memory". By ncreasng the effectveness of the cache n 2 tmes (the number of cache hts s 99, 5 %) n queue are no requests, watng tme n the queue s 0. Analyss of the mpact of the number of processor nodes on the throughput of the subsystem "processor-memory". Intal data: the number of servce channels (OP unts) n the NS K = 8; number of load sources (CPUs) CPU = 2-8; servce tme applcatons wth one channel (the OP module) = 37, 5 ns; the ntensty of the flow of requests = 0,028 query/ns. The smulaton results are shown n Fgure-3. Fgure-3. The dependence of the watng tme n the queue (1) and response tme memory (2) of the number of processor nodes. When CPU =2-5 n the studed system queue length l<1 (from 0,001 to 0,394 applcatons), the watng tme n queue s from 0,01 to 2,817 ns. When CPU =6-7 number of entres n the queue reaches 8,52 applcatons, the watng tme n the queue ncreases to 43,468 ns, response tme, memory s 80,968, whch s 2,2 tmes larger than the value when CPU =2. When CPUs =8 n the system experencng the overload =1,05. Analyss of the mpact of the number of memory real capacty act-the capacty of the subsystem "processormemory". Intal data: the number of servce channels (OP unts) n the NS K = 4-10; sources of loads (CPUs) M= 4; the servce tme of requests wth a sngle channel (the OP module) =37,5 ns; the ntensty of the flow of requests =0,028 query/ns. Results are shown n Fgure-4. Fgure-4. Dependence of average number of busy channels (1), queue length n front of the devce (2), watng tme n the queue (3) and response tme memory (4) by the number of memory modules. As seen from the fgure, the average number of occuped channels n the system for a gven task flow ntensty of 4, 2,.e. no pre-exceeds 5. The average number of customers n the system at K> 5 and not more than 5. Thus, the optmal number of memory modules 6. It s confrmed by other characterstcs, as for K>6 system characterstcs change slghtly and tend to 0. When K = 10, the number of requests n the queue l close to 0, as well as the watng tme n the queue. The, response tme, memory u conssts of the memory access tme. Analyss of nfluence of tme of storage access for real throughput of a subsystem "processor memory". As basc data for tme of storage access mean value s taken, n real system t can be more than ths value. Therefore, t s mportant to analyze model wth bgger value of tme of a memory access wth a research objectve of lmt values. Intal data: the number of servce channels (OP unts) n the NS K = 8; Load the number of sources (CPUs) CPU = 4; servce tme applcatons wth one channel (the module OP) = 37,5-40 ns; the ntensty of the flow of requests = 0,028 query/ns. Results of the study are shown n Fgure

4 Fgure-5. Dependence of the queue length before the devce (1), the watng tme n the queue (2) and the response tme of the memory (3) from the memory access tme. The fgure shows that the crtcal state of the system s observed wth consderable delay memory response (up to 77, 5 ns). Ths channel load factor s 1,085 - overload occurs. Wth a slght ncrease n the tme dos dumb to the memory (up to 45,5 ns) memory response tme s ncreased by 10 ns compared wth the value of the orgnal system, the number of requests n the queue s less than 0,319 applcatons. These values are not crtcal, so lttle effect on system performance. Development of a model of the subsystem "processormemory" archtecture NUMA. The structure of NUMA (Non Unfed Memory Access) and the count of transmssons s presented n Fgure 6, a and b. Determnaton of ntal data for NUMA archtecture. Ths archtecture s also seen on the example of a famly of Intel Pentum IV 500. L2 cache processors seres Pentum MB. Therefore, the frequency of requests n OP remans unchanged, namely =0,028 query/ns. When you study the effects of CPU performance on the subsystem "processormemory" dscusses the Intel Pentum wth a clock frequency of 2,8-3,8 GHz. In the calculatons, we use the DDR memory modules wth a frequency of 200 MHz. On the module's OP far the calculatons made above. V OP = 22, 5 (ns) Snce n the model ths archtecture the bus "controller-processor" s a separate element, then the average tme of memory access wll consst of the average tme-on operaton OP and 1 quantum bus "memory controller" to transfer words from memory. Receved: 22, 5+5 =27,5 ns. If the processor access ts local memory module, the average tme of memory access wll amount to 27, 5 ns. When handlng the CPU module to the local memory of another processor node would requre an addtonal 2 cycles of the bus "controller-processor": the transmsson controller 32- bt address and to transfer 64-bt words from the memory va the controller to the processor. 5 2=10 ns. Thus, the bus delay wll be 10 ns. We also beleve that 90 % of requests of processor nodes flow to ts local memory module, and 10 % of appeals to the local memory module of another processor node. Analyss of the mpact of effcency of the cache on the real capacty of the subsystem "processor-memory". Intal data: the number of OP unts n the NS K = 4; Load the number of sources (CPUs) CPU = 4; servce tme applcatons wth one channel (the module OP) = 27,5 ns; latency bus - 10 ns. The ntensty of the flow of requests n the smulaton was changed as follows: the probablty of a cache mss,% (CPU clock frequency). Range probablty of cache msses - 0, 5-3%. Results of the study are shown n Fgure-7. Fgure-6. The structure (a) and the transmsson graph (b) of the NUMA-system. Here: CPU/CACHE - n processng nodes; Bus - common bus; LPm - m unts of local shared memory; S 0 - source applcatons, representng a 4-weed assembly processes; S 1 - tre; S 2-S 5-4 local shared memory module. Fgure-7. Dependence of load factor (1), and the length of the queue n front of the devce (2) the probablty of a cache mss. When ht n the cache 99 % of the requests (the flow of applcatons to the memory of the processor request 0,028 query /ns): the average number of customers n the system m = 13,517 applcatons; the average queue length l = 10,

5 applcatons; latency applcatons n the queue ω= 92,191 ns; the resdence tme of applcaton to the QS (a memory response tme) = 120,691 ns. When the flow of applcatons query 0,042 query/ns (the value of a cache mss s 1, 5%) observed n the system overload - = 1,155. By ncreasng the effcency of the cache memory 2 tmes (the number of cache hts s 99, 5%) Response tme memory s 45,774 ns, whch s compared wth the orgnal one s better about 38%. At the same queue length l <1. Analyss of the mpact of the number of processor unts and memory modules on the real capacty of the subsystem "processor-memory". Intal data: the number of OP unts n the NS K = 4-7; number of load sources (CPU) CPU = 4-7; servce tme applcatons wth one channel (the module OP) = 27, 5 ns; latency bus 10 ns; the ntensty of the flow of requests = 0,028 query/ns. Results of the study are shown n Fgure-8. Fgure-8. The dependence of the watng tme n the queue (1) and the memory response tme (2) of the number of processor unts and memory modules. Despte dentcal tme of storage access, the queue length, number of requests n system, wat tme n queues and tme of the response of memory ncrease n case of ncrease n number of processng nodes and modules of memory. It occurs n connecton wth ncrease n probablty of the appeal of several processng nodes to the remote module of memory. In general, an ncrease n performance slghtly (the memory response tme ncreases by about 1 ns). Such as 90% of storage accesses make processng node to "the" local module. Analyss of nfluence of tme of storage access for real throughput of a subsystem "processor memory". As basc data for tme of storage access mean value s taken, n real system t can be more than ths value. Therefore, t s mportant to analyze model wth bgger value of tme of a memory access wth a research objectve of lmt values. Intal data: the number of OP modules n the NS K = 4; load the number of sources (CPUs) CPU = 4; servce tme applcatons wth one channel (the module OP) = 27, 5-37,5 ns; latency bus 10 ns; the ntensty of the flow of requests = 0,028 query/ns. Results of the study are shown n Fgure-9. Fgure-9. The dependence of the queue length before the devce (1), the watng tme n the queue (2) and the response tme of the memory (3) from the memory access tme. Wth a sgnfcant ncrease n the memory access tme (up to 29, 5-31, 5 ns) response tme, memory ncreases n 1,4-2,2 tmes, respectvely. Wth a further ncrease n the value of access to the memory at 35,5 ns delay before the response of memory reaches 5917,793 ns, whch s 49 tmes larger than the orgnal value. System overload occurs at 37, 5 ns memory access. Development of the "processor-memory" model subsystem SUMA s archtecture. The proposed archtecture AMD SUMA combnes the advantages of UMA and NUMA allowng you to create a flexble and hghly scalable computng systems (Fgure 10, a). Here, each CPU has ts own memory controller and hgh bandwdth nterprocessor bus Hyper Transport (HT) allows you to get rd of the huge delays when accessng memory of another CPU. AMD has fnally named ther scheme s not NUMA, but SUMA - Slghtly Unform Memory Archtecture, whch s "almost unform" memory archtecture. Bass of SUMA - seral bus Hyper Transport. The server versons of AMD processors can be ntegrated wth up to three ndependent records HT, operatng at frequences up to 1 GHz (2 GHz DDR, takng nto account the data transfer mode) and a wdth of 16 bts (4 GB/s) n each drecton. Part HT-lnks used for pont-to-pont connectons between the CPU, the part s actvated to connect perpheral devces. Each CPU ntegrated controller "local" OP. Memory access "foregn" place the CPU by HT bus, and done ths "redrecton" of requests s absolutely transparent for the actual computng core CPU - t provdes a bult-n swtch (Crossbar), runnng at full CPU frequency. It provdes the "automatc" route passng through the CPU messages from perpherals and other CPUs, ncludng the servce of "foregn" to the OP requests. Hstorcally HT was developed by AMD as the processor bus of new generaton especally for archtecture 13530

6 of AMD64. Ths bus s urged to provde throughput not smaller, than at OP, and the mnmum tme delays on data transfer and messages. Data s transferred by the scheme DDR - there s an addtonal lne for the clock sgnal, data s synchronzed at the begnnng and end of each clock pulse (that s, data s transmtted per clock cycle twce). The base clock frequency HT bus MHz (.e., the frequency of data transmsson MHz). All subsequent clock speeds are defned as multples of a gven MHz, 600 MHz, 800 MHz (HT ), 1000MHz (last revson HT 1.x and HT 2.0), 1200 and 1400 MHz (HT 2.0). Mathematcal model of archtecture SUMA and the transmsson graph shown n Fgure-10 (b), (c). Fgure-10. A four-computer system wth an archtecture based on SUMA (a), model (b) Transmsson Count (c), a varant of a four computer system archtecture SUMA (d). Here: CPU/CACHE - n processng nodes; OP - memory modules; HT - Hyper Transport channels; S 0 - processor nodes; S 1-S 4 - Hyper Transport bus; S 5-S 8 - memory modules. Bus HT specfcally optmzed for ths mode of operaton and provdes extremely low latency treatment n "another" memory, and hgh (up to 4 GB/s) bandwdth when accessng memory adjacent modules. The bus s full duplex,.e. can smultaneously transmt data at ths rate n the "both sdes" (8 GB/s total). The memory model s obtaned an nhomogeneous, but the dfferences n "ther" speed and "foregn" stes OP obtaned relatvely small. Such an organzaton of the memory subsystem has one mportant fact wth respect to each of the specfed CPU OP can be not only "ther" (belongng to the memory controller of the CPU) and "foregn" (owned by a neghborng controller). In the case that access to the OP wth TSP1, located n the address space TSP3 controller, electrcal sgnals need to pass n two serally connected bus HT (CPU1> CPU2> CPU3 or CPU1> CPU4> CPU3). If made not 4 I/O channel, but 2 the two connecton HT freed can be joned wth each other. The resultng structure s shown n Fgure-10(d). There s the possblty of buldng eght-processor systems of ths archtecture. Thus at the extreme CPU 4 on HT gven the same bus for nput/output, and n the central all three are nvolved n an nterprocessor communcatons. However, t should be noted that, presumably, n ths system the delay would ncrease strongly. The ntal data for the archtecture of SUMA. Example of x86-64 archtecture wll take CPU AMD Athlon64 class a frequency of 2800 MHz (Athlon 64 FX 57). The frequency of HT s for the model 1000 MHz (Tcycle = 1 ns). When studyng the effect of CPU performance on the subsystem "processor-memory" revewed CPU AMD Athlon64 class wth a clock frequency of 2,2-2,8 GHz. Regardng the OP module far the calculatons made above. Vop = 22,5 ns. Transfer 64-bt words from the module memory at 200 MHz the memory bus takes 1 clock cycle. 1 5= 5 ns. Thus, the average address to local memory wll occur at the tme of = 27, 5 ns. To transfer 32-bt address data from the CPU to the controller va hgh speed nternal bus beleve that t takes one clock cycle. 1 1 = 1 ns. Ths same word wll be passed to CPU for 1 clock cycle nternal bus 1 1 = 1 ns. Obtan, takng nto account the mathematcal model s constructed, all of whch appeal to the bus wll be 2 ns. Analyss of the mpact of effcency of the cache on the real capacty of the subsystem "processor-memory". Intal data: the number of modules n the OP QS = 4; the number of CPU load source = 4; servce tme applcatons wth one channel (the module OP) = 27, 5 ns; HT bus latency = 2 ns. The ntensty of the flow of requests n the smulaton was changed as follows: the probablty of a cache mss, % (CPU clock frequency). Range probablty of cache msses - 0,5-3%. The results of the study are shown n Fgure

7 Fgure-12. Dependence of the memory response tme (1) and the average number of tasks n the system (2) of the CPU performance. Fgure-11. The dependence of the queue length before the devce (1), a load factor (2), the response tme of memory (3), the watng tme n the queue the applcaton (4) and the average number of orders n the system (5) of the probablty of a cache mss. When ht n the cache 99 % of the queres (the flow of applcatons from CPU to memory 0,028 query/ns): the average number of tasks n the system, m = 13,413 tasks; the average queue length l = 10,311 tasks; task watng tme = 92,066 ns; the resdence tme of the task n the NS (memory response tme) = 119,766 ns. When the flow of tasks query 0,042 / ns (the value of a cache mss s 1, 5%), the system s overloaded (load factor s 1,155). By ncreasng the effcency of the cache memory 2 tmes (the number of cache hts s 99, 5%) Response tme memory s 44,916 ns, whch s compared wth the orgnal one preferably about 37, 5%. Analyss of the CPU performance mpact on the real capacty of the subsystem "processor-memory". Intal data: the number of modules OP n the QS = 4; the number of CPU load source = 4; servce tme applcatons wth one channel (the module OP) n = 27,5 ns; HT bus latency = 2 ns; Task flow rate l = 0,028-0,038 query/ns. The smulaton results are shown n Fgure-12. It s obvous that wth the growth of CPU tme, memory response ncreases (from Fgure 7 from 69,821 to 119,766 ns). The value of ths characterstc s ncreased by 1, 7 tmes. The average number of tasks n the system ncreases from 6,144 to 13,413,.e. more than 2 tmes. The watng tme n the queue s also ncreased approxmately 2-fold. Analyss of the nfluence of the tme of memory access to the real capacty of the subsystem "processormemory". In ths archtecture, there s the lkelhood that the block of memory IP, located n 2 connected n seres tres. Wth ths n mnd, the memory access tme s ncreased by 2 ns. Let s consder ths case. Intal data: the number of servce channels (OP unts) n the QS = 4; the number of CPU load source = 4; tme mantenance tasks one channel (the module OP) = 27, 5-29, 5 ns; HT bus latency = 2 ns, task flow rate = 0, 028 query/ns. The resultng graph s shown n Fgure-13. Fgure-13. Dependence applcatons queue length (1), the watng tme n the queue (2) and the response tme of the memory (3) from the memory access tme. Based on the results, we fnd that when referrng to a local unt PU remote queue length l memory s ncreased by 1, 5 tmes, whle watng n the queue ncreases by 47,275 ns and a memory response tme s 13532

8 ncreased by 30% compared wth the reference to the adjacent memory module CPU. Comparson of smulaton results for SUMA and NUMA archtectures. Features of the system based on SUMA archtecture wth a four organzatons slghtly less from such a system, NUMA archtecture, due to a smlar organzaton. At the same tme congeston and delay at a hgh-speed ral a lot less. Tre load results are shown n Fgure-14. Fgure-14. Dependence of the memory response (1, 2), the watng tme n the queue (3, 4) and the average number of customers n the system (5, 6) on the probablty of a cache mss n the four processes systems archtectures, NUMA and SUMA accordngly. 5. CONCLUSIONS By results of the conducted researches t s possble to make the followng outputs. When functonng n the multtask mode the flow of requests contnuously ncreases n MVS of archtecture of UMA that explans bgger number of the servced requests. At the same tme latency of memory of ths system s lower, than n case of the sngle-task mode. Ths results from the fact that CPU, wthout expectng the response of memory, make new request. At the same tme vablty of system s hgher as even n case of a hgh flow of requests the system sn't overloaded n dfference from the frst where the subsystem of memory doesn't cope wth hgh ntensty of requests. The archtecture of NUMA dffers n the fact that n case of sharp ncrease of a flow of requests n memory modules on the common bus there s a sharp ncrease n tme of the response of memory as the multprocessor's bus s permanently occuped, t leads to growth of wat tme. Though n case of a constant flow of requests stablty of system operaton s watched. The developed models can be used n case of desgn of the multprocessor computng systems. These developments gve an opportunty to make an assessment of characterstcs of the multprocessor systems and ther subsystems wthout creaton of a real prototype. At the expense of t economc effect as the assessment of characterstcs of the desgned systems and a choce of the most optmal varants can be carred out wthout creaton of real system s reached. In artcle mathematcal models of a subsystem "processor memory" whch wth ease can be used n case of desgn of new multprocessor computng systems and enhancement of already avalable are offered. The consdered optons gve the chance to make an assessment of characterstcs of the multprocessor systems and ther subsystems wthout creaton of a real prototype. At the expense of t economc effect as the assessment of characterstcs of the desgned systems and a choce of the most optmal varants can be carred out wthout creaton of real system s reached. Results of the conducted researches allow to gve the grounds for a row of outputs. MVS of archtecture of NUMA dffers n the fact that n case of sharp ncrease of a flow of requests n memory modules on the common bus there s a sharp ncrease n tme of the response of memory as the multprocessor's bus s permanently occuped, t leads to growth of wat tme. Though n case of a constant flow of requests stablty of system operaton s watched. When comparng characterstcs of the bus we wll draw a concluson that the bus Hyper Transport (SUMA archtecture) really possesses hgher throughput, and ts loadng s rather small that s explaned by the specal organzaton of an nterprocessor exchange. That s the multprocessor SUMA system possesses bgger real throughput from the pont of vew of an exchange wth memory, unlke archtecture wth the common multprocessor's bus. Hgh scalablty of system allows ncreasng advantage of the bus nterface of SUMA systems repeatedly. It s necessary to carry to advantages of ths archtecture also that the controller of memory s ntegrated nto a CPU crystal at the expense of what the address to hm happens wthout nvolvement of the front-sde bus, and the controller works at CPU frequency. ACKNOWLEDGEMENT The work has been done wth the fnancal support of RFBR (Grant No A). REFERENCES [1] Alyev T.I The Bascs of Dscrete System Modelng. SPb.: SPbGU ITMO. p [2] Matalytsky M.A., Tchonenko O.M. and Koluzayeva Ye.V The Queung Systems and Networks: the Analyss and Applcatons: The Monograph. Grodno: GrGU, 1, pp [3] Lozhkovsky A.G The Queung Theory n Telecommuncatons: Textbook. Odessa: ONAS named after A.S. Popov, pp

9 [4] Tanenbaum A. and Bos H. Modern operatng systems. The 4 th Edton. SPb.: Pter. p [5] Martyshkn, A.I. & Yasarevskaya, O.N Mathematcal modelng of Task Managers for Multprocessor systems on the bass of open-loop queung networks. ARPN Journal of Engneerng and Appled Scences. 10(16): [6] Abramov V.M Stochastc Analyss and Applcatons. 24(6): [7] Martyshkn A.I Research of algorthms plannng processes n Real Tme Systems. In collecton: Modern methods and means of the processng of spatal-temporal sgnals collecton of artcles XIII All-Russan scentfc and techncal conference. Edted I.I. Salnkov, pp [8] Martyshkn, A.I Research of memory subsystem wth buffered transactons on models of queung. 21st Century: The Resumes of the Past and the Challenges of the Present Plus: Scentfc and Methodologcal Journal. Penza: PGTA. 3 (03). pp [9] Martyshkn A.I Development and research of open-loop models of the subsystem "processor-memory" of Multprocessor systems archtectures UMA and NUMA. Herald of Ryazan State Unversty of Rado Engneerng. (54-1): [10] Martyshkn, A.I Mathematcal modelng of the hardware memory buffer for Multprocessor systems. In collecton: Optcal-electronc nstruments and devces n systems of pattern recognton, mage processng, and character nformaton, the collecton of materals of XII Internatonal scentfc-techncal conference. pp [11] Martyshkn, A.I Analytcal model for the analyss of archtectures of Mcroprocessor systems wth memory NUMA and COMA. In collecton: Modern scentfc research: theoretcal and practcal aspects. Collecton of artcles of Internatonal scentfc-practcal conference. Responsble edtor: Sukasyan Asatur Albertovch. pp [12] Kempa, Wojcech M Stochastc Models. 26(3): [13] Masuyama Hroyuk and Takne, Tetsuya. Stochastc Models. 19(3): [14] Nadarajah Saralees Stochastc Analyss and Applcatons. 26(3): [15] Mkhalev V Performance Test Results QNX Neutrno. Modern Automaton Technology: Scentfc and Techncal Journal. (2): [16] Certfcate of state regstraton, e-number Program complex for measurng the performance of the functons of operatng systems. [17] Martyshkn A.I Implementaton of the hardware memory buffer for Multprocessor system. In collecton: New nformaton technologes and systems for the collecton of scentfc artcles of the XII Internatonal scentfc-techncal conference. pp [18] Martyshkn A.I Hardware development of memory buffer devces for Multprocessor systems. Fundamental research. (12-3): [19] Martyshkn A.I To the queston of assessng servce tme of the applcatons when performng exchange operatons n Multprocessor systems-on-chp wth shared memory. In collecton: Prortes of the world scence: scentfc experment and dscusson Materals of X nternatonal scentfc conference. pp [20] Martyshkn, A.I To the problem of the constructon of memory subsystem of Multprocessor systems, n collecton: Informaton technologes n the economc and techncal problems Collecton of scentfc works of Internatonal scentfc-practcal conference, pp [21] Martyshkn, A.I Investgaton of performance hgh performance Multprocessor systems on open queung networks. Innovatons n scence. 54, pp [22] Martyshkn, A.I To the queston of hardware support for process synchronzaton n Multprocessor operatng real-tme systems. New scence: From dea to result. 2-3 (66), pp [23] Martyshkn, A.I Modelng of Multprocessor systems memory subsystem wth a buffer devce wth multple queues, based on open queung networks. Innovatons n scence. 55-2, pp [24] Martyshkn, A.I To the problem of research memory subsystem of Multprocessor computer systems. In collecton: Scence n modern socety: patterns and 13534

10 trends collecton of artcles of Internatonal scentfcpractcal conference: n 2 parts, pp [25] Certfcate of state regstraton, e-number The program package for the calculaton of probabltytme characterstcs of stochastc queung networks