PE310G4DBIR-T Intel FM10420 Based Quad Port Copper 10 Gigabit Ethernet PCI Express Content Director Server Adapter

Transcription

1 PE310G4DBIR-T Intel FM10420 Based Quad Prt Cpper 10 Gigabit Ethernet PCI Express Cntent Directr Server Adapter Prduct Descriptin Silicm s 10 Gigabit Ethernet PCI Express cntent aware directr Bypass server adapters is designed fr servers and high-end appliances. The Silicm cntent aware directr server adapter is designed with an n bard smart ruting architecture that enables packets t be redirected r drpped based n defined rules. The Silicm s 10 Gigabit Ethernet cntent aware packet directr reduces hst system prcess since nly packets that are defined t be targeted t the hst systems are ruted t the hst; ther packets can be ruted t the ther prt r can be drpped by the cntent aware hardware ruting architecture. The Silicm s 10 Gigabit Ethernet cntent aware packet directr is targeted t netwrk applicatins that needs t prcess, mnitr r bypass packets based n defined rules. The adapter supprts three main mdes f peratin: Cntent Aware Bypass, Cntent Aware TAP and cntent Aware filtering NIC. Cntent Aware Bypass Silicm s 10 Gigabit Ethernet cntent aware directr prvides intelligent packet redirectin capability where rules specify which packets are directed t the hst system and which packets are directed t the ther prt (Bypass). Cntent Aware TAP Silicm s 10 Gigabit Ethernet cntent aware directr prvides intelligent packet redirectin capability where all packets are directed t the ther prt (Bypassed) and rules specify which packets are cpied t the hst system ( TAP). Cntent Aware Filtering NIC Silicm s 10 Gigabit Ethernet cntent aware prvides intelligent packet redirectin capability where rules specify which packets are directed t the hst r drpped. The Silicm 10 Gigabit Ethernet PCI Express cntent directr server adapter is based n Intel FM10420 Ethernet cntrller and a L3 switch ruter. The Silicm s 10 Gigabit Ethernet PCI Express adapter is based n standard L2 driver and with the cntent directr engine reduces CPU hst system prcessing. The Silicm 10 Gigabit Ethernet PCI Express cntent aware server adapter ffers simple integratin int any PCI Express X8 t 10Gigabit Netwrk. 1Page Silicm Ltd. Cnnectivity Slutins

2 Key Features Cntent Aware Directr: Prvides intelligent packet redirectin capability where rules specify which packets are directed t the hst system and which packets are directed t the ther prt (Bypass). Prvides intelligent packet redirectin capability where all packets are directed t the ther prt (Bypassed) and rules that specify which packets are cpied t the hst system ( TAP). Prvides intelligent packet filtering / drp capability where rules specify which packets are directed t the hst r drpped. Prvides redirectin rules that can be defined using surce IP/ destinatin IP / Surce Prt / Destinatin Prt / VLAN tuples. Redirectin and packet filtering / drp are perfrmed by the hardware itself in wire speed and d nt require any sftware and CPU hst system pwer prcessing. Intelligent redirect mechanism is cntrllable via sftware. Intelligent ruting mechanism is cntrllable via sftware Bypass / Discnnect: Bypass / Discnnect Ethernet prts n Pwer Fail, System Hangs r Sftware Applicatin Hangs. Sftware prgrammable Bypass, Discnnect r Nrmal Mde. On Bard Watch Dg Timer (WDT) Cntrller. Sftware prgrammable time ut interval. Sftware Prgrammable WDT Enable / Disable cunter. Sftware prgrammable Bypass Capability Enable / Disable. Sftware Prgrammable Discnnect Capability Enable / Disable. Sftware Prgrammable mde (Bypass, Nrmal r Discnnect mde) at Pwer up. Sftware Prgrammable mde (Bypass, Nrmal mde) at Pwer ff. Independent Bypass peratin in every tw prts. Emulates standard NIC Cpper 10 Gigabit Ethernet 10GBASE-T: Integrated 10 Gigabit Cpper PHY supprts 10GBASE-T, 1000 BASE- T and 100BASE- TX Triple speed 10Gbps (10GBase-T), 1000Mbps (1000Base-T) and 100 Mbps (100Base-T) RJ-45 cnnectr supprts CAT 6A, CAT7 cable Cmmn Key features: Hst Interface: PCI Express X8 lane Supprt PCI Express Base Specificatin Revisin 3.0, 8GT/s, 5GT/s r 2.5GT/s SR-IOV enabled t expse t 4 Virtual Functins (VF) 2Page Silicm Ltd. Cnnectivity Slutins

3 Intel FM10420 Features: Single-element 4MB shared memry L2/L3/L4/OpenFlw frwarding & ACLs Stateless lad balancing t CPUs Datacenter Bridging (lssless Ethernet) 32K 40-bit TCAM entries 16K MAC & NextHp tables Up t 300Gbps High-bandwidth CPU interface 2x 50Gbps 8-lane PCIe interfaces 4x 25Gbps 4-lane PCIe interfaces Up t 8 25G/10G/2.5G/1G prts Up t 2 40G (4 x 10G) Up t 2 100G (4 x 25G) 300ns netwrk latency (100GbE) 1000nS hst-netwrk latency LAN Features: 256 queues per PCIe x8 interface SR-IOV (64 VFs per PCIe x8 interface) IP/TCP/UDP checksum Receive side scaling (RSS) TCP segmentatin fflad (TSO/LSO) LEDs indicatr fr link/activity Technical Specificatins Bypass Specificatins: WDT Interval (Sftware Prgrammable): 3,276,800 msec (3,276.8 Sec): Maximum 100 msec ( 0.1 Sec) : Minimum WDT Interval = (2^wdt_interval_parameter)*(0.1) sec. wdt_interval_parameter: { Valid Range: 0-15} Cpper 10 Gigabit Ethernet Technical Specificatins (10GBASE-T): IEEE Standard / Netwrk tplgy: Cpper 10Gigabit Ethernet, 10GBASE-T Gigabit Ethernet, 1000Base-T 100 Mb Ethernet : 100BASE- TX 3Page Silicm Ltd. Cnnectivity Slutins

4 Data Transfer Rate: 20 Gb/s, 2000Mb/s and 200 Mb/s in full duplex mde per prt Cables and Operating distance: Up t: 100Base-Tx Categry 5 maximum 50m1 1000Base-T Categry 5E maximum 50m1 10GBase-T Categry 6A,7 maximum 50m2 1. 1Theretical Distance Defined as half a distance as stated by the IEEE standard 2. 2Theretical Distance Defined as half a distance as stated by the IEEE 802.3an standard Operating Systems Supprt: Operating system supprt: Linux PE310G4DBIR-T General Technical Specificatins: Interface Standard: PCI-Express Base Specificatin Revisin 3.0(8 GTs) Bard Size: Standard height lng add-in card mm X mm (9.5 X ) PCI Express Card Type: X8 Lane PCI Express Vltage: +3.3V ±9%, +12V ± 8% External Vltage frm external PW jack: +12V ± 8% PCI Cnnectr: Gld Finger: X8 Lane Cntrller: Intel FM10420 Hlder: Metal Bracket Operating Humidity: 0% 90%, nn-cndensing Operating Temperature: 0 C 40 C (32 F 104 F), Air flw requirement 200FLM Strage: -40 C 65 C (40 F 149 F) EMC Certificatins: FCC Part 15, Subpart B Class A Cnducted Emissins Radiated Emissins CE EN 55022: 1998 Class A Amendments A1: 2000; A2: 2003 Cnducted Emissins 4Page Silicm Ltd. Cnnectivity Slutins

5 Radiated Emissins CE EN 55024: 1998 Amendments A1: 2000; A2: 2003 Immunity fr ITE Amendment A1: 2001 CE EN , Class A Harmnic Current Emissins CE EN , Amendment A1: 2001 Vltage Fluctuatins and Flicker CE IEC : 1995 ESD Air Discharge 8kV. Cntact Discharge 4kV. CE IEC :1995 Radiated Immunity ( Mhz), 3V/m 80% A.M. by 1kHz CE IEC :1995 EFT/B: Immunity t electrical fast transients 1kV Pwer Leads, 0.5Kv Signals Leads CE IEC :1995 Immunity t cnductive surges COM Mde; 2kV, Dif. Mde 1kV CE IEC :1996 Cnducted immunity ( MHz) 3VRMS 80% A.M. By 1kHz CE IEC :1994 Vltage Dips and Shrt Interruptins V reduc >95%, 30% >95% Duratin 0.5per, 25per, 250per PE310G4DBIR-T LEDs/ Cnnectrs Specificatins: LEDs: (2) LED per prt Speed / Bypass / Discnnect(Left): Link f 1Gb/s: Turns n link (Yellw) Link f 10Gb/s: Turns n link (Green) Bypass: Blink (Green) n Bypass Discnnect: Blink (Yellw) ACT(Right) : Blinks n activity (Green) LEDs lcatin: LEDs are lcated in the RJ45 cnnectr prt Cnnectr: (4) Shielded RJ-45 5Page Silicm Ltd. Cnnectivity Slutins

6 Functinal Descriptin Directr Directr Cntent Aware Bypass Silicm s 10 Gigabit Ethernet cntent aware directr Prvides intelligent packet redirectin capability where rules specify which packets are directed t the hst system and which packets are directed t the ther prt (Bypass). Figure 1: Cntent Aware Bypass Functinal Blck Diagram Figure 1 illustrates functinal blck diagram f cntent aware Bypass: Packets received in prt A and meet rule are directed t prt B, ther packets are directed t prt C (Bypass). Packets received in prt C and meet rule are directed t prt D, ther packets are directed t prt A (Bypass). Directr Cntent Awar TAP Silicm s 10 Gigabit Ethernet cntent aware directr Prvides intelligent packet redirectin capability where all packets are directed t the ther prt (Bypassed) and rules specify which packets are cpied t the hst system (TAP). Figure 2: Cntent Aware TAP Functinal Blck Diagram Figure 2 illustrates functinal blck diagram f cntent aware TAP: Packets received in prt A and meet rule are directed t prts B and C (TAP), ther packets are directed t prt C (Bypass). Packets received in prt C and meet rule are directed t prts D and A (TAP), ther packets are directed t prt A (Bypass). Directr Cntent Filtering NIC Silicm s 10 Gigabit Ethernet cntent aware prvides intelligent packet redirectin capability where rules specify which packets are directed t the hst r drpped. 6Page Silicm Ltd. Cnnectivity Slutins

7 Figure 3: Cntent Aware Filtering NIC Functinal Blck Diagram Figure 3 illustrates functinal blck diagram f cntent aware TAP: Packets received in prt A and meet rule, direct t prt B. Packets received in prt A and d nt meet rule are drpped. Packets received in prt C and meet rule, direct t prt D. Packets received in prt C and d nt meet rule are Drpt. Directr Lad balancing Silicm s 10 Gigabit Ethernet cntent aware directr prvides a lad balancing f the traffic cming frm the 4 x 10G external prts (0,2,4 and 6). The traffic is balanced, based n a defined hash cnfiguratin (5 tuple r ther), t the 4x 10G internal interfaces ( 1,3,5 and 7)that are ging t the hst. Figure 4: Lad Balancing Functinal Blck Diagram Figure 4 illustrates functinal blck diagram f Lad Balancing: Packets received in the 4 x 10G external prts (0,2,4 and 6) t be balanced based n a defined hash cnfiguratin (5 tuple r ther), t the 4x 10G internal interfaces (1,3,5and 7) that are ging t the hst. If there is external prt that is heavily laded the traffic will g int the 4 internal interfaces with balanced lad. An ISL tag is added t all incming packets, it enable the hst t knw the surce prt, packest that are sent back frm the hst are striedp frm the ISL tag. 7Page Silicm Ltd. Cnnectivity Slutins

8 Tagged In-Line rule aware mde Silicm s 10 Gigabit Ethernet cntent aware directr Prvides intelligent packet redirectin capability where rules specify which packets are directed t the hst system and which packets are directed t the ther prts (Bypass) but at the same time it will get these bypassed trfic int the hst with a ISL tag marking that these packets are bypassed, per the rules that the hst will issue t the Silicm s 10 Gigabit Ethernet cntent aware directr. Figure 5: Tagged In-Line rule aware mde Blck Diagram Figure 5 illustrates functinal blck diagram f Tagged In-Line rule aware mde: Prt Grup (0, 1), (2, 3), (4, 5), (6, 7) cnfigured as VLAN grups. Packets received in the 4 x 10G external prts (0, 2, 4 and 6) and meet and are directed t the ther prts f the Vlan grup with ISL tag that ntify that match fund. The riginal packet is sent t the Output Prt f Switch in the rule matched plicy Packets received in the 4 x 10G external prts (0,2,4 and 6) and d nt meet the rule are directed t the ther prts f the Vlan grup taged with ISL tag that ntify that n-match fund. Directr: Rules Classificatin and capabilities Directr Capabilities The Redirectr supprts the fllwing capabilities: Maximum ttal number f rules is 16K Each f the 16K rules can be defined t any prt the n bard multi-layer switch Each rule refers t incming packet Rules are executed per rder. First rule that matches will be executed Rules can be added and remved n the fly Each rule can include ne r mre classificatin fields. A rule match will be when all fields defined are match Each field can have a bit masking t check part f the classificatin field Per prt statistics can be read, like packets cunt, errrs, VLAN, and mre Rules and actin are dne in wire speed at any packet size 8Page Silicm Ltd. Cnnectivity Slutins

9 Rules classificatin fields Rules classificatin is dne based n the first 128 bytes f the packets. The fllwing list prvides rules classificatin fields MAC address, surce & destinatin IPv4 surce & destinatin IP IPv6 surce & destinatin IP L4 Prt surce & destinatin prt Ethernet Prtcl ethertype IP Prtcl num VLAN ID tagging User defined fields DSCP match the different services cde pint the six mst significant bits f the Type f Service ctet (IPv4) r Traffic Class ctet (IPv6).* IPv6 Flw Label* IP length* ISL Frame Type* ISL USER* Surce & destinatin prt range* VLAN pririty* VLAN tag type* TCP flags* TOS match Type f Service ctet (IPv4) r Traffic Class ctet (IPv6)* TTL field in a IPv4 header r Hp Limit in a IPv6 header* *Future SW supprts Executin per rule The fllwing Executins per rule are supprted: Drp when a rule matches the packet will be drpped Redirect when a rule matches redirect the packet t the defined destinatin prt Mirrr when a rule matches cpy packet als t a defined destinatin prt Directr Advanced Features: Prt trunking between the different Intel 10G prts t the Fulcrum 10G prts cnnected t it fr lad balancing between the different Intel prts Prt trunking between the different External Fulcrum prt t the external switch cnnected t it fr lad balancing between the different external prts 9Page Silicm Ltd. Cnnectivity Slutins

10 Sessin balancing with L3/L4 hashing r ther mechanism ISL (Inter Switch Link) Tagging per prt can be added t the packets per cnfiguratin ISL Tagging can be remved and can be frward t specific prt per the ISL index Quality f Service supprt with the fllwing features: Pririty levels: 16 internal switch pririties, 8 r 16 VLAN pririties (ptinal use f CFI bit as an extra VLAN pririty bit) Arbitrary mapping f ingress VLAN pririty t an internal VLAN pririty Arbitrary mapping f an internal VLAN pririty t egress VLAN pririty Arbitrary mapping f internal VLAN pririty t switch pririty Arbitrary mapping f DSCP t switch pririty, cnfigurable pririty surce selectin Scheduler: 8 traffic classes, arbitrary mapping f switch pririties t traffic class, deficit weighted rund-rbin r strict pririty Ntificatin: Tw cngestin ntificatins can be supprted Virtual utput queue cngestin ntificatin (VCN) and Intel prprietary backward cngestin ntificatin (FCN) Open Flw supprt (cnsistent with OpenFlw prtcl standard) sflw supprt User defined Packet transmissin with tw ptinal mdes: 1. Simple mde transmit n specific prt. 2. Switched mde where switch determines destinatin prt/prts, r with specific infrmatin such as whether r nt egress prcessing rules shuld be applied Strm Cntrl Management Switch can supprt a variety strm cntrller. Each strm cntrller can be prgrammable t define rat, cnditin (like unicast ICMP frames whse TTL is at mst 1), frame type (can be OR ed), ingress & egress prt prts. Actins: d nthing, drps frames t prt (accrding t filter) *Future SW supprts Bypass / Discnnect Silicm s Bypass adapter supprts the fllwing mde states: Nrmal/inline, Bypass/Fail-T-Wire and Discnnect mdes. Nrmal/Inline mde In Nrmal mde, the prts are independent interfaces (see Figure 6: Nrmal mde, ne Bypass pair is illustrated). 10Page Silicm Ltd. Cnnectivity Slutins

11 Figure 6: Nrmal Mde Functinal Blck Diagram Bypass/Fail-T-Wire mde In Bypass mde, the cnnectins f the Ethernet netwrk prts are discnnected frm the interfaces and switched ver t the ther prt t create a crssed cnnectin lp-back between the Ethernet prts. The cnnectins f the interfaces are left uncnnected. (See Figure 7: ne Bypass pair illustrated) Figure 7: Bypass Mde Functinal Blck Diagram Discnnect mde In Discnnect mde, the transmit cnnectins f the interfaces are discnnected frm the prts. The switch / ruter cnnected t the adapter des nt detect link partner (See Figure 8): Figure 8: Discnnect Mde Functinal Blck Diagram Bypass/Discnnect Features: Silicm s Bypass server adapter supprts sftware prgrammable t select Nrmal, Bypass r Discnnect mdes. Silicm s Bypass adapters supprts Disable Bypass, Disable Discnnected capabilities; hence, if thse adapters receive Disable Bypass capability / Disable Discnnect cmmands, the adapter des nt Bypass / des nt Discnnect its Ethernet prts, The Disable Bypass Capabilities are reserved als after pwer ff. This feature enables t emulate a standard NIC. Key Features: All mdes f peratin are fully sftware cnfigured with a well-defined and easy t use API Disable bypass/discnnect fr a standard NIC emulatin and peratin, retained even with pwer cycle Range f Watchdg timer timing, cnfigurable fr detecting appliance failure Watchdg timer reset functin by applicatin r self-reset by the prduct bypass driver Easy t read prduct status and prduct features capabilities 11Page Silicm Ltd. Cnnectivity Slutins

12 Fast switching between mde with less than 10mS f transit time Cmpatible with all Silicm bypass prducts, ne driver set and cmmand set fr all prducts Order Infrmatin P/N Descriptin Ntes PE310G4DBIR-T Quad prt Cpper 10 Gigabit Ethernet PCI Express Cntent Directr Server Adapter RHS Cmpliant, X8 Gen 3, based n Intel FM V3 12Page Silicm Ltd. Cnnectivity Slutins