PE2G4BPI80L Quad Port Copper Gigabit Ethernet PCI Express Gen 2.0 Bypass Server Adapter Intel Based

Transcription

1 PE2G4BPI80L Quad Prt Cpper Gigabit Ethernet PCI Express Gen 2.0 Bypass Server Adapter Intel Based Prduct Descriptin Silicm s Quad Prt Cpper Gigabit Ethernet PCI Express Bypass server adapter is a PCI-Express X8 netwrk interface card that cntains fur prts n a PCI-E adapter. Silicm s Quad Prt Gigabit Ethernet Bypass server adapter supprts Nrmal, Discnnect and Bypass mdes. In Nrmal mde, the prts are independent interfaces. In Bypass mde, all packets received frm ne prt are transmitted t adjacent prt. In Discnnect mde, the adapter simulates switch / rut cable discnnectin. In Bypass mde, the cnnectins f the Ethernet prts are discnnected frm the system and switched ver t the ther prt t create a crssed cnnectin lp-back between the Ethernet prts. Hence, in bypass mde all packets received frm ne prt are transmitted t the adjacent prt and vice versa. This feature enables t bypass a failed system and prvides maximum up time fr the netwrk. In Discnnect mde, the adapter simulates switch / ruter cable discnnectin. In Discnnect mde, the switch / ruter des nt detect link partner f the adapter. Silicm s Quad Prt Cpper Gigabit Ethernet PCI Express Bypass server adapters include an n bard WDT (Watch Dg Timer) cntrller. The adapter s sftware drivers r sftware applicatin can write cmmands t the n bard WDT cntrller. The adapter s sftware drivers, WDT cntrller and the Bypass circuitry prvide an interface that cntrl and manage the mde f the adapter. Silicm s Quad Prt Cpper Gigabit Ethernet PCI Express Bypass server adapters are based n Intel 82580EB Ethernet cntrller with quad fully integrated Gigabit Ethernet Media Access Cntrl (MAC) and PHY. In additin t managing MAC and PHY Ethernet layer functins, the cntrller manages PCI Express packet traffic acrss its transactin, link, and physical/lgical layers. Silicm s Quad Prt Cpper Gigabit Ethernet PCI Express Bypass server adapters are the ideal slutin fr implementing multiple netwrk segments, missin-critical high-pwered netwrking applicatins and envirnments within high perfrmance servers. 1Page

2 Key Features Bypass: Bypass / Discnnect Ethernet prts n Pwer Fail, System Hangs r Sftware Applicatin Hangs Sftware prgrammable Bypass, Discnnect r Nrmal Mde On Bard Watch Dg Timer (WDT) Cntrller Sftware prgrammable time ut interval Sftware Prgrammable WDT Enable / Disable cunter Sftware prgrammable Bypass Capability Enable / Disable Sftware Prgrammable Discnnect Capability Enable / Disable Sftware Prgrammable mde (Bypass, Nrmal r Discnnect mde) at Pwer up Sftware Prgrammable mde (Bypass, Nrmal mde) at Pwer ff Independent Bypass peratin in every tw prts Cpper Gigabit Ethernet 1000Base-T : Independently cpper Gigabit Ethernet channels supprt fur Gigabit Ethernet (1000Base-T), Fast Ethernet (100Base-Tx) and Ethernet (10Base-T) Triple speed 1000Mbps (1000Base-T), 100 Mbps (100Base-Tx) and 10 Mbps (100Base-T) peratin Nway aut negtiatin autmatic sensing and switching between 1Gbps full duplex and 100 / 10 Mbps peratins Simplex r Full Duplex RJ-45 female cnnectrs Perfrmance Features: 8 Transmit and Receive queues per prt Up t 8 queues f Receive Side Scaling (RSS) minimize CPU utilizatin acrss multiple prcessr systems Supprt fr 8 pls (single queue) f virtual machine Device Queues (VMDq) per prt Supprt Direct Cache Access (DCA) Supprt Intel I/O Acceleratin Technlgy v3.0 TSO interleaving fr reduced latency Minimized device I/O interrupts using MSI and MSI-X UDP, TCP and IP checksum fflad UDP and TCP transmit segmentatin fflad (TSO) SCTP receive and transmit checksum fflad Packet interrupt calescing timers (packet timers) and abslute- delay interrupt timers fr bth transmit and receive peratin Cmmn Key features: 2Page

3 Supprt PCI Express Base Specificatin 2.0 (5 GTs) High perfrmance, reliability, and lw pwer use in Intel Quad integrated MAC + PHY and SERDES chip Cntrllers Ultra deep, packet buffer per channel lwers CPU utilizatin Hardware acceleratin that can fflad tasks frm the hst prcessr. The Cntrllers can fflad TCP/UDP/IP checksum calculatins and TCP segmentatin Server class reliability, availability and perfrmance features Link Aggregatin and Lad Balancing Switch dependent: 802.3ad (LACP), Generic Trunking ( GEC / FEC) Switch and NIC Independent Failver Pririty queuing 802.1p layer 2 pririty encding Virtual LANs 802.1q VLAN tagging Jumb Frame (9.5KB) 802.x flw cntrl Multicast/ bradcast Packet replicatin Statistics fr SNMP MIB II, Ethernet like MIB, and Ethernet MIB (802.3z, Clause 30) Supprts Vital Prduct Data (VPD) LEDs indicatrs fr link/activity/bypass Mde status Technical Specificatins Bypass Specificatin: WDT Interval (Sftware Prgrammable): 3,276,800 msec (3,276.8 Sec): Maximum 100 msec ( 0.1 Sec) : Minimum WDT Interval = (2^wdt_interval_parameter)*(0.1) sec. wdt_interval_parameter: {Valid Range: 0-15} Cpper Gigabit Ethernet Technical Specificatins (1000Base-T) Adapters: IEEE Standard / Netwrk tplgy: Gigabit Ethernet, 1000Base-T Fast Ethernet, 100Base-TX Ethernet, 10Base-T Full duplex / Simplex: Supprt bth Simplex & Full duplex peratin in all perating speeds Aut negtiatin: Aut-negtiatin between Full duplex and simplex peratins and between 10Mb/s 100Mb/s 3Page

4 speeds and duplex 1000Mb/s Data Transfer Rate: 1000 Mbit/s, 100 Mbit/s and 10 Mbits/sec in simplex mde per prt. 2000Mbit/s 200 and 20 Mbit/s in full duplex mde per prt Cables and Operating distance: 10Base-T Categry 3, 4, r 5 maximum 50m * 100Base-Tx Categry 5 maximum 50m * 1000Base-T Categry 5E maximum 50m * *Theretical Distance Defined as half a distance as stated by the IEEE standard Operating Systems Supprt Operating system supprt: Windws Linux FreeBSD VMware General Technical Specificatins Interface Standard: PCI-Express Base Specificatin Revisin 2.0 (5 GTs) Bard Size: Lw prfile shrt add-in card: mm X 68.91mm (6.60 X ) PCI Express Card Type: X8 PCI Express Vltage: +12V +- 8% PCI Cnnectr: Gld Finger: X4 Cntrller: Intel Hlder: Metal Bracket: Full Height/Lw prfile Height I/O: Quad RJ45 lcated n edge f the bard Pwer Cnsumptin: Nrmal mde: 5.16W, 0.43A at 12V: Typical all prts perate at 1000Mb/s. 3.72W, 0.31A at 12V: Typical all prts perate at 100Mb/s. 3.60W, 0.30A at 12V: Typical all prts perate at 10Mb/s. 3.12W, 0.26A at 12V, 0.76A at 3.3V: Typical N link at all prts. Bypass mde: 2.88W, 0.24A at 12V: Typical Bypass Mde Discnnect mde: 2.88W, 0.24A at 12V: Typical Bypass Mde 4Page

5 Operating Temperature: 0 C 50 C (32 F 122 F) Strage: -20 C 65 C (-4 F 149 F) EMC Certificatins: CE EN 55022: 1998 Class B Amendments A1: 2000; A2: 2003 Cnducted Emissins Radiated Emissins CE EN 55024: 1998 Amendments A1: 2000; A2: 2003 Immunity fr ITE Amendment A1: 2001 CE EN , Class A Harmnic Current Emissins CE EN , Amendment A1: 2001 Vltage Fluctuatins and Flicker CE IEC : 1995 ESD Air Discharge 8kV. Cntact Discharge 4kV. CE IEC :1995 Radiated Immunity ( Mhz), 3V/m 80% A.M. by 1kHz CE IEC :1995 EFT/B: Immunity t electrical fast transients 1kV Pwer Leads, 0.5Kv Signals Leads CE IEC :1995 Immunity t cnductive surges COM Mde; 2kV, Dif. Mde 1kV CE IEC :1996 Cnducted immunity ( MHz) 3VRMS 80% A.M. By 1kHz CE IEC :1994 Vltage Dips and Shrt Interruptins V reduc >95%, 30% >95% Duratin 0.5per, 25per, 250per MTBF: 159 (Years) *Accrding t Telcrdia SR-332 Issue 1 Envirnmental cnditin GB (Grund, Fixed, Cntrlled). Ambient temperature 25 C. Temperature rise f 15 C abve the system ambient temperature was assumed fr the cards cmpnents LEDs LEDs: (2) LEDs per prt Left LED: Link/Act : Turns n link (Green), Blinks n activity (Green) Right LED : Link Speed / Bypass / Discnnect : Turns n Yellw 1G Link. Turns n Green 100M Link 5Page

6 Turn ff n 10M link Blink Yellw n Discnnect Blink Green n Bypass LEDs lcatin: LEDs are lcated abve their wn RJ45 cnnectr prt Cnnectrs: (1) Shielded quad RJ-45 Functinal Descriptin Silicm s Quad Prt Bypass adapter supprts Nrmal, Bypass and Discnnect mdes. In Nrmal mde, the prts are independent interfaces (see Figure 1: Nrmal mde, ne Bypass pair is illustrated) Figure 1: Nrmal Mde Functinal Blck Diagram In Bypass mde, the cnnectins f the Ethernet netwrk prts are discnnected frm the interfaces and switched ver t the ther prt t create a crssed cnnectin lp-back between the Ethernet prts. The cnnectins f the interfaces are left uncnnected. (See Figure 2: ne Bypass pair illustrated) Figure 2: Bypass Mde Functinal Blck Diagram In Discnnect mde, the transmit cnnectins f the Ethernet netwrk prts are Discnnected frm the interfaces. (See Figure 3: ne Bypass pair illustrated) 6Page

7 Figure 3: Discnnect Mde Functinal Blck Diagram Silicm s Quad Prt Bypass adapter supprts sftware prgrammable t select Nrmal, Bypass r Discnnect mdes. Silicm s Quad Prt Bypass adapter supprts Disable Bypass, Disable Discnnected capabilities; hence, if thse adapters receive Disable Bypass capability / Disable Discnnect cmmands, the adapter des nt Bypass / des nt Discnnect its Ethernet prts, The Disable Bypass Capabilities are reserved als after pwer ff. This feature enables t emulate a standard NIC. Silicm s Quad Prt Bypass adapter supprts Disable supprts setting the default mde at pwer up and pwer ff. Thse setting are reserved als after pwer ff. Order Infrmatin P/N Descriptin Ntes PE2G4BPI80L-SD-R Quad Prt Cpper Gigabit PCI Ethernet PCI Express Gen 2.0 Bypass Server Adapter x4, Based n Intel 82580EB, PCI-E Gen 2.0, RHS cmpliant Nte: Mdel P/N -SD -SD: Side Driver -R: RHS Cmpliant / Lead free adapter 1V4 7Page