Developing a Prototyping Board for Emerging Memory

Transcription

1 Developing a Prototyping Board for Emerging Memory Sungjoo Yoo Embedded System Architecture Lab. POSTECH

2 Introduction scaling problem [ITRS, 2012] Year /2 Pitch (nm) Manufacturable solution Exist Known NOT Known STT-MRAM tech. node (nm) Manufacturable solution Exist PCRAM tech. node (nm) Manufacturable solution Exist Phase-change RAM () and Spin-transfer torque RAM (STT-RAM) are candidates SET RESET Free layer Tunneling layer Fixed layer MTJ BL e - WL SL Amorphous = high resistivity Crystalline = low resistivity (a) anti-parallel (b) parallel

3 Why Prototyping Board for New Memory? Key benefits of prototyping system are Full software execution, fast speed (w.r.t. simulation models), and closing the gap between models and real devices Gap between simulation models (or simple emulations) and real new memory designs case Real chips do not support bank parallelism in write operations due to peak write current limit Longer write latency (~20 s) than what most models assume ( ns)

4 Existing Work ONYX [UCSD, 2011] A ring-based storage array architecture and real hardware implementation Targeted at server system storage

5 Prototyping Board (ESAv5) Main PWR SD Card NVM PWR ZYNQ NV-

6 Key Components DDR3 (533MHz) 1GB 4264 MB/s FPGA Dual ARM Cortex-A9 MPCore (667MHz) L1$(I/D): 32KB/32KB L2$: 512KB 600 MB/s NV- Controller DDR3 512MB 20 MB/s Controller LPDDR2-N 128MB SD Card SDHC (class 4) 8GB

7 Board Functions Linux booting from SD card Address map Physical address is allocated to, and NV- through AXI bus 0x0000_0000 0x3FFF_FFFF (1GB) 0x4000_0000 0xBFFF_FFFF (2GB) Key features Real chip usage STT-RAM emulation (with ) Latency emulation Non-volatility (128MB) NV- (512MB)

8 [ISSCC 11] Read and Write Paths in LPDDR2-NVM interface (JEDEC standard) Read Path Upper row address Lower row address Column address RAB RDB upper lower... Cells... Internal address buffer Data out BA BA BA BA Pre-active Activate Read Write Path Overlay Window Command Code/Data/Address Command Execute Suspend/Abort Status Program Buffer Embedded Controller Cells

9 [ISSCC 11] Program Operation using Overlay Window Overlay window contains program buffer and control/status registers Address Data Execute Write Overlay Window Memory Array Embedded Controller Program

10 Controller Block Diagram Controller Init_done Initialization Logic Address Logic 0 1 Address to chip Request from AXI bus Command FSM Controller FSM Data Out Logic Data In Logic 0 1 Data from/to chip Read_not_write

11 Controller Controller FSM IDLE READ Command FSM CMD_NOP WRITE POLLING Read Request IDLE 1 READ 2 CMD_NOP 3a 3b-1 CMD_PRE 3b-2 6 CMD_PRE CMD_RD CMD_ACT CMD_WR CMD_ACT 4 5 CMD_RD

12 Address Data Execute Write Overlay Window Controller Memory Array Embedded Controller Program Controller FSM Program opration IDLE WRITE IDLE 1 11b 11a READ POLLING WRITE 2 6 POLLING 7 CMD_NOP CMD_NOP Command FSM 3a 3b-1 8a 8b-1 CMD_NOP CMD_PRE 3b-2 CMD_PRE 8b-2 CMD_PRE CMD_ACT CMD_ACT CMD_ACT CMD_RD CMD_WR CMD_WR CMD_RD

13 SD Card vs Main PWR SD Card SD Card NVM PWR ZYNQ NV- FPGA NV- Controller ARM Processor AXI4 Controller NV-

14 Write Bandwidth Comparison: SD card vs PostMark Write Bandwidth [KB/s] B B B B B B SD Card Modified PostMark for by replacing functions SD Card fopen() fread() fwrite() mmap() memcpy() *mmap for usage va_pram = mmap(/dev/mem, OFFSET);

15 Write Bandwidth Comparison: SD card vs PostMark Write Bandwidth [KB/s] B B B B B B SD Card Modified PostMark for by replacing functions SD Card fopen() fread() fwrite() mmap() memcpy() [Eom, NVRAMOS 12]

16 STT-RAM Emulation w/ Main PWR 4 Power OFF Done NVM PWR 2 Self-refresh 3 LED ON ZYNQ NV- 1 Switch ON User Input

17 Latency Emulation (NV-) FPGA 600 MB/s NV- Controller (Lat. Emul.) Variable Latency Logic DDR MB DIP Switch Preset 01: +1us 10: +2us 11: +4us Original Core Addr. Addr. Latency Data Data Core NV- Addr. Preset Latency Modified Addr. Latency Data Data

18 Read Bandwidth Sensitivity BW = size / execution time of memcpy(size) Read BW [MB/s] NV- +10ns +1000ns +2000ns size Read BW [MB/s] avg. max. NV- +10ns +1000ns +2000ns

19 Non-Volatility Emulation (NV- ) Main PWR 4 Power OFF Done NVM PWR 2 Self-refresh 3 LED ON ZYNQ NV- 1 Switch ON User Input

20 Main Power OFF & NVM Power OFF 1min. later Main Power OFF & NVM Power ON 1min. later

21 Conclusion Prototyping system for new memory Linux on ARM Cortex-A9 New memory controller design on FPGA chip (LPDDR2-N) STT-RAM emulation with Additional latency and non-volatility On-going and future work Large capacity in main memory DDR3 DIMM for STT-RAM emulation VA to PA translation schemes to reduce TLB misses write performance improvement Buffered write support Multiple chips with better technology Write bandwidth enhancement, e.g., 130MB/s [ISSCC 12]