lt1te1386~~ EX Embedded Processor IDDQ Testing

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1 lt1te1386~~ EX Embedded Processor IDDQ Testing Hitesh Ahuja Dean Arriens Ben Schneller intel. corn darriensmedona. intel. corn ch. intel. corn Vandana Verma ch. intel. corn Wendy Whitman ch. intel. corn Intel Corporation, Semiconductor Products Group, 5 W. Chandler Blvd., Chandler, AZ Introduction IDDQ testing, along with stuck-at fault, AC timing, and DC testing is increasingly considered a necessity for good product quality. This paper presents an IDDQ vector selection methodology, along with vector implementation in the production test program. IDDQ fault seeding results show that by stuck-at fault modeling, we can detect single stuck-at nodes that were not detected before. A comparative evaluation of conventional testing methods testing is presented. Experimental test results are presented that ascertain the effectiveness of ID,,, particularly how it overlaps with stuck-at fault coverage. A practical method that estimates the test coverage overlap is applied to reduce the stuck-at improvement effort and obtain credit towards the 111te1386~~ EX processor quality requirements for production. A follow-on experiment for obtaining more data is proposed and data are being collected. What is ldda? IDDQ monitoring relies on the ability of CMOS circuits to draw low current from the power supplies in the quiescent state [l-61. Excessive current can be drawn by defective chips. IDDQ testing is particularly good at detecting defects due to gate oxide shorts and bridging defects. Many of these defects may not be detected with conventional voltage testing. IDDQ testing can also detect many of the defects caught or overlapped by conventional testing methods, which can be used to reduce the effort in the latter. A factor to consider is that parallel redundant devices introduced due to sizing requirements can lead to stuck-at untestables but not IDDQ untestables. I, testing requires that the circuit under test be fully static with no active DC paths while testing. The present IDDQ testing method stops the input clock to the chip and measures the current with the PMU. This is extremely expensive in test time limiting IDDQ testing to a few test points. For the Inte1386TM EX embedded processor, we have selected eight IDDQ test points providing an fault coverage of 71% and costing 18 ms in test time, ileak tool and tool set I, testing can be based on various fault models such as the pseudo stuck-at fault model, bridging fault model, leakage model, etc. [4-51. Internal tools based on the leakage model were available and recommended, so we proceeded with the tool set and models. LEAK is an internal CAD tool that selected eight vectors for IDDa testing out of a functional test suite of 2.2 million vectors. The tool is an IDD, fault evaluator based on the leakage fault model. The leakage fault model consists of six leakage faults per transistor as depicted in Fig. 1. The faults are gate-source (GS), source-drain (DS), source-bulk (SB), gate-bulk (GB), gate-drain (GD) and drain-bulk (DB). SB I GATE I BULK Figure 1. Transistor Leakage Faults DB 92 INTERNATIONAL TEST CONFERENCE $ IEEE

2 First, exhaustive simulations are performed at the switch level for all standard cells in the model. These simulations create leakage fault tables (LFT) which map Boolean input/output values of standard cells to leakages detected for that input/output combination inside the standard cell. The LFT s facilitate simulation at gate level inside ileak. The exact leakages detected inside the standard cells for a particular input/output value are determined from the LFT s. A flowchart depicting the entire IDDQ tool set flow is shown in Fig. 2. istag, FLED and ileak are the major tools in the IDDQ tool set. LOGIC I SIMULATION I I FAULTS w Figure 2. IDDQ tool set flow After these tables have been created, logic simulations are run on the model using functional vectors. Logic simulations were run on the Zycad hardware accelerator. The values at the inputs/outputs of all standard cells are stored in output record files. LEAK post processes these stored values and determines the leakage coverage at the end of a pre-determined clock cycle. Various selection modes were implemented in ileak to choose IDDQ test points based on the number of leakage faults detected. The useful modes are: Minimum Mode: In this mode, a vector is selected for IDDQ testing if it detects one new leakage fault. This mode can be used to determine the maximum IDDQ fault coverage for a test suite and is useful in down sizing the test suite. Percent Mode: A vector must detect at least n percent of the remaining faults to be selected by ileak. This is a useful mode for final vector selection. Pareto Mode : This mode provides an optimal vector set. All vectors are graded first and the vector providing the highest coverage is selected for IDDQ testing. Ths process is repeated until the desired coverage is obtained. The disadvantage of this mode is that it can take 5x the time as percent mode. Test Suite Reduction Significant hardware resource is required to run ileak on all functional tests in a large test suite at the full chip level. The output record files of the functional tests are also very large and time consuming to generate. Disk space and time constraints did not permit us to generate all output record files at the full chip level for the entire functional test suite. A novel hybrid methodology was used to reduce the Intel386 EX embedded processor functional test suite from 88 test patterns to 1 test patterns. The hybrid methodology consisted of two approaches: (1) fustileuk to reduce the peripheral test suite, and (2) Use of toggle information to reduce the core test suite. The test suite was first divided into peripheral, interperipheral and core tests. ileak was run in minimum mode for the peripheral and the inter-peripheral tests, seeding faults inside the modules. This methodology is called fustileuk. Test patterns which provided the highest IDDQ fault coverage were selected. This reduced the peripheral and inter-peripheral test suite from 3 functional tests to 6 tests for ID^, purposes. For the core tests, test patterns with high toggle coverage were chosen for ileak simulations. Logicsim with the ---togout option was run on each diag in the core test suite giving us an additional four diags. Experiments indicate that fustileuk is superior to using toggle information in test suite reduction. The above hybrid test suite reduction method prefers fastileak over toggle whenever possible. We used toggle information because we did not have enough disk space to save the large output record files for the core. Vector Selection We started with pareto mode to select IDDQ vectors. This was impractical with regards to time. ileak runs indicated that percent mode could provide coverage close to pareto mode while significantly reducing CPU time requirements. Variable percentages, selected on the basis of knowing the vector coverage from previous runs, were used in the percent mode to get an optimal IDDQ coverage. An example of the percentages that can 93

3 be used are shown in Table 1. The percentages used on the Intel386 EX chip correspond to an older revision of LEAK and hence are different form the ones shown below. We observed that the increase in coverage per vector was very small after we reached 71%. T Separate experiments indicated that a significant improvement in speed can be obtained by forcing LEAK to evaluate IDDQ coverage on every 5th vector instead of every vector, maintaining approximately the same coverage. Tal B 2. Resul Cycle factor IDDQ coverage time (secs) Table 2, row 2 shows reduction in CPU time by a factor of 5 without any impact, in this case, on the IDDQ fault coverage. The first row in the table indicates the CPU requirements if ileak selects on every vector in the diag. The second, third and fourth rows describe the ileak coverage and CPU runtime if LEAK selects on every 5th, 1 lth and 19th cycle. If a cycle factor of 5 is used the CPU requirement is reduced by 5. Adjacent vectors detecting similar faulte might account for the minimal impact on the IDDQ coverage. This method was not used on the Intel386 EX chip since assumptions had to be made and complete experimentation has not yet been performed. Tester Implementation Implementing the selected vectors was not a trivial task. The IDDO test should exercise the device to a known state, or until the selected IDDQ vector. At this point, the pattern must allow enough time to take a current measurement on the power supply. For this reason, we added three vectors that we looped on where the clocks were stopped, which was first hand modification to the pattern. The initial measurements showed current in the 1 s of ma range which was a problem. The device had some DC paths from pull up and pull down resistors on 44 pins. Some of these pins were in a logic state that activated the pullups/pulldowns and the fix was to temporarily drive the pin to the inactive state. Another problem was floating pins. Since the design used U pads for all pins, including pure output pins, a floating output left the IC input pin at VDd2 causing high currents. In this situation, the pins were driven to a known valid state. Also, with a high percentage of muxed pins with bi-directional pin functions, IO contention problems were verified not to exist. Once the pin configuration was corrected, the IDDQ current measurements were still in the ma range. Empty socket measurement showed the problem to be the capacitors on the loadboard. Table 3 shows the capacitor values initially used on the loadboard. The 1 uf capacitor was leaky and had to be replaced. Table 3. Loadboard Capacitance Capacitance(#) number However the decoupling capacitors did affect the IDDQ measurements. Table 4 gives the measurements with the additional capacitors. Tantalum capacitors proved more reliable than electrol$c capacitors. Also found was a direct relationship between the current level and the temperature. The current measurement at room temperature on the majority of the selected vectors was around 1-2 ua. This increased to 4-6 ua at hot temperature. The current limit was arbitrarily set to 9 ua. The last vector could be measured to a 6 ua limit averaging 3-4 ua. The cause of this high current limit was just recently found to be an active pull down on a single pin driving out a logic 1. Present I, limits are set to 2 ua now that typical IDDg current values are stabilized at 6-7 ua. 94

4 One solution to these problems is to separate the power supplied to the pads from the power supplied to the internal logic. The pull-up/pulldowns, and inputloutput contention problems can then be segregated. The tester hardware, however, did not have the design to support this solution, so the results of this method were not verified. The next revision of the hardware will take advantage of isolated power supplies in high volume manufacturing. Table 4 shows the increase in IDDq current with increased capacitance. We did not see a significant difference when we provided delays. I Table 4. Current Vs Capacitance I for seven vectors (a) Capacitance(uF) I Average IDDQ Current 1 I IDDQ min. % BF min% ~ 1 BF max% 5.5v,4.5v p-@ * ontinue Figure 3. Evaluation test program flow IDDQ Evaluation and Results An evaluation was performed using the selected IDDQ patterns and the Intel386 EX chip as the test vehicle to obtain information regarding IDDQ and defect detection. The evaluation was designed to determine: 1) to what degree IDDQ enhances fault coverage. 2) to what extent the IDDQ coverage overlaps the stuck-at coverage, and, 3) the most effective IDDQ vectors out of the seven generated from the methods described above. A statistically determined sample size of about 29, wafer level die were tested to groups of patterns or vectors that supply a minimum or maximum percent IDDQ and stuck-at coverage. Using wafer maps and test counters, we recorded whether a die fails IDDQ vectors representing minimum IDDQ coverage, maximum IDDQ coverage, both or none. The same information is recorded for minimum and maximum stuck-at coverage. See Fig. 3 for the evaluation test program flow. Stuck-at fault tests are designated as BF 5.5 and 4.5~. They are run at speed with loose timings. Fault grading and a project to increase fault coverage by writing test patterns was occurring at the time of the evaluation. All available stuck-at fault patterns that could be released to production were used in this evaluation. The stuck-at fault coverage for the full chip was 84.9% and used as the high percent or maximum coverage. Low percent or minimum coverage is 76.6%. Less than 5% of the nodes and input faults were excluded and coverage for minimum and maximum percent is unevenly distributed. Tests making up the minimum percent coverage are a subset of the maximum percent coverage. For this evaluation minimum percent IDDQ coverage is 27.9%, and maximum percent IDDQ coverage is 7.4%. IDDQ low coverage is a subset of high coverage. Results of the evaluation show that IDDQ does in fact enhance test quality. Of the approximately 29, units tested, about 1% fail for IDDQ. This is equivalent to 1, DPM (Defects Per Million), a significant number. However, keep in mind that data were taken at sort before any bum-in is done, and therefore, includes units that may fail &er bum-in testing. 95

5 There is a si@cant overlap of failures detected by stuck-at fault tests and ID, (Fig. 4 and 5). Figure 6 shows the overlap of IDw and other types of testing. In the figures. the chart category labeled All other failures. represent die failing any other test in the test flow such as opens or shorts. Comparison of lddq vs other Fai I u res IPD lddq 2% 1% Stuckqt 29% All Failures lddq Only 7 1, Stuckat 29% IDDQ and AC tests DC tests % 1% Stuck-at 11% All other failures 58% Figure 4. Distnbution of failures Stuck-at Failures IDDQ Stuck-at 5% ck-at 11% Stuck-at 68% Figure 5. Distribution of stuck-at fault and IDw failures Figure 6. Distribution of IDw and other types of testing In Fig. 6, IPD (powerdown current), is a production test impiemented to meet data sheet specifications of 1 ua. It is performed the same way an ID, test is performed. Power down is a test mode where the device is shut down and the clock diverted. Typical room temperature measurements are 6 to 7 ua. It is also implemented later in the test flow, and therefore, could not be included with the other IDDQ failures. Additionally, the data show that 4 82% of devices that fail both an IDDQ test and a stuckat fault test, fail both minimum and maximum percent coverage for stuck-at fault and ID, testing. 4 9% of the IDDQ failures were detected by vectors 1 or 2. Vectors 1 and 2 represent 42.5% ID^ coverage. Vector number 1 is included in a direct access test mode vector that tests the core of the Intel386 processor. Vector number 2 is part of a JTAG test. At least 58% of the tdm failures were caught by more than one vector. The minimum versus maximum portion of the evaluation did not clearly give the information we were seeking. It is obyious that the additional stuck-at coverage from 76.6% to 84.9% coverage is required to reduce outgoing DPM. The effectiveness of 1.4% IDm coverage over 27.9% IDDQ coverage so far appears to be minimal. However, certain tests seem to be SigrUScantly more effective at catching failures than others. *A small percentage of IDw failures overlap with ac timings tests or the DC tests ICC, IjD, uts, or leakage. 96

6 Comparison of I, coverage coverage and Stuck-at IDDQ testing offers great potential for reducing the effort required to fault grade stuck-at vectors. Without IDDQ testing, the chip fault grading effort may have required many more man years of effort to achieve comparable test coverage. Instead, IDDQ testing provided the additional coverage required for high product quality. If the relationship between them can be quantified early, IDDQ and stuck-at testing can be used to compliment each other in the fault grading process. Thereby, test methods can be targeted at specific areas or faults. In this way, IDDQ and stuck-at can be used for test coverage and reduce fault grading effort. Fault seeding offers great potential in striking a comparison between IDDQ and fault grading. An experiment was performed where we held a node at a certain state and later released it in the stim file. We did this for four separate random nodes in four different ileak runs. This had the effect of modeling a single stuck-at fault. LEAK was run with and without the above seeding. The results of comparing the stuck-at fault versus seeded LEAK, for the nodes that we seeded, was that LEAK detected the modeled fault where in some cases the fault was not caught in fault grading. In addition, the seeded fault toggled other nodes, increasing the coverage. This implies that using ileak fault seeding may be as good as single stuck-at fault grading. The effort to put the tools in place and complete the fault seeding comparison was significant and would not meet the project goals and schedules, so the following comparison method was developed. We developed a method to identlfy coverage distribution by particular test methods. Thus numerically identified the overlap and unique areas covered by these IDDQ and stuck-at testing during the fault grading process. The method was initially used for comparison on the Intel386 EX chip and was based upon two ideas: If 1% of leakage faults on a gate were detected, input stuck-at faults for the gate were detected. The IDDQ vector selection and grading tool provided the percentage of leakage faults per gate detected by each selected strobe point -- not comprehensive across strobe points. Using this comparison methodology, the test coverage on the Intel386 EX chip was effectively increased by 2-3%. Additional analysis performed on several blocks showed from 2% to 7% coverage overlap between IDDQ and stuck-at testing. This 2% to 7% coverage overlap is promising because it indicates substantial IDDQ and stuck-at fault overlap. Simply, a large amount of overlap gives a large target for either test method. This correlates well with the 68% overlap observed in the post-silicon results. Quantitative Fault Comparison After the initial fault comparison effort, the need for a quantitative method to compare IDDQ and stuck-at fault coverage was identifed. A better comparison method was justified by The Intel386 EX chip method was conservative and limited in the scope of the analysis performed The data indicate a large amount of fault overlap that was not utilized -- there was significant potential. Tool limitations prevented IDDQ fault information that was comprehensive across all selected strobe points. The Intel386 EX chip effort also indicated several appropriate goals for future comparison methodology The method must correspond well to observed failure data. Cumulative (across IDDQ strobe points) information should be used. The method should identlfy both overlapping and unique areas. Weighing these factors and other lessons from the initial fault grading effort reduction, a quantitative method for comparing stuck-at faults was devised. This method identifies a unique set of leakage faults needed to consider a stuck-at fault detected or well covered by IDDQ testing. This set of leakage faults is termed the needed set of leakages -- the leakages are needed to consider the corresponding stuck-at fault well covered by IDDQ testing. Using the needed leakage sets, it is possible to mark each stuck-at fault as detected or undetected by IDDQ. Once the IDDQ detection status of stuck-at faults is marked, the overlap between testing methods can be analyzed. This analysis will indicate those areas poorly covered by one test method, but well covered by the 97

7 other test method. In this way, the fault grading effort does not need to concentrate on areas (or even particular faults) covered by either test method. This can greatly reduce the number of difficult, impossible, and possible stuck-at faults that need to be researched and detected In order to identlfy all the needed leakage sets, a manner of associating leakage faults with stuck-at faults is required. A method, termed the path method (Fig. 7), was devised from the Intel386 EX chip experience. Any leakage fault along the path that information flows from gate input to gate output is said to be on the path of the corresponding gate input stuck-at fault. The leakage faults must have one terminal (end) connected to the path to be in the set of needed faults. The circuit shown below illustrates the needed faults for the path association method: 2 Input AND Gate stuck-at faults occurs). i.e. the scope of the analysis is limited. The path method limits fault comparison to gate input stuck-at faults. Results of a Quantitative Comparison The quantitative fault comparison methodology was implemented on another design, the Intel96JX. The stuck-at fault coverage was 92.5% without redundant faults included in the calculation. The stuck-at fault coverage was 57.3% with redundant faults included in the calculation. The transistor leakage fault coverage was 6.9% using seven strobe points. Fig. 8 details the fault coverage predicted by the comparison methodology described in this paper. Post-silicon failure distribution, (Fig. 9) shows good correlation to the prediction. An addtional3% of leakage fault coverage was used during testing but not used during the fault comparison analysis. This added IDDQ coverage may contribute to the slight difference between Figures 8 and 9. Path Method Coverage IDDQ 1%.-.- Stuckat 22% Path method of associating faults: all leakage faults with one terminal connected to this line must be detected for a stuck-at fault to be marked as detected. Figure 7. Path Method of Associating Stuck-at Faults Several points to note about the path method are The path method attempts to translate transistor level faults into logic level faults. i.e. the method requires detection of those leakage faults that can affect circuit functionality related to the stuck-at fault. The path method analyzes the needed leakage faults from a single gate (the gate on which the Stuckat 68% Figure 8. Path Method Coverage for lnte196jx Failure Distribution IDDQ 8% Stuckat 32% 6% Figure 9. Post-Silicon Failure Distribution for Inte196JX 98

8 Summary This paper describes the tool flow used by Intel386 EX chip to select IDDQ strobe points and implement them on the testers. The paper also demonstrates enhanced techniques for vector selection. The methodology for porting the vectors to the test floor was described. Design considerations such as separating the power supplied to the pads from the power supplied to the internal logic, testing hardware, test planning and testing methodologies should be pursued to make this a plug in type test. The advent of new technology will still have implementation problems if some of the above situations are not accounted for during the device and test hardware designs. Substantial speed-up in vector selection was obtained by using the flow described in this paper. Data collected by the evaluation and comparing the IDDQ coverage to stuck-at coverage allowed us to meet fault grading requirements for production. The ileak tool is being enhanced to automatically compare the detected leakage faults with categories of stuck-at faults. Acknowledgments The authors would like to acknowledge from Intel : Joe Hernandez, Terry Gillett, Wayne Needham, Tony Miller, Jim Missimer, Jim Williams, Glidden Martin. Steve Eastman of Sematech in Austin, Texas. References [l] Bakhle, A., Campbell, D., Cox, S., Emura, Y., Martin, G. IDDQ Test Technique, Intel Product Development Technology Summit, June, Available from the authors or Intel Library Information Services. [Z] Nucci, J. IDDQ, in Intel Test and Logic R & D report, Available from the authors or Intel Library Information Services. [3] Emura, Y. P9S IDDQ Testing, in Intel Technical Report, November, Available from the authors or Intel Library Information Services. [4] Mao, W., Gulati, R.K., Goel, D.K., Ciletti, M.D. QUIETEST: A Quiescent Current Testing Methodology for Detecting Leakage Faults, Proc. Int. conf. Comp.-Aided Design, pp , 199. [5] Maxwell, P.C., Aitken, R.C., Johansen, V., Chiang, I., The Effect of Different Test Sets on Quality Level Prediction: When is 8% Better Than 9%?, Proc. Int. Test Conf., pp , [6] Hawkins, C.F., Soden, J.M., Righter, A.W., Ferguson, F.J., Defect Classes - An Overdue Paradigm for CMOS IC Testing, Proc. Int. Test Conf., pp ,