32-Bit ARM Cortex FM0+ based Microcontroller

Transcription

1 32-Bit ARM Cortex FM0+ based Microcontroller The S6E1A1 Series is a series of highly integrated 32-bit microcontrollers designed for embedded controllers aiming at low power consumption and low cost. This series has the ARM Cortex-M0+ Processor with on-chip Flash memory and SRAM, and consists of peripheral functions such as various timers, ADCs and communication interfaces (UART, CSIO, I2C, LIN). The products which are described in this data sheet are placed into TYPE1-M0+ product categories in "FM0+ Family PERIPHERAL MANUAL". Features 32-bit ARM Cortex-M0+ Core Processor version: r0p1 Maximum operating frequency: 40 MHz Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 32 peripheral interrupt with 4 selectable interrupt priority levels 24-bit System timer (Sys Tick): System timer for OS task management Bit Band operation Compatible with Cortex-M3 bit band operation On-Chip Memories Flash memory Up to 88 Kbyte Read cycle:0 wait-cycle Security function for code protection SRAM The on-chip SRAM of this series has one independent SRAM. SRAM: 6 Kbyte Multi-function Serial Interface (Max 3channels) 128 bytes with FIFO in all channels (The number of FIFO steps varies depending on the settings of the communication mode or bit length.) The operation mode of each channel can be selected from one of the following. UART CSIO LIN I 2 C UART Full duplex double buffer Parity can be enabled or disabled. Built-in dedicated baud rate generator External clock available as a serial clock Various error detection functions (parity errors, framing errors, and overrun errors) CSIO Full duplex double buffer Built-in dedicated baud rate generator Overrun error detection function Serial chip select function (ch.1 and ch.3 only) Data length: 5 to 16 bits LIN LIN protocol Rev.2.1 supported Full duplex double buffer Master/Slave mode supported LIN break field generation function (The length is variable between 13 bits and 16 bits.) LIN break delimiter generation function (The length is variable between 1 bit and 4 bits.) Various error detection functions available (parity errors, framing errors, and overrun errors) I 2 C Standard-mode (Max: 100 kbps) supported / Fast-mode (Max 400kbps) supported. DMA Controller (2 channels) The DMA Controller has its own bus independent of the CPU, and CPU and DMA Controller can process simultaneously. 2 independently configurable and operable channels It can start a transfer with a software request or a request from a built-in peripheral. Transfer address area: 32 bits (4 Gbyte) Transfer mode: block transfer/burst transfer/demand transfer Transfer data type: byte/halfword/word Transfer block count: 1 to 16 Number of transfers: 1 to Cypress Semiconductor Corporation 198 Champion Court San Jose, CA Document Number: Rev.*A Revised February 10, 2016

2 A/D Converter (Max: 8 channels) 12-bit A/D Converter Successive approximation type Conversion time: V (S6E1A1xC0A) / 2.0 μs (S6E1A1xB0A) Priority conversion available (2 levels of priority) Scan conversion mode Built-in FIFO for conversion data storage (for scan conversion: 16 steps, for priority conversion: 4 steps) Base Timer (Max: 4 channels) The operation mode of each channel can be selected from one of the following. 16-bit PWM timer 16-bit PPG timer 16/32-bit reload timer 16/32-bit PWC timer General-purpose I/O Port This series can use its pin as a general-purpose I/O port when it is not used for an external bus or a peripheral function. All ports can be set to fast general-purpose I/O ports or slow general-purpose I/O ports. In addition, this series has a port relocate function that can set to which I/O port a peripheral function can be allocated. All ports are Fast GPIO which can be accessed by 1cycle Capable of controlling the pull-up of each pin Capable of reading pin level directly Port relocate function Up to 37 fast general-purpose I/O package Certain ports are 5 V tolerant. See "3. Pin Assignment" and "5. I/O Circuit Type" for details of such pins. Dual Timer (32/16-bit Down Counter) The Dual Timer consists of two programmable 32/16-bit down counters. The operation mode of each timer channel can be selected from one of the following. Free-running mode Periodic mode (= Reload mode) One-shot mode Quadrature Position/Revolution Counter (QPRC) The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position encoder. In addition, it can be used as an up/down counter. The detection edge for the three external event input pins AIN, BIN and ZIN is configurable. 16-bit position counter 16-bit revolution counter Two 16-bit compare registers Multi-function Timer The Multi-function Timer consists of the following blocks. 16-bit free-run timer 3 channels Input capture 4 channels Output compare 6 channels ADC start compare 6 channel Waveform generator 3 channels 16-bit PPG timer 3 channels IGBT mode is contained. The following function can be used to achieve the motor control. PWM signal output function DC chopper waveform output function Dead time function Input capture function ADC start function DTIF (motor emergency stop) interrupt function Real-time Clock (RTC) The Real-time Clock counts year/month/day/hour/minute/second/day of the week from year 01 to year 99. The RTC can generate an interrupt at a specific time (year/month/day/hour/minute/second/day of the week) and can also generate an interrupt in a specific year, in a specific month, on a specific day, at a specific hour or at a specific minute. It has a timer interrupt function generating an interrupt upon a specific time or at specific intervals. It can keep counting while rewriting the time. It can count leap years automatically. Document Number: Rev.*A Page 2 of 95

3 Watch Counter The Watch Counter wakes up the microcontroller from the low power consumption mode. The clock source can be selected from the main clock, the sub clock, the built-in high-speed CR clock or the built-in low-speed CR clock. Interval timer: up to 64 s (sub clock: khz) External Interrupt Controller Unit Up to 8 external interrupt input pins Non-maskable interrupt (NMI) input pin: 1 Watchdog Timer (2 channels) The watchdog timer generates an interrupt or a reset when the counter reaches a time-out value. This series consists of two different watchdogs, "hardware" watchdog and "software" watchdog. The "hardware" watchdog timer is clocked by the built-in low-speed CR oscillator. Therefore, the "hardware" watchdog is active in any low-power consumption modes except RTC mode and STOP mode. Clock and Reset Clocks A clock can be selected from five clock sources (two external oscillators, two built-in CR oscillator, and main PLL). Main clock : 4 MHz to 40MHz Sub clock : khz Built-in high-speed CR clock : 4 MHz Built-in low-speed CR clock : 100 khz Main PLL clock Resets Reset request from the INITX pin Power on reset Software reset Watchdog timer reset Low-voltage detection reset Clock supervisor reset Low-voltage Detector (LVD) This series monitors the voltage on the VCC pin with a 2-stage mechanism. When the voltage falls below a designated voltage, the Low-voltage Detector generates an interrupt or a reset. LVD1: error reporting via an interrupt LVD2: auto-reset operation Low Power Consumption Mode This series has four low power consumption modes. SLEEP TIMER RTC STOP Peripheral Clock Gating The system can reduce the current consumption of the total system with gating the operation clocks of peripheral functions not used. Debug Serial Wire Debug Port (SW-DP) Micro Trace Buffer (MTB) Unique ID A 41-bit unique value of the device has been set. Power Supply Wide voltage range: VCC = 2.7 V to 5.5 V Clock Supervisor (CSV) The Clock Supervisor monitors the failure of external clocks with a clock generated by a built-in CR oscillator. If an external clock failure (clock stop) is detected, a reset is asserted. If an external frequency anomaly is detected, an interrupt or a reset is asserted. Document Number: Rev.*A Page 3 of 95

4 Contents 1. Product Lineup Packages Pin Assignment Pin Descriptions I/O Circuit Type Handling Precautions Precautions for Product Design Precautions for Package Mounting Precautions for Use Environment Handling Devices Block Diagram Memory Size Memory Map Pin Status in Each CPU State Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions DC Characteristics Current Rating Pin Characteristics AC Characteristics Main Clock Input Characteristics Sub Clock Input Characteristics Built-in CR Oscillation Characteristics Operating Conditions of Main PLL (In the case of using the main clock as the input clock of the PLL) Operating Conditions of Main PLL (In the case of using the built-in high-speed CR clock as the input clock of the main PLL) Reset Input Characteristics Power-on Reset Timing Base Timer Input Timing CSIO Timing External Input Timing QPRC Timing I 2 C Timing SW-DP Timing bit A/D Converter Low-voltage Detection Characteristics Low-voltage Detection Reset Low-voltage Detection Interrupt Flash Memory Write/Erase Characteristics Return Time from Low-Power Consumption Mode Return Factor: Interrupt Return Factor: Reset Ordering Information Package Dimensions Major Changes Document Number: Rev.*A Page 4 of 95

5 1. Product Lineup Memory Size Product name S6E1A11B0A S6E1A11C0A On-chip Flash memory 56 Kbyte 88 Kbyte On-chip SRAM 6 Kbyte 6 Kbyte S6E1A12B0A S6E1A12C0A Function Product name S6E1A11B0A S6E1A12B0A Pin count 32 48/52 CPU Cortex-M0+ Frequency 40 MHz Power supply voltage range 2.7 V to 5.5 V DMAC 2 ch. Multi-function Serial Interface (UART/CSIO/I 2 C) Base Timer (PWC/Reload timer/pwm/ppg) A/D start compare 6 ch. 3 ch. (Max) ch.0/ch.1/ch.3: FIFO 4 ch. (Max) Input capture 4 ch. Multi-functio Free-run timer 3 ch. n 1 unit Timer Output compare 6 ch. Waveform 3 ch. generator PPG 3 ch. QPRC 1 ch. Dual Timer 1 unit Real-time Clock 1 unit Watch Counter 1 unit Watchdog timer 1 ch. (SW) + 1 ch. (HW) External Interrupt 8 pins (Max) + NMI 1 I/O port 23 pins (Max) 37 pins (Max) 12-bit A/D converter 5 ch. (1 unit) 8 ch. (1 unit) CSV (Clock Supervisor) Yes LVD (Low-voltage Detection) 2 ch. Built-in CR High-speed 4 MHz Low-speed 100 khz Debug Function SW-DP Unique ID Yes S6E1A11C0A S6E1A12C0A Note: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use the port relocate function of the I/O port according to your function use. See "14. ELECTRICAL CHARACTERISTICS 14.4 AC Characteristics Built-in CR Oscillation Characteristics" for accuracy of built-in CR. Document Number: Rev.*A Page 5 of 95

6 2. Packages Product name Package S6E1A11B0A S6E1A12B0A LQFP: FPT-32P-M30 (0.80 mm pitch) - QFN: LCC-32P-M73 (0.50 mm pitch) - LQFP: FPT-48P-M49 (0.50 mm pitch) - QFN: LCC-48P-M74 (0.50 mm pitch) - LQFP: FPT-52P-M02 (0.65 mm pitch) - : Supported S6E1A11C0A S6E1A12C0A Note: See "14. Package Dimensions" for detailed information on each package. Document Number: Rev.*A Page 6 of 95

7 VCC P46/X0A P47/X1A INITX PE0/ADTG_1/DTTI0X_1/INT02_2 MD0 PE2/X0 PE3/X VSS P60/SIN3_0/TIOA2_2/INT15_1/IC00_0/IGTRG0_0/SCS10_2 P61/SOT3_0/TIOB2_2/DTTI0X_2/SCS11_2 P0F/NMIX/SUBOUT_0/CROUT_1/RTCCO_0 P04/SCK3_0/INT03_2/TIOB0_1/IGTRG0_1 P03/SWDIO P01/SWCLK P21/SIN0_0/INT06_1/TIOB1_1/IC01_1/BIN0_1/FRCK0_0 S6E1A11B0A/C0A 3. Pin Assignment FPT-32P-M30 (TOP VIEW) P3A/RTO00_0/TIOA0_1/AIN0_3/SUBOUT_2/RTCCO_2/INT03_0/SCK0_ P22/AN07/SOT0_0/TIOB2_0/IC03_1/ZIN0_1/INT05_1 P3B/RTO01_0/TIOA1_1/BIN0_3/SOT0_2/INT04_0/SCS31_ P23/AN06/SCK0_0/TIOA2_0/IC02_1/AIN0_1/INT04_1 P3C/RTO02_0/TIOA2_1/ZIN0_3/SIN0_2/INT05_0/SCS30_ AVSS P3D/RTO03_0/TIOA3_1/INT06_0/AIN0_0/SCK3_ AVCC LQFP - 32 P3E/RTO04_0/TIOA0_0/BIN0_0/SOT3_2/INT15_ P13/AN03/SCK1_1/SUBOUT_1/IC01_2/RTCCO_1/INT00_1 P3F/RTO05_0/TIOA1_0/ZIN0_0/SIN3_ P12/AN02/SOT1_1/IC00_2/INT01_1 VSS 7 18 P11/AN01/SIN1_1/INT02_1/FRCK0_2/IC02_0 C 8 17 VSS Note: The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: Rev.*A Page 7 of 95

8 VCC P46/X0A P47/X1A INITX PE0/ADTG_1/DTTI0X_1/INT02_2 MD0 PE2/X0 PE3/X VSS P60/SIN3_0/TIOA2_2/INT15_1/IC00_0/IGTRG0_0/SCS10_2 P61/SOT3_0/TIOB2_2/DTTI0X_2/SCS11_2 P0F/NMIX/SUBOUT_0/CROUT_1/RTCCO_0 P04/SCK3_0/INT03_2/TIOB0_1/IGTRG0_1 P03/SWDIO P01/SWCLK P21/SIN0_0/INT06_1/TIOB1_1/IC01_1/BIN0_1/FRCK0_0 S6E1A11B0A/C0A LCC-32P-M73 (TOP VIEW) P3A/RTO00_0/TIOA0_1/AIN0_3/SUBOUT_2/RTCCO_2/INT03_0/SCK0_ P22/AN07/SOT0_0/TIOB2_0/IC03_1/ZIN0_1/INT05_1 P3B/RTO01_0/TIOA1_1/BIN0_3/SOT0_2/INT04_0/SCS31_ P23/AN06/SCK0_0/TIOA2_0/IC02_1/AIN0_1/INT04_1 P3C/RTO02_0/TIOA2_1/ZIN0_3/SIN0_2/INT05_0/SCS30_ AVSS QFN - 32 P3D/RTO03_0/TIOA3_1/INT06_0/AIN0_0/SCK3_ AVCC P3E/RTO04_0/TIOA0_0/BIN0_0/SOT3_2/INT15_ P13/AN03/SCK1_1/SUBOUT_1/IC01_2/RTCCO_1/INT00_1 P3F/RTO05_0/TIOA1_0/ZIN0_0/SIN3_ P12/AN02/SOT1_1/IC00_2/INT01_1 VSS 7 18 P11/AN01/SIN1_1/INT02_1/FRCK0_2/IC02_0 C 8 17 VSS Note: The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: Rev.*A Page 8 of 95

9 C VCC P46/X0A P47/X1A INITX P49/TIOB0_0 P4A/TIOB1_0 PE0/ADTG_1/DTTI0X_1/INT02_2 MD0 PE2/X0 PE3/X1 VSS VSS P82/SIN1_2 P81/SOT1_2 P80/SCK1_2/FRCK0_1 P60/SIN3_0/TIOA2_2/INT15_1/IC00_0/IGTRG0_0/SCS10_2 P61/SOT3_0/TIOB2_2/DTTI0X_2/SCS11_2 P0F/NMIX/SUBOUT_0/CROUT_1/RTCCO_0 P04/SCK3_0/INT03_2/TIOB0_1/IGTRG0_1 P03/SWDIO P02 P01/SWCLK P00 S6E1A11B0A/C0A FPT-48P-M49 (TOP VIEW) VCC 1 36 P21/SIN0_0/INT06_1/TIOB1_1/IC01_1/BIN0_1/FRCK0_0 P50/INT00_0/AIN0_2/SIN3_1/IC01_ P22/AN07/SOT0_0/TIOB2_0/IC03_1/ZIN0_1/INT05_1 P51/INT01_0/BIN0_2/SOT3_ P23/AN06/SCK0_0/TIOA2_0/IC02_1/AIN0_1/INT04_1 P52/INT02_0/ZIN0_2/SCK3_ AVSS P39/DTTI0X_0/ADTG_ AVRH LQFP - 48 P3A/RTO00_0/TIOA0_1/AIN0_3/SUBOUT_2/RTCCO_2/INT03_0/SCK0_ AVCC P3B/RTO01_0/TIOA1_1/BIN0_3/SOT0_2/INT04_0/SCS31_ P15/AN05/SOT0_1/SCS11_1/IC03_2/INT15_2 P3C/RTO02_0/TIOA2_1/ZIN0_3/SIN0_2/INT05_0/SCS30_ P14/AN04/SIN0_1/SCS10_1/INT03_1/IC02_2 P3D/RTO03_0/TIOA3_1/INT06_0/AIN0_0/SCK3_ P13/AN03/SCK1_1/SUBOUT_1/IC01_2/RTCCO_1/INT00_1 P3E/RTO04_0/TIOA0_0/BIN0_0/SOT3_2/INT15_ P12/AN02/SOT1_1/IC00_2/INT01_1 P3F/RTO05_0/TIOA1_0/ZIN0_0/SIN3_ P11/AN01/SIN1_1/INT02_1/FRCK0_2/IC02_0 VSS P10/AN00 Note: The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: Rev.*A Page 9 of 95

10 P4A/TIOB1_0 PE0/ADTG_1/DTTI0X_1/INT02_2 C VCC P46/X0A P47/X1A INITX P49/TIOB0_0 MD0 PE2/X0 PE3/X1 VSS VSS P82/SIN1_2 P81/SOT1_2 P80/SCK1_2/FRCK0_1 P60/SIN3_0/TIOA2_2/INT15_1/IC00_0/IGTRG0_0/SCS10_2 P61/SOT3_0/TIOB2_2/DTTI0X_2/SCS11_2 P0F/NMIX/SUBOUT_0/CROUT_1/RTCCO_0 P04/SCK3_0/INT03_2/TIOB0_1/IGTRG0_1 P03/SWDIO P02 P01/SWCLK P00 S6E1A11B0A/C0A LCC-48P-M74 (TOP VIEW) VCC 1 36 P21/SIN0_0/INT06_1/TIOB1_1/IC01_1/BIN0_1/FRCK0_0 P50/INT00_0/AIN0_2/SIN3_1/IC01_ P22/AN07/SOT0_0/TIOB2_0/IC03_1/ZIN0_1/INT05_1 P51/INT01_0/BIN0_2/SOT3_ P23/AN06/SCK0_0/TIOA2_0/IC02_1/AIN0_1/INT04_1 P52/INT02_0/ZIN0_2/SCK3_ AVSS P39/DTTI0X_0/ADTG_ AVRH QFN- 48 P3A/RTO00_0/TIOA0_1/AIN0_3/SUBOUT_2/RTCCO_2/INT03_0/SCK0_ AVCC P3B/RTO01_0/TIOA1_1/BIN0_3/SOT0_2/INT04_0/SCS31_ P15/AN05/SOT0_1/SCS11_1/IC03_2/INT15_2 P3C/RTO02_0/TIOA2_1/ZIN0_3/SIN0_2/INT05_0/SCS30_ P14/AN04/SIN0_1/SCS10_1/INT03_1/IC02_2 P3D/RTO03_0/TIOA3_1/INT06_0/AIN0_0/SCK3_ P13/AN03/SCK1_1/SUBOUT_1/IC01_2/RTCCO_1/INT00_1 P3E/RTO04_0/TIOA0_0/BIN0_0/SOT3_2/INT15_ P12/AN02/SOT1_1/IC00_2/INT01_1 P3F/RTO05_0/TIOA1_0/ZIN0_0/SIN3_ P11/AN01/SIN1_1/INT02_1/FRCK0_2/IC02_0 VSS P10/AN00 Note: The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: Rev.*A Page 10 of 95

11 P47/X1A INITX P49/TIOB0_0 P4A/TIOB1_0 NC PE0/ADTG_1/DTTI0X_1/INT02_2 C VCC P46/X0A MD0 PE2/X0 PE3/X1 VSS VSS P82/SIN1_2 P81/SOT1_2 P80/SCK1_2/FRCK0_1 P60/SIN3_0/TIOA2_2/INT15_1/IC00_0/IGTRG0_0/SCS10_2 P61/SOT3_0/TIOB2_2/DTTI0X_2/SCS11_2 P0F/NMIX/SUBOUT_0/CROUT_1/RTCCO_0 P04/SCK3_0/INT03_2/TIOB0_1/IGTRG0_1 P03/SWDIO P02 P01/SWCLK P00 NC S6E1A11B0A/C0A FPT-52P-M02 (TOP VIEW) VCC 1 39 P21/SIN0_0/INT06_1/TIOB1_1/IC01_1/BIN0_1/FRCK0_0 P50/INT00_0/AIN0_2/SIN3_1/IC01_ P22/AN07/SOT0_0/TIOB2_0/IC03_1/ZIN0_1/INT05_1 P51/INT01_0/BIN0_2/SOT3_ P23/AN06/SCK0_0/TIOA2_0/IC02_1/AIN0_1/INT04_1 P52/INT02_0/ZIN0_2/SCK3_ NC NC 5 35 AVSS P39/DTTI0X_0/ADTG_ AVRH LQFP - 52 P3A/RTO00_0/TIOA0_1/AIN0_3/SUBOUT_2/RTCCO_2/INT03_0/SCK0_ AVCC P3B/RTO01_0/TIOA1_1/BIN0_3/SOT0_2/INT04_0/SCS31_ P15/AN05/SOT0_1/SCS11_1/IC03_2/INT15_2 P3C/RTO02_0/TIOA2_1/ZIN0_3/SIN0_2/INT05_0/SCS30_ P14/AN04/SIN0_1/SCS10_1/INT03_1/IC02_2 P3D/RTO03_0/TIOA3_1/INT06_0/AIN0_0/SCK3_ P13/AN03/SCK1_1/SUBOUT_1/IC01_2/RTCCO_1/INT00_1 P3E/RTO04_0/TIOA0_0/BIN0_0/SOT3_2/INT15_ P12/AN02/SOT1_1/IC00_2/INT01_1 P3F/RTO05_0/TIOA1_0/ZIN0_0/SIN3_ P11/AN01/SIN1_1/INT02_1/FRCK0_2/IC02_0 VSS P10/AN00 Note: The number after the underscore ("_") in a pin name such as XXX_1 and XXX_2 indicates the relocated port number. The channel on such pin has multiple functions, each of which has its own pin name. Use the Extended Port Function Register (EPFR) to select the pin to be used. Document Number: Rev.*A Page 11 of 95

12 4. Pin Descriptions List of Pin Functions The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. LQFP-52 Pin no. LQFP-48 QFN-48 LQFP-32 QFN VCC P50 INT00_0 AIN0_2 SIN3_1 IC01_0 P51 INT01_0 BIN0_2 SOT3_1 P52 INT02_0 ZIN0_2 SCK3_1 P39 DTTI0X_0 ADTG_2 P3A RTO00_0 TIOA0_1 AIN0_3 SUBOUT_2 RTCCO_2 INT03_0 SCK0_2 P3B RTO01_0 TIOA1_1 BIN0_3 SOT0_2 INT04_0 SCS31_2 Pin name I/O circuit type Pin state type I* J I* J I* J E F F I J J Document Number: Rev.*A Page 12 of 95

13 LQFP-52 Pin no. LQFP-48 QFN LQFP-32 QFN-32 P3C RTO02_0 TIOA2_1 ZIN0_3 SIN0_2 INT05_0 SCS30_2 P3D RTO03_0 TIOA3_1 INT06_0 AIN0_0 SCK3_2 P3E RTO04_0 TIOA0_0 BIN0_0 SOT3_2 INT15_0 P3F RTO05_0 TIOA1_0 ZIN0_0 SIN3_ VSS C VCC Pin name I/O circuit type Pin state type INITX B C P46 X0A P47 X1A P49 TIOB0_0 P4A TIOB1_0 F F F F D D E E J J J I E F I I Document Number: Rev.*A Page 13 of 95

14 LQFP-52 Pin no. LQFP-48 QFN-48 LQFP-32 QFN-32 Pin name I/O circuit type Pin state type PE ADTG_1 DTTI0X_1 INT02_2 C J MD0 J D PE X0 A A PE X1 A B VSS - P AN00 G K P AN01 SIN1_1 INT02_1 FRCK0_2 IC02_0 H* L P AN02 SOT1_1 IC00_2 INT01_1 H* L P AN03 SCK1_1 SUBOUT_1 IC01_2 RTCCO_1 INT00_1 H* L P AN04 SIN0_1 SCS10_1 INT03_1 H* L IC02_2 Document Number: Rev.*A Page 14 of 95

15 Pin no. LQFP-52 LQFP-48 QFN-48 LQFP-32 QFN-32 Pin name I/O circuit type Pin state type P AN05 SOT0_1 SCS11_1 IC03_2 INT15_2 H* L AVCC AVRH AVSS - P AN06 SCK0_0 TIOA2_0 IC02_1 AIN0_1 INT04_1 G L P AN07 SOT0_0 TIOB2_0 IC03_1 ZIN0_1 INT05_1 G L P SIN0_0 INT06_1 TIOB1_1 IC01_1 BIN0_1 FRCK0_0 E J P00 E I P SWCLK E H P02 E I P SWDIO E H Document Number: Rev.*A Page 15 of 95

16 LQFP-52 Pin no. LQFP-48 QFN LQFP-32 QFN-32 P04 SCK3_0 INT03_2 TIOB0_1 IGTRG0_1 P0F NMIX SUBOUT_0 CROUT_1 RTCCO_0 P61 SOT3_0 TIOB2_2 DTTI0X_2 SCS11_2 P60 SIN3_0 TIOA2_2 INT15_1 IC00_0 IGTRG0_0 SCS10_2 P80 SCK1_2 FRCK0_1 P81 SOT1_2 P82 SIN1_ VSS - 5,21,36, NC - *:5V tolerant I/O Pin name I/O circuit type Pin state type I* J E I* I I* J K K K G I I I Document Number: Rev.*A Page 16 of 95

17 List of pin functions The number after the underscore ("_") in a pin name such as XXX_1 and XXX_2 indicates the relocated port number. The channel on such pin has multiple functions, each of which has its own pin name. Use the Extended Port Function Register (EPFR) to select the pin to be used. Pin function ADC Base Timer 0 Base Timer 1 Base Timer 2 Base Timer 3 Debugger Pin name Function description LQFP-52 Pin no. LQFP-48 QFN-48 ADTG_1 A/D converter external trigger ADTG_2 input pin AN AN AN AN03 A/D converter analog input pin AN04 ANxx describes ADC ch.xx AN AN AN TIOA0_ Base timer ch.0 TIOA pin TIOA0_ TIOB0_ Base timer ch.0 TIOB pin TIOB0_ TIOA1_ Base timer ch.1 TIOA pin TIOA1_ TIOB1_ Base timer ch.1 TIOB pin TIOB1_ TIOA2_ TIOA2_1 Base timer ch.2 TIOA pin TIOA2_ TIOB2_ Base timer ch.2 TIOB pin TIOB2_ TIOA3_1 Base timer ch.3 TIOA pin SWCLK Serial wire debug interface clock input pin SWDIO Serial wire debug interface data input / output pin LQFP-32 QFN-32 Document Number: Rev.*A Page 17 of 95

18 Pin function External Interrupt Pin name Function description LQFP-52 Pin no. LQFP-48 QFN-48 INT00_ External interrupt request 00 input pin INT00_ INT01_ External interrupt request 01 input pin INT01_ INT02_ INT02_1 External interrupt request 02 input pin INT02_ INT03_ INT03_1 External interrupt request 03 input pin INT03_ INT04_ External interrupt request 04 input pin INT04_ INT05_ External interrupt request 05 input pin INT05_ INT06_ External interrupt request 06 input pin INT06_ INT15_ INT15_1 External interrupt request 15 input pin INT15_ NMIX Non-Maskable Interrupt input pin LQFP-32 QFN-32 Document Number: Rev.*A Page 18 of 95

19 Pin function GPIO GPIO P00 Pin name Function description LQFP-52 Pin no. LQFP-48 QFN P P General-purpose I/O port 0 P P P0F P P P General-purpose I/O port 1 P P P P P22 General-purpose I/O port P P P3A P3B P3C General-purpose I/O port P3D P3E P3F P P General-purpose I/O port 4 P P4A P P51 General-purpose I/O port P P General-purpose I/O port 6 P P P81 General-purpose I/O port P PE0* PE2 General-purpose I/O port E PE LQFP-32 QFN-32 Document Number: Rev.*A Page 19 of 95

20 Pin function Multi-functio n Serial 0 Multi-functio n Serial 1 Multifunction Serial 3 Pin name Function description LQFP-52 Pin no. LQFP-48 QFN-48 SIN0_ SIN0_1 Multi-function serial interface ch.0 input pin SIN0_ SOT0_0 (SDA0_0) SOT0_1 (SDA0_1) SOT0_2 (SDA0_2) SCK0_0 (SCL0_0) SCK0_2 (SCL0_2) Multi-function serial interface ch.0 output pin. This pin operates as SOT0 when used as a UART/CSIO/LIN pin (operation mode 0 to 3) and as SDA0 when used as an I 2 C pin (operation mode 4). Multi-function serial interface ch.0 clock I/O pin. This pin operates as SCK0 when used as a CSIO pin (operation mode 2) and as SCL0 when used as an I 2 C pin (operation mode 4) SIN1_1 Multi-function serial interface ch.1 input SIN1_2 pin SOT1_1 (SDA1_1) SOT1_2 (SDA1_2) SCK1_1 (SCL1_1) SCK1_2 (SCL1_2) Multi-function serial interface ch.1 output pin. This pin operates as SOT1 when used as a UART/CSIO/LIN pin (operation mode 0 to 3) and as SDA1 when used as an I 2 C pin (operation mode 4). Multi-function serial interface ch.1 clock I/O pin. This pin operates as SCK1 when used as a CSIO pin (operation mode 2) and as SCL1 when used as an I 2 C pin (operation mode 4) SCS10_1 Multi-function serial interface ch.1 serial SCS10_2 chip select 0 output/input pin SCS11_1 Multi-function serial interface ch.1 serial SCS11_2 chip select 1 output pin SIN3_ SIN3_1 Multi-function serial interface ch.3 input pin SIN3_ SOT3_0 (SDA3_0) SOT3_1 (SDA3_1) SOT3_2 (SDA3_2) SCK3_0 (SCL3_0) SCK3_1 (SCL3_1) SCK3_2 (SCL3_2) SCS30_2 SCS31_2 Multi-function serial interface ch.3 output pin. This pin operates as SOT3 when used as a UART/CSIO/LIN pin (operation mode 0 to 3) and as SDA3 when used as an I 2 C pin (operation mode 4). Multi-function serial interface ch.3 clock I/O pin. This pin operates as SCK3 when used as a CSIO (operation mode 2) and as SCL3 when used as an I 2 C pin (operation mode 4). Multi-function serial interface ch.3 serial chip select 0 input/output pin. Multi-function serial interface ch.3 serial chip select 1 output pin LQFP-32 QFN-32 Document Number: Rev.*A Page 20 of 95

21 Pin function Multi-functio n Timer 0 Pin name Function description LQFP-52 Pin no. LQFP-48 QFN-48 DTTI0X_0 Input signal of waveform generator DTTI0X_1 controlling RTO00 to RTO05 outputs of DTTI0X_2 Multi-function Timer FRCK0_ FRCK0_1 16-bit free-run timer ch.0 external clock input pin FRCK0_ IC00_ IC00_ IC01_ IC01_ IC01_2 16-bit input capture input pin of Multi-function timer 0. IC02_0 ICxx describes channel number IC02_ IC02_ IC03_ IC03_ RTO00_0 (PPG00_0) RTO01_0 (PPG00_0) RTO02_0 (PPG02_0) RTO03_0 (PPG02_0) RTO04_0 (PPG04_0) RTO05_0 (PPG04_0) Waveform generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output mode. Waveform generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output mode. Waveform generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output mode. Waveform generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output mode. Waveform generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output mode. Waveform generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output mode IGTRG0_ PPG IGBT mode external trigger input pin IGTRG0_ LQFP-32 QFN-32 Document Number: Rev.*A Page 21 of 95

22 Pin function Quadrature Position/ Revolution Counter Real-time clock RESET Mode POWER GND CLOCK Pin name AIN0_0 Function description LQFP-52 Pin no. LQFP-48 QFN AIN0_ QPRC ch.0 AIN input pin AIN0_ AIN0_ BIN0_ BIN0_ QPRC ch.0 BIN input pin BIN0_ BIN0_ ZIN0_ ZIN0_ QPRC ch.0 ZIN input pin ZIN0_ ZIN0_ RTCCO_ RTCCO_1 0.5-seconds pulse output pin of Real-time clock RTCCO_ SUBOUT_ SUBOUT_1 Sub clock output pin SUBOUT_ INITX MD0 External Reset Input pin. A reset is valid when INITX="L". Mode 0 pin. During normal operation, input MD0="L". During serial programming to Flash memory, input MD0="H" VCC Power supply pin VCC Power supply pin VSS GND pin VSS GND pin VSS GND pin X0 Main clock (oscillation) input pin X0A Sub clock (oscillation) input pin X1 Main clock (oscillation) I/O pin X1A Sub clock (oscillation) I/O pin CROUT_1 Built-in high-speed CR oscillation clock output port AVCC A/D converter analog power supply pin Analog POWER A/D converter analog reference voltage AVRH input pin Analog A/D converter analog reference voltage AVSS GND input pin Power supply stabilization capacitance C pin C pin *: PE0 is an open drain pin, cannot output high. LQFP-32 QFN-32 Document Number: Rev.*A Page 22 of 95

23 5. I/O Circuit Type Type Circuit Remarks X1 P-ch P-ch Digital output R N-ch Digital output A Pull-up resistor control Digital input Standby mode control Clock input Standby mode control Digital input Standby mode control It is possible to select the main oscillation / GPIO function When the main oscillation is selected. Oscillation feedback resistor : Approximately 1MΩ With standby mode control When the GPIO is selected. CMOS level output. CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50kΩ I OH = -4mA, I OL = 4mA R X0 P-ch P-ch Digital output N-ch Digital output Pull-up resistor control B Pull-up resistor Digital input CMOS level hysteresis input Pull-up resistor : Approximately 50kΩ Document Number: Rev.*A Page 23 of 95

24 Type Circuit Remarks Digital input C N-ch Digital output Open drain output CMOS level hysteresis input X1A P-ch P-ch Digital output R N-ch Digital output D Pull-up resistor control Digital input Standby mode control Clock input Standby mode control Digital input Standby mode control It is possible to select the sub oscillation / GPIO function When the sub oscillation is selected. Oscillation feedback resistor : Approximately 5MΩ With standby mode control When the GPIO is selected. CMOS level output. CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50kΩ I OH = -4mA, I OL = 4mA R X0A P-ch P-ch Digital output N-ch Digital output Pull-up resistor control Document Number: Rev.*A Page 24 of 95

25 Type Circuit Remarks E R P-ch P-ch N-ch Digital output Digital output Pull-up resistor control CMOS level output CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50kΩ I OH = -4mA, I OL = 4mA When this pin is used as an I 2 C pin, the digital output P-ch transistor is always off Digital input Standby mode control F R P-ch P-ch N-ch Digital output Digital output CMOS level output CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50kΩ I OH = -12mA, I OL = 12mA When this pin is used as an I 2 C pin, the digital output P-ch transistor is always off Pull-up resistor control Digital input Standby mode control Document Number: Rev.*A Page 25 of 95

26 Type Circuit Remarks P-ch P-ch Digital output G R N-ch Digital output Pull-up resistor control Digital input Standby mode control CMOS level output CMOS level hysteresis input With input control Analog input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50kΩ I OH = -4mA, I OL = 4mA When this pin is used as an I 2 C pin, the digital output P-ch transistor is always off Analog input Input control H P-ch R P-ch N-ch Digital output Digital output Pull-up resistor control Digital input Standby mode control CMOS level output CMOS level hysteresis input With input control Analog input 5V tolerant With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50kΩ I OH = -4mA, I OL = 4mA Available to control of PZR registers. When this pin is used as an I 2 C pin, the digital output P-ch transistor is always off Analog input Input control Document Number: Rev.*A Page 26 of 95

27 Type Circuit Remarks I R P-ch P-ch N-ch Digital output Digital output Pull-up resistor control CMOS level output CMOS level hysteresis input 5V tolerant With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50kΩ I OH = -4mA, I OL = 4mA Available to control PZR registers When this pin is used as an I 2 C pin, the digital output P-ch transistor is always off Digital input Standby mode control J Mode input CMOS level hysteresis input P-ch Digital output K R N-ch Digital output CMOS level output CMOS level hysteresis input With standby mode control I OH = -4mA, I OL = 4mA When this pin is used as an I 2 C pin, the digital output P-ch transistor is always off Digital input Standby mode control Document Number: Rev.*A Page 27 of 95

28 6. Handling Precautions Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices. 6.1 Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices. Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. 1. Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. 2. Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. 3. Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin. Code: DS Ea Document Number: Rev.*A Page 28 of 95

29 Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred ma to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: 1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. 2. Be sure that abnormal current flows do not occur during the power-on sequence. Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Precautions Related to Usage of Devices Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 6.2 Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Cypress's recommended conditions. For detailed information about mount conditions, contact your sales representative. Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended conditions. Document Number: Rev.*A Page 29 of 95

30 Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: 1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. 2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5 C and 30 C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. 3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. 4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust. Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended conditions for baking. Condition: 125 C/24 h Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: 1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. 2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. 3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. 4. Ground all fixtures and instruments, or protect with anti-static measures. 5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies. Document Number: Rev.*A Page 30 of 95

31 6.3 Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: 1. Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. 2. Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. 3. Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. 4. Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. 5. Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Cypress products in other special environmental conditions should consult with sales representatives. Document Number: Rev.*A Page 31 of 95

32 7. Handling Devices Power Supply Pins In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with each POWER pins and GND pins of this device at low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µf be connected as a bypass capacitor between VCC and VSS, between AVCC and AVSS and between AVRH and AVRL near this device. A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed operating range of the VCC power supply voltage. As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient fluctuation rate does not exceed 0.1 V/μs at a momentary fluctuation such as switching the power supply. Crystal Oscillator Circuit Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1, X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by ground plane as this is expected to produce stable operation. Evaluate oscillation of your using crystal oscillator by your mount board. Sub Crystal Oscillator This series sub oscillator circuit is low gain to keep the low current consumption. The crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation. Surface mount type Size: Load capacitance: Load capacitance: Lead type Load capacitance: Load capacitance: More than 3.2 mm 1.5 mm Approximately 6 pf to 7 pf When the Standard setting (CCS/CCB= ) Approximately 4 pf to 7 pf When the low power setting (CCS/CCB= ) Approximately 6 pf to 7 pf When the Standard setting (CCS/CCB= ) Approximately 4 pf to 7 pf When the low power setting (CCS/CCB= ) Document Number: Rev.*A Page 32 of 95

33 Using an External Clock When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1(PE3) can be used as a general-purpose I/O port. Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input, and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port. Example of Using an External Clock Device Can be used as general-purpose I/O ports. X0(X0A) X1(PE3), X1A (P47) Set as External clock input Handling when Using Multi-Function Serial Pin as I 2 C Pin If it is using the multi-function serial pin as I 2 C pins, P-ch transistor of digital output is always disabled. However, I 2 C pins need to keep the electrical characteristic like other pins and not to connect to the external I 2 C bus system with power OFF. C Pin This series contains the regulator. Be sure to connect a smoothing capacitor (C S ) for the regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. A smoothing capacitor of about 4.7 μf would be recommended for this series. Device C VSS C S GND Mode Pins (MD0) Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is because of preventing the device erroneously switching to test mode due to noise. Document Number: Rev.*A Page 33 of 95

34 Notes on Power-on Turn power on/off in the following order or at the same time. Turning on : VBAT VCC VCC AVCC AVRH Turning off : VCC VBAT AVRH AVCC VCC Serial Communication There is a possibility to receive wrong data due to the noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. If an error is detected, retransmit the data. Differences in Features among the Products with Different Memory Sizes and between Flash Products and MASK Products The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between Flash products and MASK products are different because chip layout and memory structures are different. If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics. Pull-Up Function of 5V Tolerant I/O Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5V tolerant I/O. Document Number: Rev.*A Page 34 of 95

35 AHB-APB Bridge : APB1 (Max 40MHz) AHB-AHB Bridge AHB-APB Bridge: APB0(Max 40MHz) Multi-layer AHB (Max 40MHz) S6E1A11B0A/C0A 8. Block Diagram S6E1A11/S6E1A12 To PIN-Function-Ctrl SWCLK, SWDIO SW-DP Cortex-M0+ NVIC Bit Band Wrapper Fast GPIO MTB On-Chip SRAM 6 Kbyte System ROM table Dual-Timer Flash I/F Security On-Chip Flash 56 Kbyte/ 88 Kbyte WatchDog Timer (Software) INITX Clock Reset Generator WatchDog Timer (Hardware) CSV DMAC 2ch. CLK X0 X1 X0A X1A Main Osc Sub Osc PLL CR 4MHz Source Clock CR 100kHz CROUT AVCC, AVSS AVRH (only 48/52pin PKG) ANxx ADTG 12-bit A/D Converter Unit 0 LVD Ctrl Power-On Reset LVD TIOAx TIOBx Base Timer 16-bit 4ch./ 32-bit 2ch. IRQ-Monitor Watch Counter Regulator C AINx BINx ZINx IC0x FRCKx DTTI0X RTO0x QPRC 1ch. A/D Activation Compare 6ch. 16-bit Input Capture 4ch. 16-bit Free-run Timer 3ch. 16-bit Output Compare 6ch. Waveform Generator 3ch. Real-Time Clock External Interrupt Controller 8pin + NMI MODE-Ctrl Low-speed CR Prescaler Peripheral Clock Gating GPIO To Fast GPIO PIN-Function-Ctrl RTCCO, SUBOUT INTx NMIX MD0 P0x, P1x,... Pxx IGTRGx 16-bit PPG 3ch. Multi-function Timer Multi-function Serial I/F 3ch. (with FIFO) SCKx SINx SOTx SCSx Document Number: Rev.*A Page 35 of 95

36 9. Memory Size See Memory size in 1. Product Lineup to confirm the memory size. 10. Memory Map Memory Map (1) 0x41FF_FFFF Peripheral area See " Memory Memory map map(2)" (2) for for the memory size details. 0xFFFF_FFFF 0xF802_0000 0xF800_0000 0xF000_3000 0xF000_2000 0xF000_1000 0xF000_0000 0xE000_0000 0x4400_0000 0x4200_0000 0x4000_0000 0x2400_0000 0x2200_0000 0x2008_0000 0x2000_0000 0x0010_0008 0x0010_0004 0x0010_0000 Reserved Fast GPIO (Single-cycle I/O port) Reserved ROM table MTB_DWT MTB registers(sfr) Cortex-M0+ Private Peripherals Reserved 32 Mbytes Bit Band alias Peripherals Reserved 32 Mbytes Bit Band alias Reserved SRAM Reserved CR Trim Security Flash 0x4006_1000 0x4006_0000 0x4003_C800 0x4003_C100 0x4003_C000 0x4003_B000 0x4003_A000 0x4003_9000 0x4003_8000 0x4003_5100 0x4003_5000 0x4003_4000 0x4003_3000 0x4003_2000 0x4003_1000 0x4003_0000 0x4002_F000 0x4002_E000 0x4002_8000 0x4002_7000 0x4002_6000 0x4002_5000 0x4002_4000 0x4002_1000 0x4002_0000 0x4001_6000 0x4001_5000 0x4001_3000 0x4001_2000 0x4001_1000 0x4001_0000 Reserved DMAC Reserved Peripheral Clock Gating Low Speed CR Prescaler RTC Watch Counter Reserved MFS Reserved LVD Reserved GPIO Reserved INT-Req READ EXTI Reserved CR Trim Reserved A/DC QPRC Base Timer PPG Reserved MFT unit 0 Reserved Dual Timer Reserved SW WDT HW WDT Clock/Reset 0x0000_0000 Reserved 0x4000_1000 0x4000_0000 Flash I/F Document Number: Rev.*A Page 36 of 95

37 Memory Map(2) S6E1A12B0A S6E1A12C0A S6E1A11B0A S6E1A11C0A 0x2008_0000 0x2008_0000 Reserved Reserved 0x2000_1800 0x2000_1800 0x2000_0000 SRAM 6K bytes 0x2000_0000 SRAM 6K bytes Reserved Reserved 0x0010_0004 CR trimming 0x0010_0004 CR trimming 0x0010_0000 Security 0x0010_0000 Security Reserved Reserved 0x0001_6000 Flash 88K bytes * 0x0000_E000 Flash 56Kbytes * 0x0000_0000 0x0000_0000 Document Number: Rev.*A Page 37 of 95

38 Peripheral Address Map Start address End address Bus Peripheral 0x4000_0000 0x4000_0FFF Flash memory I/F register AHB 0x4000_1000 0x4000_FFFF Reserved 0x4001_0000 0x4001_0FFF Clock/Reset Control 0x4001_1000 0x4001_1FFF Hardware Watchdog Timer 0x4001_2000 0x4001_2FFF Software Watchdog Timer APB0 0x4001_3000 0x4001_4FFF Reserved 0x4001_5000 0x4001_5FFF Dual-Timer 0x4001_6000 0x4001_FFFF Reserved 0x4002_0000 0x4002_0FFF Multi-function Timer unit0 0x4002_1000 0x4002_3FFF Reserved 0x4002_4000 0x4002_4FFF PPG 0x4002_5000 0x4002_5FFF Base Timer 0x4002_6000 0x4002_6FFF Quadrature Position/Revolution Counter 0x4002_7000 0x4002_7FFF A/D Converter 0x4002_8000 0x4002_DFFF Reserved 0x4002_E000 0x4002_EFFF Built-in CR trimming 0x4002_F000 0x4002_FFFF Reserved 0x4003_0000 0x4003_0FFF External Interrupt Controller 0x4003_1000 0x4003_1FFF Interrupt Request Batch-Read Function 0x4003_2000 0x4003_2FFF APB1 Reserved 0x4003_3000 0x4003_3FFF GPIO 0x4003_4000 0x4003_4FFF Reserved 0x4003_5000 0x4003_57FF Low-Voltage Detection 0x4003_5800 0x4003_7FFF Reserved 0x4003_8000 0x4003_8FFF Multi-function Serial Interface 0x4003_9000 0x4003_9FFF Reserved 0x4003_A000 0x4003_AFFF Watch Counter 0x4003_B000 0x4003_BFFF Real-time clock 0x4003_C000 0x4003_C0FF Low-speed CR Prescaler 0x4003_C100 0x4003_C7FF Peripheral Clock Gating 0x4003_C800 0x4003_FFFF Reserved 0x4004_0000 0x4005_FFFF Reserved 0x4006_0000 0x4006_0FFF AHB DMAC register 0x4006_1000 0x41FF_FFFF Reserved Document Number: Rev.*A Page 38 of 95

39 11. Pin Status in Each CPU State The terms used for pin status have the following meanings. INITX=0 INITX=1 SPL=0 SPL=1 This is the period when the INITX pin is the L level. This is the period when the INITX pin is the H level. This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 0. This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 1. Input enabled Indicates that the input function can be used. Internal input fixed at 0 Hi-Z This is the status that the input function cannot be used. Internal input is fixed at L. Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state. Setting disabled Indicates that the setting is disabled. Maintain previous state Maintains the state that was immediately prior to entering the current mode. If a built-in peripheral function is operating, the output follows the peripheral function. If the pin is being used as a port, that output is maintained. Analog input is enabled Indicates that the analog input is enabled. Document Number: Rev.*A Page 39 of 95

40 Pin status type S6E1A11B0A/C0A List of Pin Status A B Function group GPIO selected Main crystal oscillator input pin/ External main clock input selected GPIO selected External main clock input selected Main crystal oscillator output pin C INITX input pin D Mode input pin E F GPIO selected Sub crystal oscillator input pin / External sub clock input selected GPIO selected External sub clock input selected State upon power-on reset or low-voltage detection Power supply unstable Setting disabled Input enabled Setting disabled Setting disabled State at INITX input State upon device internal reset Power supply stable State in Run mode or SLEEP mode Power supply stable State in TIMER mode, RTC mode, or STOP mode Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = SPL = 0 SPL = 1 Hi-Z / Internal Setting Setting Maintain Maintain input fixed at disabled disabled previous state previous state "0" Hi-Z / Internal input fixed at "0"/ Input enabled Pull-up / Input enabled Input enabled Setting disabled Input enabled Setting disabled Setting disabled Input enabled Setting disabled Setting disabled Hi-Z / Internal input fixed at "0" Pull-up / Input enabled Input enabled Setting disabled Input enabled Setting disabled Setting disabled Input enabled Input enabled Input enabled Input enabled Setting disabled Setting disabled Hi-Z / Internal input fixed at "0" Pull-up / Input enabled Maintain previous state Maintain previous state Maintain previous state/when oscillation stops* 1, Hi-Z / Internal input fixed at "0" Pull-up / Input enabled Maintain previous state Maintain previous state Maintain previous state/when oscillation stops* 1, Hi-Z / Internal input fixed at "0" Pull-up / Input enabled Hi-Z / Internal input fixed at "0" Hi-Z / Internal input fixed at "0" Maintain previous state/when oscillation stops* 1, Hi-Z / Internal input fixed at "0" Pull-up / Input enabled Input enabled Input enabled Input enabled Input enabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at "0" Input enabled Input enabled Input enabled Input enabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Hi-Z / Internal input fixed at "0" Hi-Z / Internal input fixed at "0" Document Number: Rev.*A Page 40 of 95

41 Pin status type S6E1A11B0A/C0A G H I Function group Sub crystal oscillator output pin NMIX selected Resource other than the above selected GPIO selected Serial wire debug selected GPIO selected Resource selected GPIO selected State upon power-on reset or low-voltage detection Power supply unstable Hi-Z / Internal input fixed at "0"/ Input enabled Setting disabled Hi-Z Hi-Z Setting disabled Hi-Z State at INITX input State upon device internal reset Power supply stable State in Run mode or SLEEP mode Power supply stable State in TIMER mode, RTC mode, or STOP mode Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = SPL = 0 SPL = 1 Maintain Maintain previous previous state/when state/when Hi-Z / Hi-Z / Internal Maintain oscillation oscillation Internal input input fixed at previous state stops* 2, stops* 2, fixed at "0" "0" Hi-Z / Internal Hi-Z / Internal input fixed at input fixed at "0" "0" Setting disabled Hi-Z / Input enabled Pull-up / Input enabled Setting disabled Hi-Z / Input enabled Setting disabled Hi-Z / Input enabled Pull-up / Input enabled Setting disabled Hi-Z / Input enabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Hi-Z / Internal input fixed at "0" Maintain previous state Hi-Z / Internal input fixed at "0" Hi-Z / Internal input fixed at "0" J External interrupt enabled selected Resource other than the above selected GPIO selected Setting disabled Hi-Z Setting disabled Hi-Z / Input enabled Setting disabled Hi-Z / Input enabled Maintain previous state Maintain previous state Maintain previous state Hi-Z / Internal input fixed at "0" K Analog input selected Resource other than the above selected GPIO selected Hi-Z Setting disabled Hi-Z / Internal input fixed at "0" / Analog input enabled Setting disabled Hi-Z / Internal input fixed at "0" / Analog input enabled Setting disabled Hi-Z / Internal input fixed at "0" / Analog input enabled Maintain previous state Hi-Z / Internal input fixed at "0" / Analog input enabled Maintain previous state Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" L Analog input selected Hi-Z Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Document Number: Rev.*A Page 41 of 95

42 Pin status type S6E1A11B0A/C0A Function group External interrupt enabled selected Resource other than the above selected GPIO selected State upon power-on reset or low-voltage detection Power supply unstable Setting disabled State at INITX input State upon device internal reset Power supply stable State in Run mode or SLEEP mode Power supply stable State in TIMER mode, RTC mode, or STOP mode Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = SPL = 0 SPL = 1 Setting disabled Setting disabled Maintain previous state *1:Oscillation stops in Sub timer mode, Low-speed CR timer mode, STOP mode, RTC mode. *2:Oscillation stops in STOP mode. Maintain previous state Maintain previous state Hi-Z / Internal input fixed at "0" Document Number: Rev.*A Page 42 of 95

43 12. Electrical Characteristics 12.1 Absolute Maximum Ratings Parameter Symbol Min Rating Max Unit Power supply voltage* 1, * 2 V CC V SS V SS V Analog power supply voltage* 1, * 3 AV CC V SS V SS V Analog reference voltage* 1, * 3 AVRH V SS V SS V Remarks Only S6E1A1xC0A Input voltage* 1 V V V SS CC I ( 6.5 V) V V SS V SS V 5V tolerant Analog pin input voltage* 1 V IA V SS AV CC ( 6.5 V) V Output voltage* 1 V O V SS Vcc ( 6.5 V) V "L" level maximum output current* 4 I OL - 10 ma 4 ma type 20 ma 12 ma type "L" level average output current* 5 I OLAV - 4 ma 4 ma type 12 ma 12 ma type "L" level total maximum output current I OL ma "L" level total average output current* 6 I OLAV - 50 ma "H" level maximum output current* 4 I OH ma 4 ma type - 20 ma 12 ma type "H" level average output current* 5 I OHAV ma 4 ma type - 12 ma 12 ma type "H" level total maximum output current I OH ma "H" level total average output current* 6 I OHAV ma Power consumption P D mw Storage temperature T STG C *1:These parameters are based on the condition that V SS = AVss = 0 V. *2:Vcc must not drop below V SS V. *3:Ensure that the voltage does not to exceed V CC V at power-on. *4:The maximum output current is the peak value for a single pin. *5:The average output is the average current for a single pin over a period of 100 ms. *6:The total average output current is the average current for all pins over a period of 100 ms. Warning Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings Document Number: Rev.*A Page 43 of 95

44 12.2 Recommended Operating Conditions (V SS = AV SS = 0.0V) Parameter Symbol Conditions Min Value Max Unit Remarks Power supply voltage V CC - 2.7* V Analog power supply voltage AV CC V AV CC = V CC Analog reference voltage AVRH AV CC V Only S6E1A1xC0A Smoothing capacitor C S μf For regulator* 1 Operating temperature Ta C 1: See "C Pin" in "6. Handling Precautions" for the connection of the smoothing capacitor. *2: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction execution and low voltage detection function by built-in High-speed CR(including Main PLL is used) or built-in Low-speed CR is possible to operate only. Warning 1. The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. 2. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. 3. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. 4. Users considering application outside the listed conditions are advised to contact their representatives beforehand. Document Number: Rev.*A Page 44 of 95

45 12.3 DC Characteristics Current Rating Symbol (Pin name) Icc (VCC) Iccs (VCC) Run mode, code executed from Flash Run mode, code executed from RAM Run mode, code executed from Flash Run mode, code executed from Flash SLEEP operation Conditions 4MHz external clock input, PLL ON* 8 NOP code executed Built-in high speed CR stopped All peripheral clock stopped by CKENx 4MHz external clock input, PLL ON* 8 Benchmark code executed Built-in high speed CR stopped PCLK1 stopped 4MHz crystal oscillation, PLL ON* 8 NOP code executed Built-in high speed CR stopped All peripheral clock stopped by CKENx 4MHz external clock input, PLL ON* 8 NOP code executed Built-in high speed CR stopped All peripheral clock stopped by CKENx 4MHz external clock input, PLL ON NOP code executed Built-in high speed CR stopped PCLK1 stopped Built-in high speed CR* 5 NOP code executed All peripheral clock stopped by CKENx 32kHz crystal oscillation NOP code executed All peripheral clock stopped by CKENx Built-in low speed CR NOP code executed All peripheral clock stopped by CKENx 4MHz external clock input, PLL ON* 8 All peripheral clock stopped by CKENx Built-in high speed CR* 5 All peripheral clock stopped by CKENx 32kHz crystal oscillation All peripheral clock stopped by CKENx Built-in low speed CR All peripheral clock stopped by CKENx HCLK Value Frequency * 4 Typ* 1 Max* 2 4MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz Unit ma *3 ma *3 ma *3 ma *3 Remarks 40MHz ma *3,*6,*7 4MHz ma *3 32kHz μa *3 100kHz μa *3 4MHz MHz MHz MHz ma *3 4MHz ma *3 32kHz μa *3 100kHz μa *3 Document Number: Rev.*A Page 45 of 95

46 *1 : Ta=+25,V CC =3.0V *2 : Ta=+105,V CC =5.5V *3 : All ports are fixed *4 : PCLK0=HCLK/8 *5 : The frequency is set to 4MHz by trimming *6 : Flash sync down is set to FRWTR.RWT = 11 and FSYNDN.SD = 1111 *7 : V CC =2.7V *8 : When HCLK=4MHz, PLL OFF Symbol (Pin name) I CCH (VCC) I CCT (VCC) I CCR (VCC) STOP mode Sub timer mode RTC mode *1:All ports are fixed. Conditions Ta=25 Vcc=3.0V LVD off Ta=25 Vcc=5.0V LVD off Ta=105 Vcc=5.5V LVD off Ta=25 Vcc=3.0V 32kHz crystal oscillation LVD off Ta=25 Vcc=5.0V 32kHz crystal oscillation LVD off Ta=105 Vcc=5.5V 32kHz crystal oscillation LVD off Ta=25 Vcc=3.0V 32kHz crystal oscillation LVD off Ta=25 Vcc=5.0V 32kHz crystal oscillation LVD off Ta=105 Vcc=5.5V 32kHz crystal oscillation LVD off Typ Value Max Uni t μa * μa *1-540 μa * μa * μa *1-730 μa * μa * μa *1-570 μa *1 Remarks Document Number: Rev.*A Page 46 of 95

47 LVD current Parameter Low-Voltage detection circuit (LVD) power supply current Symbol Pin name Conditions I CCLVD VCC At operation (V CC = 2.7V to 5.5V, V SS = AV SS = 0V, Ta = - 40 C to C) Value Typ Max Unit Remarks μa For occurrence of reset μa For occurrence of interrupt Flash memory current Parameter Flash memory write/erase current Symbol Pin name Conditions (V CC = 2.7V to 5.5V, V SS = AV SS = 0V, Ta = - 40 C to C) Value Typ Max I CCFLASH VCC At Write/Erase ma Unit Remarks A/D convertor current (S6E1A1xC0A) Parameter Power supply current Reference power supply current (AVRH) Symbol I CCAD I CCAVRH Pin name AVCC AVRH (V CC = 2.7V to 5.5V, V SS = AV SS = 0V, Ta = - 40 C to C) Conditions Value Typ Max Unit Remarks At operation ma At stop μa At operation ma AVRH=5.5V At stop μa A/D convertor current (S6E1A1xB0A) Parameter Power supply current Symbol I CCAD Pin name AVCC (V CC = 2.7V to 5.5V, V SS = AV SS = 0V, Ta = - 40 C to C) Conditions Value Typ Max Unit Remarks At operation ma At stop μa Peripheral current dissipation Clock Frequency (MHz) system Peripheral Conditions HCLK GPIO At all ports operation DMAC At 2ch operation Base timer At 4ch operation Multi-functional timer/ppg At 1unit/4ch operation PCLK1 Quadrature position/revolution counter At 1unit operation ADC At 1unit operation Multi-function serial At 1ch operation Unit ma ma Remarks Document Number: Rev.*A Page 47 of 95

48 Pin Characteristics Parameter Symbol Pin name Conditions "H" level input voltage (hysteresis input) "L" level input voltage (hysteresis input) "H" level output voltage "L" level output voltage Input leak current Pull-up resistance value Input capacitance V IHS V ILS V OH V OL CMOS hysteresis input pin, MD0, PE0 5V tolerant input pin CMOS hysteresis input pin, MD0, PE0 5V tolerant input pin 4 ma type 12 ma type 4 ma type 12 ma type (V CC =AV CC = 2.7 V to 5.5 V, V SS = AV SS = 0 V, Ta = - 40 C to C) Value Min Typ Max - V CC V CC V - V CC V SS V - V SS V CC 0.2 V - V SS V CC 0.2 V V CC 4.5 V, I OH = - 4 ma V CC < 4.5 V, I OH = - 2 ma V CC 4.5 V, I OH = - 12 ma V CC < 4.5 V, I OH = - 8 ma V CC 4.5 V, I OL = 4 ma V CC < 4.5 V, I OL = 2 ma V CC 4.5 V, I OL = 12 ma V CC < 4.5 V, I OL = 8 ma V CC V CC V V CC V CC V V SS V V SS V I IL μa R PU C IN Pull-up pin Other than VCC, VSS, AVCC, AVSS, AVRH V CC 4.5 V V CC < 4.5 V pf Unit kω Remarks Document Number: Rev.*A Page 48 of 95

49 12.4 AC Characteristics Main Clock Input Characteristics Parameter Input frequency Symbol F CH Pin name (V CC = AV CC = 2.7 V to 5.5 V, V SS = AV SS = 0 V, Ta = - 40 C to C) Value Conditions Unit Remarks Min Max V CC 4.5V 4 40 V CC < 4.5V 4 20 X0, Input clock cycle t CYLH X ns Input clock pulse width Input clock rising time and falling time Internal operating clock *1 frequency - t CF, t CR MHz MHz PWH/tCYLH, PWL/tCYLH % ns When the crystal oscillator is connected When the external clock is used When the external clock is used When the external clock is used When the external clock is used F CM MHz Master clock F CC MHz Base clock (HCLK/FCLK) F CP MHz APB0 bus clock* 2 F CP MHz APB1 bus clock* 2 t CYCC ns Base clock (HCLK/FCLK) Internal operating clock *1 cycle time t CYCP ns APB0 bus clock* 2 t CYCP ns APB1 bus clock* 2 *1: For details of each internal operating clock, refer to "CHAPTER: Clock" in "FM0+ Family PERIPHERAL MANUAL". *2: For details of the APB bus to which a peripheral is connected, see "8. Block Diagram". X0 Document Number: Rev.*A Page 49 of 95

50 Sub Clock Input Characteristics (V CC = AV CC = 2.7 V to 5.5 V, V SS = AV SS = 0 V, Ta = - 40 C to C) Parameter Symbol Pin Value name Conditions Min Typ Max Unit Remarks When the crystal khz oscillator is Input frequency 1/t CYLL connected When the external X0A, khz clock is used X1A When the external Input clock cycle t CYLL μs clock is used Input clock pulse PWH/tCYLL, When the external % width PWL/tCYLL clock is used *: See "Sub crystal oscillator" in "7. Handling Devices" for the crystal oscillator used. X0A Document Number: Rev.*A Page 50 of 95

51 Built-in CR Oscillation Characteristics Built-in high-speed CR Parameter Symbol Conditions Clock frequency F CRH Ta = + 25 C, 3.6V < V CC 5.5V Ta =0 C to + 85 C, 3.6V < V CC 5.5V Ta = - 40 C to C, 3.6V < V CC 5.5V Ta = + 25 C, 2.7V V CC 3.6V Ta = - 20 C to + 85 C, 2.7V V CC 3.6V Ta = - 20 C to C, 2.7V V CC 3.6V Ta = - 40 C to C, 2.7V V CC 3.6V (V CC = AV CC = 2.7 V to 5.5 V, V SS =AV SS = 0 V, Ta = - 40 C to C) Value Min Typ Max Unit MHz Remarks During trimming *1 Ta = - 40 C to C Not during trimming Frequency t stabilization time CRWT μs *2 *1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency trimming/temperature trimming. *2: This is time from the trim value setting to stable of the frequency of the High-speed CR clock. After setting the trim value, the period when the frequency stability time passes can use the High-speed CR clock as a source clock. Built-in low-speed CR Parameter Symbol Conditions (V CC = AV CC = 2.7 V to 5.5 V, V SS =AV SS = 0 V, Ta = - 40 C to C) Value Unit Remarks Min Typ Max Clock frequency F CRL khz Document Number: Rev.*A Page 51 of 95

52 Operating Conditions of Main PLL (In the case of using the main clock as the input clock of the PLL) (V CC = AV CC = 2.7 V to 5.5 V, V SS = AV SS = 0 V, Ta = - 40 C to C) Parameter Symbol Value Min Typ Max Unit Remarks PLL oscillation stabilization wait time* 1 (LOCK UP time) t LOCK μs PLL input clock frequency F PLLI 4-16 MHz PLL multiple rate multiple PLL macro oscillation clock frequency F PLLO MHz Main PLL clock frequency* 2 F CLKPLL MHz *1: The wait time is the time it takes for PLL oscillation to stabilize. *2: For details of the main PLL clock (CLKPLL), refer to "CHAPTER: Clock" in "FM0+ Family PERIPHERAL MANUAL" Operating Conditions of Main PLL (In the case of using the built-in high-speed CR clock as the input clock of the main PLL) (V CC = AV CC = 2.7 V to 5.5 V, V SS = AV SS = 0 V, Ta = - 40 C to C) Parameter Symbol Value Min Typ Max Unit Remarks PLL oscillation stabilization wait time* 1 (LOCK UP time) t LOCK μs PLL input clock frequency F PLLI MHz PLL multiple rate multiple PLL macro oscillation clock frequency F PLLO MHz Main PLL clock frequency* 2 F CLKPLL MHz *1: The wait time is the time it takes for PLL oscillation to stabilize. *2: For details of the main PLL clock (CLKPLL), refer to "CHAPTER: Clock" in "FM0+ Family PERIPHERAL MANUAL". Note: For the main PLL source clock, input the high-speed CR clock (CLKHC) whose frequency has been trimmed. Document Number: Rev.*A Page 52 of 95

53 Reset Input Characteristics (V CC =AV CC = 2.7 V to 5.5 V, V SS = AV SS = 0 V, Ta = - 40 C to C) Parameter Symbol Pin name Conditions Min Value Max Unit Remarks Reset input time t INITX INITX ns Power-on Reset Timing (V CC = AV CC = 2.7 V to 5.5 V, V SS = AV SS = 0 V, Ta = - 40 C to C) Parameter Symbol Pin name Min Value Max Unit Remarks Power supply rising time Tr 0 - ms Power supply shut down time Toff VCC 1 - ms Time until releasing Power-on reset Tprt ms VCC_minimum VCC VDH_minimum 0.2V Tr 0.2V 0.2V Tprt Toff Internal RST RST Active Release CPU Operation start Glossary VCC_minimum : Minimum V CC of recommended operating conditions. VDH_minimum : Minimum release voltage (when SVHR=0000) of Low-Voltage detection reset. See "6. Low-Voltage Detection Characteristics". Document Number: Rev.*A Page 53 of 95

54 Base Timer Input Timing Timer input timing Parameter Symbol Pin name Conditions Input pulse width t TIWH, t TIWL TIOAn/TIOBn (when using as ECK, TIN) (V CC = AV CC = 2.7 V to 5.5 V, V SS = AV SS = 0 V, Ta = - 40 C to C) Value Min Max - 2 t CYCP - ns Unit Remarks ECK t TIWH t TIWL TIN V IHS V IHS V ILS V ILS Trigger input timing Parameter Symbol Pin name Conditions Input pulse width t TRGH, t TRGL TIOAn/TIOBn (when using as TGIN) (V CC = AV CC = 2.7 V to 5.5 V, V SS = AV SS = 0 V, Ta = - 40 C to C) Value Min Max - 2 t CYCP - ns Unit Remarks t TRGH t TRGL TGIN V IHS V IHS V ILS V ILS Note: t CYCP indicates the APB bus clock cycle time. For the number of the APB bus to which the Base Timer has been connected, see "8. Block Diagram". Document Number: Rev.*A Page 54 of 95

55 CSIO Timing Synchronous serial (SPI = 0, SCINV = 0) Parameter Symbol Pin name Serial clock cycle time t SCYC SCKx SCK SOT delay time t SLOVI SCKx, SOTx SIN SCK setup time t IVSHI SCKx, SINx SCK SIN hold time t SHIXI SCKx, SINx Serial clock "L" pulse width t SLSH SCKx (V CC = AV CC = 2.7 V to 5.5 V, V SS = AV SS = 0 V, Ta = - 40 C to C) Conditions Internal shift clock operation V CC < 4.5 V V CC 4.5 V Unit Min Max Min Max 4 t CYCP - 4 t CYCP - ns ns ns ns 2 t CYCP - 10 Serial clock "H" pulse width t SHSL SCKx t CYCP t CYCP - 10 t CYCP ns - ns SCKx, SCK SOT delay time t SLOVE External shift ns SOTx clock SCKx, SIN SCK setup time t IVSHE operation ns SINx SCK SIN hold time t SHIXE SCKx, SINx ns SCK falling time tf SCKx ns SCK rising time tr SCKx ns Notes: The above AC characteristics are for CLK synchronous mode. t CYCP represents the APB bus clock cycle time. For the number of the APB bus to which Multi-function Serial has been connected, see "8. Block Diagram ". The characteristics are only applicable when the relocate port numbers are the same. For instance, they are not applicable for the combination of SCLKx_0 and SOTx_1. External load capacitance C L = 30 pf tscyc SCK VOL VOH VOL SOT t SLOVI VOH VOL SIN VIH VIL tivshi tshixi VIH VIL MS bit = 0 Document Number: Rev.*A Page 55 of 95

56 tslsh tshsl SCK VIH tf VIL t SLOVE VIL VIH tr VIH SOT VOH VOL SIN tivshe VIH VIL tshixe VIH VIL MS bit = 1 Synchronous serial (SPI = 0, SCINV = 1) (V CC = AV CC = 2.7 V to 5.5 V, V SS = AV SS = 0 V, Ta = - 40 C to C) Parameter Symbol Pin V name Conditions CC < 4.5V V CC 4.5V Min Max Min Max Unit Serial clock cycle time t SCYC SCKx 4 t CYCP - 4 t CYCP - ns SCK SOT delay time t SHOVI SCKx, SOTx Internal shift ns SIN SCK setup time t IVSLI SCKx, clock SINx operation ns SCK SIN hold time t SLIXI SCKx, SINx ns Serial clock "L" pulse width t SLSH SCKx 2 t CYCP - 2 t - CYCP ns Serial clock "H" pulse width t SHSL SCKx t CYCP t CYCP ns SCK SOT delay time t SHOVE SCKx, SOTx External shift ns SIN SCK setup time t IVSLE SCKx, clock SINx operation ns SCK SIN hold time t SLIXE SCKx, SINx ns SCK falling time tf SCKx ns SCK rising time tr SCKx ns Notes: The above AC characteristics are for CLK synchronous mode. t CYCP represents the APB bus clock cycle time. For the number of the APB bus to which Multi-function Serial has been connected, see "8. Block Diagram ". The characteristics are only applicable when the relocate port numbers are the same. For instance, they are not applicable for the combination of SCLKx_0 and SOTx_1. External load capacitance C L = 30 pf Document Number: Rev.*A Page 56 of 95

57 tscyc SCK VOH VOH VOL SOT t SHOVI VOH VOL SIN VIH VIL tivsli tslixi VIH VIL MS bit = 0 tshsl tslsh SCK tr VIL VIH t SHOVE tf VIH VIL VIL SOT VOH VOL tivsle tslixe SIN VIH VIH VIL VIL MS bit = 1 Document Number: Rev.*A Page 57 of 95

58 Synchronous serial (SPI = 1, SCINV = 0) (V CC = AV CC = 2.7 V to 5.5 V, V SS = AV SS = 0 V, Ta = - 40 C to C) Parameter Symbol Pin V name Conditions CC < 4.5 V V CC 4.5 V Min Max Min Max Unit Serial clock cycle time t SCYC SCKx 4 t CYCP - 4 t CYCP - ns SCK SOT delay time t SHOVI SCKx, SOTx ns SCKx, Internal shift SIN SCK setup time t IVSLI clock ns SINx SCKx, operation SCK SIN hold time t SLIXI ns SINx SOT SCK delay time t SOVLI SCKx, 2 t CYCP - 2 t - CYCP - SOTx ns Serial clock "L" pulse width t SLSH SCKx 2 t CYCP - 2 t - CYCP ns Serial clock "H" pulse width t SHSL SCKx t CYCP t CYCP ns SCK SOT delay time t SHOVE SCKx, SOTx External shift ns SIN SCK setup time t IVSLE SCKx, clock SINx operation ns SCK SIN hold time t SLIXE SCKx, SINx ns SCK falling time tf SCKx ns SCK rising time tr SCKx ns Notes: The above AC characteristics are for CLK synchronous mode. t CYCP represents the APB bus clock cycle time. For the number of the APB bus to which Multi-function Serial has been connected, see "8. Block Diagram ". The characteristics are only applicable when the relocate port numbers are the same. For instance, they are not applicable for the combination of SCLKx_0 and SOTx_1. External load capacitance C L = 30 pf Document Number: Rev.*A Page 58 of 95

59 tscyc SCK tsovli VOL VOH tshovi VOL SOT VOH VOL VOH VOL tivsli tslixi SIN VIH VIL VIH VIL MS bit = 0 tslsh tshsl SCK VIH VIH VIH VIL VIL SOT * VOH VOL tf tr tshove VOH VOL tivsle tslixe SIN VIH VIL VIH VIL MS bit = 1 *: This changes as data is written to the TDR register. Document Number: Rev.*A Page 59 of 95

60 Synchronous serial (SPI = 1, SCINV = 1) Parameter Symbol Pin name Serial clock cycle time t SCYC SCKx (V CC = AV CC = 2.7 V to 5.5 V, V SS = AV SS = 0 V, Ta = - 40 C to C) Conditions V CC < 4.5 V V CC 4.5 V Unit Min Max Min Max 4 t CYCP - 4 t CYCP - ns SCK SOT delay time t SLOVI SCKx, SOTx ns Internal shift SCKx, SIN SCK setup time t IVSHI clock ns SINx operation SCKx, SCK SIN hold time t SHIXI ns SINx SOT SCK delay time t SOVHI SCKx, 2 t CYCP - 2 t - CYCP - SOTx ns Serial clock "L" pulse width t SLSH SCKx 2 t CYCP - 2 t - CYCP ns Serial clock "H" pulse width t SHSL SCKx t CYCP t CYCP ns SCK SOT delay time t SLOVE SCKx, SOTx External shift ns SIN SCK setup time t IVSHE SCKx, clock SINx operation ns SCK SIN hold time t SHIXE SCKx, SINx ns SCK falling time tf SCKx ns SCK rising time tr SCKx ns Notes: The above AC characteristics are for CLK synchronous mode. t CYCP represents the APB bus clock cycle time. For the number of the APB bus to which Multi-function Serial has been connected, see "8. Block Diagram ". The characteristics are only applicable when the relocate port numbers are the same. For instance, they are not applicable for the combination of SCLKx_0 and SOTx_1. External load capacitance C L = 30 pf Document Number: Rev.*A Page 60 of 95

61 tscyc SCK VOH VOL VOH tsovhi tslovi SOT VOH VOL VOH VOL tivshi tshixi SIN VIH VIL VIH VIL MS bit = 0 tr tshsl tslsh tf SCK VIL VIH VIH VIL VIL VIH tslove SOT VOH VOH VOL VOL tivshe tshixe SIN VIH VIL VIH VIL MS bit = 1 Document Number: Rev.*A Page 61 of 95

62 When using synchronous serial chip select (SPI = 1, SCINV = 0, MS=0, CSLVL=1) Parameter Symbol Conditions V CC < 4.5V V CC 4.5V Min Max Min Max (V CC = 2.7V to 5.5V, V SS = 0V) SCS SCK setup time t CSSI (*1)-50 (*1)+0 (*1)-50 (*1)+0 ns Internal shift SCK SCS hold time t CSHI clock (*2)+0 (*2)+50 (*2)+0 (*2)+50 ns SCS deselect time t operation (*3)-50 (*3)+50 (*3)-50 (*3)+50 CSDI ns +5t CYCP +5t CYCP +5t CYCP +5t CYCP SCS SCK setup time 3t CYCP +30-3t CYCP ns t CSSE SCK SCS hold time t CSHE External shift ns SCS deselect time t CSDE clock 3t CYCP +30-3t CYCP ns SCS SUT delay time t DSE operation ns SCS SUT delay time t DEE ns Unit (*1): CSSU bit value serial chip select timing operating clock cycle [ns] (*2): CSHD bit value serial chip select timing operating clock cycle [ns] (*3): CSDS bit value serial chip select timing operating clock cycle [ns] Notes: t CYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function Serial is connected to, see "8. Block Diagram ". About CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM0+ Family PERIPHERAL MANUAL". When the external load capacitance C L = 30pF. Document Number: Rev.*A Page 62 of 95

63 SCS output tcsdi tcssi tcshi SCK output SOT (SPI=0) SOT (SPI=1) SCS input tcsde tcsse tcshe SCK input tdee SOT (SPI=0) tdse SOT (SPI=1) Document Number: Rev.*A Page 63 of 95

64 When using synchronous serial chip select (SPI = 1, SCINV = 1, MS=0, CSLVL=1) Parameter Symbol Conditions V CC < 4.5V V CC 4.5V Min Max Min Max (V CC = 2.7V to 5.5V, V SS = 0V) SCS SCK setup time t CSSI (*1)-50 (*1)+0 (*1)-50 (*1)+0 ns Internal shift SCK SCS hold time t CSHI clock (*2)+0 (*2)+50 (*2)+0 (*2)+50 ns SCS deselect time t operation (*3)-50 (*3)+50 (*3)-50 (*3)+50 CSDI ns +5t CYCP +5t CYCP +5t CYCP +5t CYCP SCS SCK setup time 3t CYCP +30-3t CYCP ns t CSSE SCK SCS hold time t CSHE External shift ns SCS deselect time t CSDE clock 3t CYCP +30-3t CYCP ns SCS SOT delay time t DSE operation ns SCS SOT delay time t DEE ns Unit (*1): CSSU bit value serial chip select timing operating clock cycle [ns] (*2): CSHD bit value serial chip select timing operating clock cycle [ns] (*3): CSDS bit value serial chip select timing operating clock cycle [ns] Notes: t CYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function Serial is connected to, see "8. Block Diagram ". About CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM0+ Family PERIPHERAL MANUAL". When the external load capacitance C L = 30pF. Document Number: Rev.*A Page 64 of 95

65 SCS output tcsdi tcssi tcshi SCK output SOT (SPI=0) SOT (SPI=1) SCS input tcsde tcsse tcshe SCK input SOT (SPI=0) tdee SOT (SPI=1) tdse Document Number: Rev.*A Page 65 of 95

66 When using synchronous serial chip select (SPI = 1, SCINV = 0, MS=0, CSLVL=0) Parameter Symbol Conditions V CC < 4.5V V CC 4.5V Min Max Min Max (V CC = 2.7V to 5.5V, V SS = 0V) SCS SCK setup time t CSSI (*1)-50 (*1)+0 (*1)-50 (*1)+0 ns Internal shift SCK SCS hold time t CSHI clock (*2)+0 (*2)+50 (*2)+0 (*2)+50 ns SCS deselect time t operation (*3)-50 (*3)+50 (*3)-50 (*3)+50 CSDI ns +5t CYCP +5t CYCP +5t CYCP +5t CYCP SCS SCK setup time 3t CYCP +30-3t CYCP ns t CSSE SCK SCS hold time t CSHE External shift ns SCS deselect time t CSDE clock 3t CYCP +30-3t CYCP ns SCS SOT delay time t DSE operation ns SCS SOT delay time t DEE ns Unit (*1): CSSU bit value serial chip select timing operating clock cycle [ns] (*2): CSHD bit value serial chip select timing operating clock cycle [ns] (*3): CSDS bit value serial chip select timing operating clock cycle [ns] Notes: t CYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function Serial is connected to, see "8. Block Diagram ". About CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM0+ Family PERIPHERAL MANUAL". When the external load capacitance C L = 30pF. Document Number: Rev.*A Page 66 of 95

67 SCS output tcsdi tcssi tcshi SCK output SOT (SPI=0) SOT (SPI=1) SCS input tcsde tcsse tcshe SCK input SOT (SPI=0) tdee SOT (SPI=1) tdse Document Number: Rev.*A Page 67 of 95

68 When using synchronous serial chip select (SPI = 1, SCINV = 1, MS=0, CSLVL=0) Parameter Symbol Conditions V CC < 4.5V V CC 4.5V Min Max Min Max (V CC = 2.7V to 5.5V, V SS = 0V) SCS SCK setup time t CSSI (*1)-50 (*1)+0 (*1)-50 (*1)+0 ns Internal shift SCK SCS hold time t CSHI clock (*2)+0 (*2)+50 (*2)+0 (*2)+50 ns SCS deselect time t operation (*3)-50 (*3)+50 (*3)-50 (*3)+50 CSDI ns +5t CYCP +5t CYCP +5t CYCP +5t CYCP SCS SCK setup time 3t CYCP +30-3t CYCP ns t CSSE SCK SCS hold time t CSHE External shift ns SCS deselect time t CSDE clock 3t CYCP +30-3t CYCP ns SCS SOT delay time t DSE operation ns SCS SOT delay time t DEE ns Unit (*1): CSSU bit value serial chip select timing operating clock cycle [ns] (*2): CSHD bit value serial chip select timing operating clock cycle [ns] (*3): CSDS bit value serial chip select timing operating clock cycle [ns] Notes: t CYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function Serial is connected to, see "8. Block Diagram ". About CSSU, CSHD, CSDS, serial chip select timing operating clock, see "FM0+ Family PERIPHERAL MANUAL". When the external load capacitance C L = 30pF. Document Number: Rev.*A Page 68 of 95

69 SCS output tcsdi tcssi tcshi SCK output SOT (SPI=0) SOT (SPI=1) SCS input tcsde tcsse tcshe SCK input SOT (SPI=0) tdee SOT (SPI=1) tdse Document Number: Rev.*A Page 69 of 95

70 External clock (EXT = 1): asynchronous only (V CC = AV CC = 2.7 V to 5.5 V, V SS = AV SS = 0 V, Ta = - 40 C to C) Value Parameter Symbol Conditions Unit Min Max Serial clock "L" pulse width t SLSH t CYCP ns Serial clock "H" pulse width t SHSL t C L = 30 pf CYCP ns SCK falling time tf - 5 ns SCK rising time tr - 5 ns Remarks SCK tr tshsl tslsh V IH V IH V IH V IL V IL V IL tf Document Number: Rev.*A Page 70 of 95

71 External Input Timing Parameter Symbol Pin name Conditions ADTGx (V CC = AV CC = 2.7 V to 5.5 V, V SS = AV SS = 0 V, Ta = - 40 C to C) Value Min Max Unit Remarks A/D converter trigger input FRCKx - 2 t CYCP * 1 - ns Free-run timer input clock Input pulse width t INH, t INL ICxx Input capture DTTIxX - 2 t CYCP * 1 - ns Wave form generator INTxx, NMIX - 2 t CYCP + 100* 1 - ns External 500* 2 - ns interrupt, NMI *1: t CYCP represents the APB bus clock cycle time except when the APB bus clock stops in STOP mode or in TIMER mode. For the number of the APB bus to which the Multi-function Timer is connected and that of the APB bus to which the External Interrupt Controller is connected, see "8. Block Diagram". *2: In STOP mode and TIMER mode Document Number: Rev.*A Page 71 of 95

72 QPRC Timing (V CC = AV CC = 2.7 V to 5.5 V, V SS = AV SS = 0 V, Ta = - 40 C to C) Parameter Symbol Conditions Min Value Max Unit AIN pin "H" width t AHL - AIN pin "L" width t ALL - BIN pin "H" width t BHL - BIN pin "L" width t BLL - Time from AIN pin "H" level to BIN rise t AUBU PC_Mode2 or PC_Mode3 Time from BIN pin "H" level to AIN fall t BUAD PC_Mode2 or PC_Mode3 Time from AIN pin "L" level to BIN fall t ADBD PC_Mode2 or PC_Mode3 Time from BIN pin "L" level to AIN rise t BDAU PC_Mode2 or PC_Mode3 Time from BIN pin "H" level to AIN rise t BUAU PC_Mode2 or PC_Mode3 2 t CYCP * - ns Time from AIN pin "H" level to BIN fall t AUBD PC_Mode2 or PC_Mode3 Time from BIN pin "L" level to AIN fall t BDAD PC_Mode2 or PC_Mode3 Time from AIN pin "L" level to BIN rise t ADBU PC_Mode2 or PC_Mode3 ZIN pin "H" width t ZHL QCR:CGSC="0" ZIN pin "L" width t ZLL QCR:CGSC="0" Time from determined ZIN level to AIN/BIN rise and fall t ZABE QCR:CGSC="1" Time from AIN/BIN rise and fall time to determined ZIN level t ABEZ QCR:CGSC="1" *: t CYCP represents the APB bus clock cycle time except when the APB bus clock stops in STOP mode or in TIMER mode. For the number of the APB bus to which the QPRC is connected, see "8. Block Diagram". tahl tall AIN taubu tbuad tadbd tbdau BIN tbhl tbll Document Number: Rev.*A Page 72 of 95

73 tbhl tbll BIN tbuau taubd tbdad tadbu AIN tahl tall ZIN ZIN AIN/BIN Document Number: Rev.*A Page 73 of 95

74 I 2 C Timing Parameter Symbol Conditions (V CC = AV CC = 2.7 V to 5.5 V, V SS = AV SS = 0 V, Ta = - 40 C to C) Standard-mode Fast-mode Unit Min Max Min Max khz SCL clock frequency F SCL (Repeated) START condition hold time t HDSTA μs SDA SCL SCL clock "L" width t LOW μs SCL clock "H" width t HIGH μs (Repeated) START setup time SCL SDA Data hold time SCL SDA Data setup time SDA SCL STOP condition setup time SCL SDA Bus free time between "STOP condition" and "START condition" t SUSTA μs t HDDAT C L = 30 pf, R = (Vp/I OL )* * * 3 μs t SUDAT ns t SUSTO μs t BUF μs Remarks Noise filter t SP - 2 t CYCP * 4-2 t CYCP * 4 - ns *1: R represents the pull-up resistance of the SCL and SDA lines, and CL the load capacitance of the SCL and SDA lines. Vp represents the power supply voltage of the pull-up resistance, and I OL the V OL guaranteed current. *2: The maximum t HDDAT must satisfy at least the condition that the period during which the device is holding the SCL signal at "L" (t LOW ) does not extend. *3: A Fast-mode I 2 C bus device can be used in a Standard-mode I 2 C bus system, provided that the condition of "t SUDAT 250 ns" is fulfilled. *4: t CYCP represents the APB bus clock cycle time. For the number of the APB bus to which the I 2 C is connected, see "8. Block Diagram". To use Standard-mode, set the APB bus clock at 2MHz or more. To use Fast-mode, set the APB bus clock at 8 MHz or more. SDA SCL Document Number: Rev.*A Page 74 of 95

75 SW-DP Timing Parameter Symbol Pin name Conditions SWDIO setup time SWDIO hold time SWDIO delay time t SWS t SWH t SWD SWCLK, SWDIO SWCLK, SWDIO SWCLK, SWDIO Note: External load capacitance C L = 30 pf (V CC = AV CC = 2.7 V to 5.5 V, V SS = AV SS = 0 V, Ta = - 40 C to C) Value Min Max ns ns ns Unit Remarks SWCLK SWDIO (When input) SWDIO (When output) SWD Document Number: Rev.*A Page 75 of 95

76 bit A/D Converter Electrical characteristics of A/D Converter (V CC = AV CC = 2.7 V to 5.5 V, V SS = AV SS = 0 V, Ta = - 40 C to C) Parameter Symbol Pin name Min Value Typ Max Unit Remarks Resolution bit Integral Nonlinearity LSB Differential Nonlinearity LSB Zero transition voltage V ZT ANxx mv Full-scale transition voltage V FST ANxx AVRH AVRH+ 20 mv S6E1A1xC0A AV CC AV CC +20 S6E1A1xB0A Conversion time * 1 S6E1A1xC0A - - μs AV CC 4.5V * 1 S6E1A1xB0A Sampling time* 2 S6E1A1xC0A 0.24 AV CC 4.5V - Ts - 10 μs S6E1A1xC0A 0.5 AV CC < 4.5V 0.6 S6E1A1xB0A Compare clock cycle* 3 S6E1A1xC0A 40 AV CC 4.5V - Tcck ns S6E1A1xC0A 50 AV CC < 4.5V 100 S6E1A1xB0A State transition time to operation permission Tstt μs Analog input capacity C AIN pf Analog input resistance R AIN AV CC 4.5V kω 2.3 AV CC < 4.5V Interchannel disparity LSB Analog port input current - ANxx μa Analog input voltage - ANxx AV SS - AVRH V S6E1A1xC0A AV SS - AV CC S6E1A1xB0A Reference voltage - AVRH AV CC V Only S6E1A1xB0A *1: The conversion time is the value of "sampling time (Ts) + compare time (Tc)". The minimum conversion time is computed according to the following conditions: sampling time = 240 ns, compare time = 560 ns (AVcc 4.5 V). Must be set 25MHz to the Base clock (HCLK). Ensure that the conversion time satisfies the specifications of the sampling time (Ts) and compare clock cycle (Tcck). For details of the settings of the sampling time and compare clock cycle, refer to "CHAPTER: A/D Converter" in "FM0+ Family PERIPHERAL MANUAL Analog Macro Part". The register settings of the A/D Converter are reflected in the operation according to the APB bus clock timing. For the number of the APB bus to which the A/D Converter is connected, see "8. Block Diagram". The base clock (HCLK) is used to generate the sampling time and the compare clock cycle. *2: The required sampling time varies according to the external impedance. Set a sampling time that satisfies (Equation 1). *3: The compare time (Tc) is the result of (Equation 2). Document Number: Rev.*A Page 76 of 95

77 Analog signal source Rext ANxx, Analog input pins R AIN Comparator C AIN (Equation 1) Ts (R AIN + Rext ) C AIN 9 Ts: Sampling time R AIN : Input resistance of A/D Converter = 1.6 kω with 4.5 < AVCC < 5.5 ch.1 to ch.5 Input resistance of A/D Converter = 1.4 kω with 4.5 < AVCC < 5.5 ch.0, ch.6, ch.7 Input resistance of A/D Converter = 2.3 kω with 2.7 < AVCC < 4.5 ch.1 to ch.5 Input resistance of A/D Converter = 2.0 kω with 2.7 < AVCC < 4.5 ch.0, ch.6, ch.7 CAIN: Input capacitance of A/D Converter = 9.7 pf with 2.7 < AVCC < 5.5 Rext: Output impedance of external circuit (Equation 2) Tc = Tcck 14 Tc: Compare time Tcck : Compare clock cycle Document Number: Rev.*A Page 77 of 95

78 Digital output Digital output S6E1A11B0A/C0A Definitions of 12-bit A/D Converter terms Resolution Integral Nonlinearity Differential Nonlinearity : Analog variation that is recognized by an A/D converter. : Deviation of the line between the zero-transition point (0b b ) and the full-scale transition point (0b b ) from the actual conversion characteristics. : Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB. Integral Nonlinearity Differential Nonlinearity 0xFFF 0xFFE 0xFFD 0x004 0x003 0x002 0x001 Actual conversion characteristics {1 LSB(N-1) + V ZT } V FST (Actuallymeasured value) V NT (Actually-measured value) Actual conversion characteristics Ideal characteristics V ZT (Actually-measured value) 0x(N+1) 0xN 0x(N-1) 0x(N-2) Actual conversion characteristics Ideal characteristics V NT V (N+1)T (Actually-measured value) (Actually-measured value) Actual conversion characteristics AV SS AVRH *1 AV SS AVRH *1 Analog input Analog input *1: At the 32pin product, it is AV CC Integral Nonlinearity of digital output N = V NT - {1LSB (N - 1) + V ZT } 1LSB [LSB] Differential Nonlinearity of digital output N = V (N + 1) T - V NT 1LSB - 1 [LSB] 1LSB = V FST V ZT 4094 N : A/D converter digital output value. V ZT : Voltage at which the digital output changes from 0x000 to 0x001. V FST : Voltage at which the digital output changes from 0xFFE to 0xFFF. : Voltage at which the digital output changes from 0x(N 1) to 0xN. V NT Document Number: Rev.*A Page 78 of 95

79 12.6 Low-voltage Detection Characteristics Low-voltage Detection Reset (Ta = - 40 C to C) Parameter Symbol Conditions Min Value Typ Max Unit Remarks Detected voltage VDL SVHR *1 = V When voltage drops Released voltage VDH V When voltage rises Detected voltage VDL SVHR *1 = V When voltage drops Released voltage VDH Same as SVHR = value V When voltage rises Detected voltage VDL SVHR *1 = V When voltage drops Released voltage VDH Same as SVHR = value V When voltage rises Detected voltage VDL SVHR *1 = V When voltage drops Released voltage VDH Same as SVHR = value V When voltage rises Detected voltage VDL SVHR *1 = V When voltage drops Released voltage VDH Same as SVHR = value V When voltage rises Detected voltage VDL SVHR *1 = V When voltage drops Released voltage VDH Same as SVHR = value V When voltage rises Detected voltage VDL SVHR *1 = V When voltage drops Released voltage VDH Same as SVHR = value V When voltage rises Detected voltage VDL SVHR *1 = V When voltage drops Released voltage VDH Same as SVHR = value V When voltage rises Detected voltage VDL SVHR *1 = V When voltage drops Released voltage VDH Same as SVHR = value V When voltage rises Detected voltage VDL SVHR *1 = V When voltage drops Released voltage VDH Same as SVHR = value V When voltage rises Detected voltage VDL SVHR *1 = V When voltage drops Released voltage VDH Same as SVHR = value V When voltage rises LVD stabilization wait time T LVDW t CYCP *2 μs LVD detection delay time T LVDDL μs *1: SVHR bit of Low-Voltage Detection Voltage Control Register (LVD_CTL) is reset to SVHR = by low voltage detection reset. *2: t CYCP indicates the APB1 bus clock cycle time. Document Number: Rev.*A Page 79 of 95

80 Low-voltage Detection Interrupt Value Parameter Symbol Conditions Uni t Remarks Min Typ Max Detected voltage VDL V When voltage drops SVHI = Released voltage VDH V When voltage rises Detected voltage VDL V When voltage drops SVHI = Released voltage VDH V When voltage rises Detected voltage VDL V When voltage drops SVHI = Released voltage VDH V When voltage rises Detected voltage VDL V When voltage drops SVHI = Released voltage VDH V When voltage rises Detected voltage VDL V When voltage drops SVHI = Released voltage VDH V When voltage rises Detected voltage VDL V When voltage drops SVHI = Released voltage VDH V When voltage rises Detected voltage VDL V When voltage drops SVHI = Released voltage VDH V When voltage rises Detected voltage VDL V When voltage drops SVHI = Released voltage VDH V When voltage rises LVD stabilization wait 8160 T time LVDW μs t CYCP * LVD detection delay T time LVDDL μs *:t CYCP represents the APB1 bus clock cycle time. (Ta = - 40 C to C) Document Number: Rev.*A Page 80 of 95

81 12.7 Flash Memory Write/Erase Characteristics Parameter Sector erase time Large sector Small sector Value Min Typ Max Halfword (16-bit) write time μs Chip erase time s s Unit (V CC = 2.7 V to 5.5 V, Ta = - 40 C to C) Remarks The sector erase time includes the time of writing prior to internal erase. The halfword (16-bit) write time excludes the system-level overhead. The chip erase time includes the time of writing prior to internal erase. Write/erase cycle and data hold time Write/erase cycle Data hold time (year) Remarks 1,000 20* 10,000 10* *: This value was converted from the result of a technology reliability assessment. (This value was converted from the result of a high temperature accelerated test using the Arrhenius equation with the average temperature value being + 85 C). Document Number: Rev.*A Page 81 of 95

82 12.8 Return Time from Low-Power Consumption Mode Return Factor: Interrupt The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the program operation. Return Count Time Parameter Symbol Typ Value* Max Unit SLEEP mode t CYCC μs High-speed CR TIMER mode, Main TIMER mode, t CYCC t CYCC μs PLL TIMER mode Low-speed CR TIMER mode Ticnt μs Sub TIMER mode μs RTC mode, STOP mode μs *: The value depends on the accuracy of built-in CR. The stabilization time of Main clock/sub clock/main PLL clock is not included. (V CC = 2.7V to 5.5V, Ta = - 40 C to C) Remarks Operation example of return from Low-Power consumption mode (by external interrupt*) Ext.INT Interrupt factor accept Active Ticnt Interrupt factor clear by CPU CPU Operation Start *: External interrupt is set to detecting fall edge. Document Number: Rev.*A Page 82 of 95

83 Operation example of return from Low-Power consumption mode (by internal resource interrupt*) Internal Resource INT Interrupt factor accept Active Ticnt Interrupt factor clear by CPU CPU Operation Start *: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode. Notes: The return factor is different in each Low-Power consumption modes. See "Chapter: Low Power Consumption Mode" and "Operations of Standby Modes" in FM0+ Family PERIPHERAL MANUAL. When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption mode transition. See "CHAPTER: Low Power Consumption Mode" in "FM0+ Family PERIPHERAL MANUAL". Document Number: Rev.*A Page 83 of 95

84 Return Factor: Reset The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program operation. Return Count Time Parameter Symbol Typ Value Max* Unit SLEEP mode μs High-speed CR TIMER mode, Main TIMER mode, μs PLL TIMER mode Low-speed CR TIMER mode Trcnt μs Sub TIMER mode μs RTC/STOP mode μs *: The maximum value depends on the accuracy of built-in CR. (V CC = 2.7V to 5.5V, Ta = - 40 C to C) Remarks Operation example of return from Low-Power consumption mode (by INITX) INITX Internal RST RST Active Release Trcnt CPU Operation Start Document Number: Rev.*A Page 84 of 95

85 Operation example of return from low power consumption mode (by internal resource reset*) Internal Resource RST Internal RST RST Active Release Trcnt CPU Operation Start *: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode. Notes: The return factor is different in each Low-Power consumption modes. See "Chapter: Low Power Consumption Mode" and "Operations of Standby Modes" in FM0+ Family PERIPHERAL MANUAL. When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption mode transition. See "CHAPTER: Low Power Consumption Mode" in "FM0+ Family PERIPHERAL MANUAL". The time during the power-on reset/low-voltage detection reset is excluded. See " Power-on Reset Timing " for the detail on the time during the power-on reset/low -voltage detection reset. When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait time or the main PLL clock stabilization wait time. The internal resource reset means the watchdog reset and the CSV reset. Document Number: Rev.*A Page 85 of 95

86 13. Ordering Information Part number S6E1A11B0AGP2 S6E1A12B0AGP2 S6E1A11B0AGN2 S6E1A12B0AGN2 S6E1A11C0AGV2 S6E1A12C0AGV2 S6E1A11C0AGN2 S6E1A12C0AGN2 S6E1A11C0AGF2 S6E1A12C0AGF2 Package Plastic LQFP (0.80 mm pitch), 32 pins (FPT-32P-M30) Plastic QFN (0.50 mm pitch), 32 pins (LCC-32P-M73) Plastic LQFP (0.50 mm pitch), 48 pins (FPT-48P-M49) Plastic QFN (0.50 mm pitch), 48 pins (LCC-48P-M74) Plastic LQFP (0.65 mm pitch), 52 pins (FPT-52P-M02) Document Number: Rev.*A Page 86 of 95

87 14. Package Dimensions Document Number: Rev.*A Page 87 of 95

88 Document Number: Rev.*A Page 88 of 95

89 48-pin plastic LQFP Lead pitch 0.50 mm Package width package length Lead shape Lead bend direction Sealing method 7.00 mm 7.00 mm Gullwing Normal bend Plastic mold Mounting height 1.70 mm MAX (FPT-48P-M49) Weight 0.17 g 48-pin plastic LQFP (FPT-48P-M49) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 9.00± 0.20(.354 ±.008)SQ *7.00± 0.10(.276 ±.004)SQ ± (.006±.002) INDEX 0.08(.003) Details of "A" part (Mounting height) "A" 0 ~8 0.10± 0.10 (.004±.004) (Stand off) (.020) 0.22± 0.05 (.008±.002) 0.08(.003) M 0.60± 0.15 (.024±.006) 0.25(.010) C 2010 FUJITSU SEMICONDUCTOR LIMITED HMbF48-49Sc-1-2 Dimensions in mm (inches). Note: The values in parentheses are reference values. Document Number: Rev.*A Page 89 of 95

90 Document Number: Rev.*A Page 90 of 95

91 Document Number: Rev.*A Page 91 of 95