32-bit ARM Cortex -M4F FM4 Microcontroller

Transcription

1 32-bit ARM Cortex -M4F FM4 Microcontroller Devices in the S6E2C5 Series are highly integrated 32-bit microcontrollers with high performance and competitive cost. This series is based on the ARM Cortex-M4F processor with on-chip flash memory and SRAM. The series has peripherals such as motor control timers, A/D converters, and communications interfaces (USB, CAN, UART, CSIO (SPI), I 2 C, LIN). The products that are described in this data sheet are placed into TYPE3-M4 product categories "FM4 Family Peripheral Manual Main Part ( )." Features 32-bit ARM Cortex-M4F Core Processor version: r0p1 Up to 200 MHz frequency operation FPU built-in Support DSP instructions Memory protection unit (MPU): improves the reliability of an embedded system Integrated nested vectored interrupt controller (NVIC): 1 NMI (non-maskable interrupt) and 128 peripheral interrupts and 16 priority levels 24-bit system timer (Sys Tick): system timer for OS task management On-chip Memories External Bus Interface Supports SRAM, NOR, NAND flash and SDRAM device Up to 9 chip selects CS0 to CS8 (CS8 is only for SDRAM) 8-/16-/32-bit data width Up to 25-bit address bus Maximum Access size: 256M byte Supports address/data multiplexing Supports external RDY function Supports scramble function Possible to set the validity/invalidity of the scramble function for the external areas 0x6000_0000 to 0xDFFF_FFFF in 4 Mbytes units. Possible to set two kinds of the scramble key Note: It is necessary to use the Cypress provided software library to use the scramble function. Flash memory This series is based on two independent on-chip flash memories. Up to 2048 Kbytes Built-in flash accelerator system with 16 Kbytes trace buffer memory Read access to flash memory that can be achieved without wait-cycle up to an operating frequency of 72 MHz. Even at the operating frequency more than 72 MHz, an equivalent single cycle access to flash memory can be obtained by the flash accelerator system. Security function for code protection SRAM This is composed of three independent SRAMs (SRAM0, SRAM1 and SRAM2). SRAM0 is connected to the I-code bus or D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are connected to system bus of Cortex-M4F core. SRAM0: up to 192 Kbytes SRAM1: 32 Kbytes SRAM2: 32 Kbytes USB Interface (Max two Channels) The USB interface is composed of a device and a host. USB device USB 2.0 Full-speed supported Max 6 EndPoint supported EndPoint 0 is control transfer EndPoint 1, 2 can be selected bulk-transfer, interrupt-transfer or isochronous-transfer EndPoint 3 to 5 can select bulk-transfer or interrupt-transfer EndPoint 1 to 5 comprise double buffer The size of each endpoint is as follows. Endpoint 0, 2 to 5: 64 byte EndPoint 1: 256 byte USB host USB2.0 Full-Speed/Low-Speed supported Bulk-transfer, interrupt-transfer, and isochronous-transfer support USB Device connected/dis-connected automatically detect IN/OUT token handshake packet automatically Max 256-byte packet length supported Wake-up function supported Cypress Semiconductor Corporation 198 Champion Court San Jose, CA Document Number: Rev.*B Revised February 20, 2017

2 CAN Interface (Max two Channels) Compatible with CAN specification 2.0A/B Maximum transfer rate: 1 Mbps Built-in 32-message buffer I 2 C Standard mode (Max 100 kbps)/fast mode (Max 400 kbps) supported Fast mode Plus (Fm+) (Max 1000 kbps, only for ch 3 = ch A and ch 7 = ch B) supported CAN-FD Interface (One Channel) Compatible with CAN Specification 2.0A/B Maximum transfer rate: 5 Mbps Message buffer for receiver: up to 192 messages Message buffer for transmitter: up to 32 messages CAN with flexible data rate (non-iso CAN FD) Notes: CAN FD cannot communicate between non-iso CAN FD and ISO CAN FD, because non-iso CAN FD and ISO CAN FD are different frame format. About the problem of "non-iso CAN FD", see the White Paper from CiA(CAN in Automation) _can-fd-and-crc-issued_white-paper_bosch DMA Controller (Eight channels) DMA controller has an independent bus, so the CPU and DMA controller can process simultaneously. Eight independently configured and operated channels Transfer can be started by software or request from the built-in peripherals Transfer address area: 32-bit (4 GB) Transfer mode: Block transfer/burst transfer/demand transfer Transfer data type: bytes/half-word/word Transfer block count: 1 to 16 Number of transfers: 1 to Multi-function Serial Interface (Max 16 channels) Separate 64 byte receive and transmit FIFO buffers for channels 0 to 7. Operation mode is selectable for each channel from the following: UART CSIO (SPI) LIN I 2 C UART Full-duplex double buffer Selection with or without parity supported Built-in dedicated baud rate generator External clock available as a serial clock Various error detect functions available (parity errors, framing errors, and overrun errors) CSIO (SPI) Full-duplex double buffer Built-in dedicated baud rate generator Overrun error detect function available Serial chip select function (ch 6 and ch 7 only) Supports high-speed SPI (ch 4 and ch 6 only) Data length 5 to 16-bit LIN LIN protocol Rev.2.1 supported Full-duplex double buffer Master/slave mode supported LIN break field generation (can change to 13- to 16-bit length) LIN break delimiter generation (can change to 1- to 4-bit length) Various error detect functions available (parity errors, framing errors, and overrun errors) DSTC (Descriptor System data Transfer Controller; 256 Channels) The DSTC can transfer data at high-speed without going via the CPU. The DSTC adopts the descriptor system and, following the specified contents of the descriptor that has already been constructed on the memory, can access directly the memory/peripheral device and perform the data-transfer operation. It supports the software activation, the hardware activation, and the chain activation functions. A/D Converter (Max 32 channels) 12-bit A/D Converter Successive approximation type Built-in three units Conversion time: 0.5 μs at 5 V Priority conversion available (priority at two levels) Scanning conversion mode Built-in FIFO for conversion data storage (for SCAN conversion: 16 steps, for priority conversion: 4 steps) D/A Converter (Max 2 Channels) R-2R type 12-bit resolution Document Number: Rev.*B Page 2 of 201

3 Base Timer (Max 16 Channels) Operation mode is selected from the following for each channel: 16-bit PWM timer 16-bit PPG timer 16-/32-bit reload timer 16-/32-bit PWC timer General Purpose I/O Port This series can use its pins as general purpose I/O ports when they are not used for external bus or peripherals; moreover, the port relocate function is built in. It can set the I/O port to which the peripheral function can be allocated. Capable of pull-up control per pin Capable of reading pin level directly Built-in port-relocate function Up to 120 high-speed general-purpose I/O ports in 144 pin package Some pins 5V tolerant I/O. See 4. Pin Descriptions and 5. I/O Circuit Type for the corresponding pins. Real-Time Clock (RTC) The real-time clock can count year, month, day, hour, minute, second, or day of the week from 00 to 99. Interrupt function with specifying date and time (year/month/day/hour/minute) is available. This function is also available by specifying only year, month, day, hour, or minute. Timer interrupt function after set time or each set time. Capable of rewriting the time with continuing the time count. Leap year automatic count is available. Quadrature Position/Revolution Counter (QPRC; Max four Channels) The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position encoder. It is also possible to use up/down counter. The detection edge of the three external event pins AIN, BIN and ZIN is configurable. 16-bit position counter 16-bit revolution counter Two 16-bit compare registers Multi-function Timer (Max three Units) The multi-function timer is composed of the following blocks: Minimum resolution: 5.00 ns 16-bit free-run timer 3 ch/unit Input capture 4 ch/unit Output compare 6 ch/unit A/D activation compare 6 ch/unit Waveform generator 3 ch/unit 16-bit PPG timer 3 ch/unit The following functions can be used to achieve the motor control: PWM signal output function DC chopper waveform output function Dead time function Input capture function A/D convertor activate function DTIF (motor emergency stop) interrupt function Dual Timer (32-/16-bit Down Counter) The dual timer consists of two programmable 32-/16-bit down counters. Operation mode is selectable from the following for each channel: Free-running Periodic (= Reload) One shot Watch Counter The watch counter is used for wake up from low-power consumption mode. It is possible to select the main clock, sub clock, built-in High-speed CR clock, or built-in low-speed CR clock as the clock source. Interval timer: up to 64 s (max) with a sub clock of khz External Interrupt Controller Unit External interrupt pin: Max 32 pins Include one non-maskable interrupt (NMI) Document Number: Rev.*B Page 3 of 201

4 Watchdog Timer (2 Channels) A watchdog timer can generate interrupts or a reset when a time-out value is reached. This series consists of two different watchdogs: a "hardware" watchdog and a "software" watchdog. The hardware watchdog timer is clocked by low-speed internal CR oscillator. The hardware watchdog is thus active in any power saving mode except RTC mode and Stop mode. Cyclic Redundancy Check (CRC) Accelerator The CRC accelerator helps to verify data transmission or storage integrity. CCITT CRC16 and IEEE CRC32 are supported. CCITT CRC16 generator polynomial: 0x1021 IEEE CRC32 generator polynomial: 0x04C11DB7 Programmable Cyclic Redundancy Check (PRGCRC) Accelerator The CRC accelerator helps a verify data transmission or storage integrity. CCITT CRC16, IEEE CRC32 and generating polynomial are supported. CCITT CRC16 generator polynomial: 0x1021 IEEE CRC32 generator polynomial: 0x04C11DB7 Generating polynomial SD Card Interface It is possible to use the SD card that conforms to the following standards. Part 1 Physical Layer Specification version 3.01 Part E1 SDIO Specification version 3.00 Part A2 SD Host Controller Standard Specification version bit or 4-bit data bus I 2 S (Inter-IC Sound Bus) Interface (TX x 1 channel, RX x 1 channel) Supports three transfer protocols I 2 S Left justified DSP mode Separate clock generation block for flexible system integration options Master/slave mode selectable RX Only, TX Only or TX and RX simultaneous operation selectable Word length is programmable from 7-bits to 32 bits RX/TX FIFO integrated (RX: 66 words x 32-bits, TX: 66 words x 32-bits) DMA, interrupts, or polling based data transfer supported Clock and Reset Clocks Five clock sources (two external oscillators, two internal CR oscillators, and Main PLL) that are dynamically selectable. Main clock: 4 MHz to 48 MHz Sub clock: khz High-speed internal CR clock: 4 MHz Low-speed internal CR clock: 100 khz Main PLL Clock Resets Reset requests from INITX pin Power on reset Software reset Watchdog timer reset Low-voltage detector reset Clock supervisor reset Clock Supervisor (CSV) Clocks generated by internal CR oscillators are used to supervise abnormality of the external clocks. External OSC clock failure (clock stop) is detected, reset is asserted. External OSC frequency anomaly is detected, interrupt or reset is asserted. Low-Voltage Detector (LVD) This Series include two-stage monitoring of voltage on the VCC pins. when the voltage falls below the voltage that has been set, the low-voltage detector function generates an interrupt or reset. LVD1: error reporting via interrupt LVD2: auto-reset operation Document Number: Rev.*B Page 4 of 201

5 Low-power Consumption Mode Six low power consumption modes are supported. Sleep Timer RTC Stop Deep standby RTC (selectable from with/without RAM retention) Deep standby stop (selectable from with/without RAM retention) Peripheral Clock Gating The system can reduce the current consumption of the total system with gating the operation clocks of peripheral functions not used. VBAT The consumption power during the RTC operation can be reduced by supplying the power supply independent from the RTC (calendar circuit)/32 khz oscillation circuit. The following circuits can also be used. RTC 32-kHz oscillation circuit Power-on circuit Back up register: 32 bytes Port circuit Debug Serial wire JTAG debug port (SWJ-DP) Embedded trace macrocells (ETM) provide comprehensive debug and trace facilities. AHB trace macrocells (HTM) Unique ID Unique value of the device (41-bit) is set. Power Supply Four power supplies Wide range voltage: VCC = 2.7 V to 5.5 V Power supply for USB ch 0 I/O: USBVCC0 = 3.0 V to 3.6 V (when USB is used) = 2.7 V to 5.5 V (when GPIO is used) Power supply for USB ch 1 I/O: USBVCC1 = 3.0 V to 3.6 V (when USB is used) = 2.7 V to 5.5 V (when GPIO is used) Power supply for VBAT: VBAT = 1.65 V to 5.5 V Document Number: Rev.*B Page 5 of 201

6 Table of Contents Features Product Lineup Packages Pin Assignments Pin Descriptions I/O Circuit Type Handling Precautions Precautions for Product Design Precautions for Package Mounting Precautions for Use Environment Handling Devices Block Diagram Memory Size Memory Map Pin Status in Each CPU State Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions DC Characteristics Current Rating Pin Characteristics AC Characteristics Main Clock Input Characteristics Sub Clock Input Characteristics Built-In CR Oscillation Characteristics Operating Conditions of Main PLL (in the Case of Using Main Clock for Input Clock of PLL) Operating Conditions of USB PLL I 2 S PLL (in the Case of Using Main Clock for Input Clock of PLL) Operating Conditions of Main PLL (in the Case of Using Built-in High-speed CR Clock for Input Clock of Main PLL) Reset Input Characteristics Power-On Reset Timing GPIO Output Characteristics External Bus Timing Base Timer Input Timing CSIO (SPI) Timing External Input Timing Quadrature Position/Revolution Counter Timing I 2 C Timing SD Card Interface Timing ETM/ HTM Timing JTAG Timing I 2 S Timing High-Speed Quad SPI Timing bit A/D Converter bit D/A Converter USB Characteristics Document Number: Rev.*B Page 6 of 201

7 12.8 Low-Voltage Detection Characteristics Low-Voltage Detection Reset Interrupt of Low-Voltage Detection MainFlash Memory Write/Erase Characteristics Dual Flash Memory Write/Erase Characteristics Standby Recovery Time Recovery cause: Interrupt/WKUP Recovery Cause: Reset Ordering Information Package Dimensions Major Changes Document History Sales, Solutions, and Legal Information Document Number: Rev.*B Page 7 of 201

8 1. Product Lineup Memory Size Product Name S6E2C58H/J/L S6E2C59H/J/L S6E2C5AH/J/L On-chip flash memory 1024 Kbytes 1536 Kbytes 2048 Kbytes On-chip SRAM 128 Kbytes 192 Kbytes 256 Kbytes SRAM0 64 Kbytes 128 Kbytes 192 Kbytes SRAM1 32 Kbytes 32 Kbytes 32 Kbytes SRAM2 32 Kbytes 32 Kbytes 32 Kbytes Function Product Name S6E2C58H0A S6E2C59H0A S6E2C5AH0A S6E2C58J0A S6E2C59J0A S6E2C5AJ0A S6E2C58L0A S6E2C59L0A S6E2C5AL0A Pin count / CPU Cortex-M4F, MPU, NVIC 128 ch Freq. 200 MHz Power supply voltage range 2.7V to 5.5V USB2.0 (device/host) 2 ch CAN 2 ch (Max) CAN-FD (non-iso CAN FD) 1 ch DMAC 8ch DSTC 256 ch External bus interface Addr: 25-bit (Max), Data: 8-/16-bit CS: 9 (Max), SRAM, NOR flash NAND flash Addr: 25-bit (Max), Data: 8-/16-bit CS: 9 (Max), SRAM, NOR flash, NAND flash SDRAM Addr: 25-bit (Max), Data: 8-/16-/32-bit CS: 9 (Max), SRAM, NOR flash, NAND flash, SDRAM Multi-function serial interface (UART/CSIO/LIN/I 2 C) 16ch (Max) ch 0 to ch 7:FIFO, ch 8 to ch 15:No FIFO Base timer (PWC/Reload timer/pwm/ppg) 16 ch (Max) A/D activation compare 6 ch Input capture 4 ch Free-run timer 3 ch Output compare 6 ch 3 units (Max) Waveform generator 3 ch PPG 3 ch SD card interface 1 unit I 2 S - 1 unit High-speed quad SPI - 1 unit QPRC 4 ch (Max) Dual timer 1 unit Real-time clock 1 unit Watch counter 1 unit CRC accelerator Yes (fixed, programmable) Watchdog timer 1 ch (SW) + 1 ch (HW) External interrupts 32 pins (Max)+ NMI 1 I/O ports 120 pins (Max) 152 pins (Max) 190 pins (Max) 12-bit A/D converter 24 ch (3 units) 32 ch (3 units) 12-bit D/A converter 2 units (Max) CSV (clock supervisor) Yes LVD (low-voltage detector) 2 ch MF timer Document Number: Rev.*B Page 8 of 201

9 Built-in CR Debug function Unique ID Product Name High-speed Low-speed S6E2C58H0A S6E2C59H0A S6E2C5AH0A S6E2C58J0A S6E2C59J0A S6E2C5AJ0A 4 MHz 100 khz SWJ-DP/ETM/HTM Yes Notes: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use the port relocate function of the I/O port according to your function use. See Built-In CR Oscillation Characteristics for the accuracy of the built-in CR. S6E2C58L0A S6E2C59L0A S6E2C5AL0A Document Number: Rev.*B Page 9 of 201

10 2. Packages Package Product Name S6E2C58H0A S6E2C59H0A S6E2C5AH0A S6E2C58J0A S6E2C59J0A S6E2C5AJ0A S6E2C58L0A S6E2C59L0A S6E2C5AL0A LQFP: LQS144 (0.5-mm pitch) - - LQFP: LQP176 (0.5-mm pitch) - - BGA : LBE192 (0.8-mm pitch) - - LQFP: LQQ216 (0.4-mm pitch) - - : Supported Note: See 14. Package Dimensions for detailed information on each package. Document Number: Rev.*B Page 10 of 201

11 3. Pin Assignments LQS144 (Top View) VSS P81/UDP0 P80/UDM0 USBVCC0 P60/SIN4_0/INT31_0/WKUP3 P61/UHCONX0/SOT4_0/MALE_0/RTCCO_0/SUBOUT_0 P62/SCK4_0/MWEX_0 P63/ADTG_3/RTS4_0/INT30_0/MOEX_0 P6E/ADTG_5/SCK4_1/IC23_1/INT29_0 PD2/CTS4_1/FRCK2_1 PD1/INT31_1 PD0/INT30_1 PCF/RTS4_1/INT12_0 PCE/SIN4_1/INT15_0 PCD/SOT4_1/INT14_0 PCC PCB/INT28_0 VSS VCC PCA/TIOA15_0 PC9/TIOB15_0 PC8 PC7/INT13_0/CROUT_1 PC6/TIOA14_0 PC5/TIOB14_0 PC4/TIOA7_0 PC3/TIOB7_0 PC2/TIOA6_0 PC1/TIOB6_0 PC0 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX VCC VCC VSS PA0/RTO20_0/TIOA8_0/AIN2_0/INT00_0/MADATA00_ P83/UDP1 PA1/RTO21_0/TIOA9_0/BIN2_0/MADATA01_ P82/UDM1 PA2/RTO22_0/TIOA10_0/ZIN2_0/MADATA02_ USBVCC1 PA3/RTO23_0/TIOA11_0/MADATA03_ P20/NMIX/WKUP0 PA4/RTO24_0/TIOA12_0/MADATA04_ P21/ADTG_4/SIN0_0/INT27_0/CROUT_0 PA5/SIN1_0/RTO25_0/TIOA13_0/INT01_0/MADATA05_ P22/AN31/SOT0_0/INT26_0 PA6/SOT1_0/DTTI2X_0/MADATA06_ P23/UHCONX1/AN30/SCK0_0/TIOB13_1 PA7/SCK1_0/IC20_0/MADATA07_ P24/AN29/TIOA13_1/MAD18_0 PA8/SIN7_0/IC21_0/INT02_0/WKUP1/MADATA08_ P25/AN28/RX1_0/INT25_0/MAD17_0 PA9/SOT7_0/IC22_0/MADATA09_ P26/TX1_0/MAD16_0 PAA/SCK7_0/IC23_0/MADATA10_ P27/AN27/SIN5_0/INT24_0/MAD15_0 PAB/SCS70_0/RX0_0/FRCK2_0/INT03_0/MADATA11_ P28/AN26/SOT5_0/MAD14_0 PAC/SCS71_0/TX0_0/TIOB8_0/AIN3_0/MADATA12_ P29/AN25/SCK5_0/MAD13_0 PAD/SCK3_0/TIOB9_0/BIN3_0/MADATA13_ P2A/AN24/CTS5_0/MAD12_0 PAE/ADTG_0/SOT3_0/TIOB10_0/ZIN3_0/MADATA14_ P1F/AN15/RTS5_0/TIOB8_1/INT27_1/MAD11_0 PAF/SIN3_0/TIOB11_0/INT16_0/MADATA15_ P1E/AN14/TIOA8_1/INT26_1/MAD10_0 LQFP P08/SIN14_0/TIOB12_0/INT17_0/MDQM0_ P1D/AN13/SCK12_0/TIOB5_2/TRACED3 P09/SOT14_0/TIOB13_0/INT18_0/MDQM1_ P1C/AN12/SOT12_0/TIOA5_2/TRACED2 P0A/ADTG_1/SCK14_0/AIN2_1/MCLKOUT_ P1B/AN11/SIN12_0/TIOB4_2/INT11_0/TRACED1 P32/BIN2_1/INT19_0/S_DATA1_ P1A/AN10/SCK2_0/TIOA4_2/TRACED0 P33/FRCK0_0/ZIN2_1/S_DATA0_ P19/AN09/SOT2_0/TIOB3_2/INT24_1/TRACECLK P34/IC03_0/INT00_1/S_CLK_ P18/AN08/SIN2_0/TIOA3_2/INT10_0 VCC P17/AN07/SCK11_0/TIOB2_2/ZIN1_2 VSS P16/AN06/SOT11_0/TIOA2_2/BIN1_2 P35/IC02_0/INT01_1/S_CMD_ P15/AN05/SIN11_0/TIOB1_2/AIN1_2/INT09_0 P36/IC01_0/INT02_1/S_DATA3_ P14/AN04/SOT6_1/TX1_1 P37/IC00_0/INT03_1/S_DATA2_ P13/AN03/SIN6_1/RX1_1/INT25_1 P38/ADTG_2/DTTI0X_0/S_WP_ P12/AN02/SCK10_0/TIOA1_2/ZIN0_2 P39/SIN2_1/RTO00_0/TIOA0_1/AIN3_1/INT16_1/S_CD_0/MAD24_ P11/AN01/SOT10_0/TIOB0_2/BIN0_2 P3A/SOT2_1/RTO01_0/TIOA1_1/BIN3_1/INT17_1/MAD23_ P10/AN00/SIN10_0/TIOA0_2/AIN0_2/INT08_0 P3B/SCK2_1/RTO02_0/TIOA2_1/ZIN3_1/INT18_1/MAD22_0/MNALE_ AVRH P3C/SIN13_0/RTO03_0/TIOA3_1/INT19_1/MAD21_0/MNCLE_ AVRL P3D/SOT13_0/RTO04_0/TIOA4_1/MAD20_0/MNWEX_ AVSS P3E/SCK13_0/RTO05_0/TIOA5_1/MAD19_0/MNREX_ AVCC VSS VCC VCC P40/SIN3_1/RTO10_0/TIOA0_0/AIN0_0/INT23_0/MCSX7_0 P41/SOT3_1/RTO11_0/TIOA1_0/BIN0_0/MCSX6_0 P42/SCK3_1/RTO12_0/TIOA2_0/ZIN0_0/MCSX5_0 P43/SIN15_0/RTO13_0/TIOA3_0/INT04_0/MCSX4_0 P44/SOT15_0/RTO14_0/TIOA4_0/MCSX3_0 P45/SCK15_0/RTO15_0/TIOA5_0/MCSX2_0 C VSS VCC P7D/SCK1_1/RX2_0/DTTI1X_0/INT05_0/WKUP2/MCSX1_0 P7E/ADTG_7/TX2_0/FRCK1_0/MCSX0_0 INITX P46/X0A P47/X1A VBAT P48/VREGCTL P49/VWAKEUP P70/ADTG_8/SIN1_1/INT06_0/MRDY_0 P71/SOT1_1/MAD00_0 P72/SIN9_0/TIOB0_0/INT07_0/MAD01_0 P73/SOT9_0/TIOB1_0/MAD02_0 P74/SCK9_0/TIOB2_0/MAD03_0 P75/SIN8_0/TIOB3_0/AIN1_0/INT20_0/MAD04_0 P76/SOT8_0/TIOB4_0/BIN1_0/MAD05_0 P77/SCK8_0/TIOB5_0/ZIN1_0/MAD06_0 P78/SIN6_0/IC10_0/INT21_0/MAD07_0 P79/SOT6_0/IC11_0/MAD08_0 P7A/SCK6_0/IC12_0/MAD09_0 P7B/DA1/SCS60_0/IC13_0/INT22_0 P7C/DA0/SCS61_0/INT04_1 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS Note: The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: Rev.*B Page 11 of 201

12 LQP176 (Top View) VSS P81/UDP0 P80/UDM0 USBVCC0 P60/SIN4_0/INT31_0/WKUP3 P61/UHCONX0/SOT4_0/MALE_0/RTCCO_0/SUBOUT_0 P62/SCK4_0/MWEX_0 P63/ADTG_3/RTS4_0/INT30_0/MOEX_0 P64/CTS4_0/RTO25_1/INT29_1 P65/RTO24_1/INT28_1 P6E/ADTG_5/SCK4_1/IC23_1/INT29_0 PD2/CTS4_1/FRCK2_1 PD1/INT31_1 PD0/INT30_1 PCF/RTS4_1/INT12_0 PCE/SIN4_1/INT15_0 PCD/SOT4_1/INT14_0 PCC PCB/INT28_0 VSS VCC PCA/TIOA15_0 PC9/TIOB15_0 PC8 PC7/INT13_0/CROUT_1 PC6/TIOA14_0 PC5/TIOB14_0 PC4/TIOA7_0 PC3/TIOB7_0 PC2/TIOA6_0 PC1/TIOB6_0 PC0 P95/RTS5_1/Q_CS0_0 P94/CTS5_1/Q_SCK_0 P93/SCK5_1/INT15_1/Q_IO0_0 P92/SOT5_1/INT14_1/Q_IO1_0 P91/SIN5_1/INT13_1/Q_IO2_0 P90/INT12_1/Q_IO3_0 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX VCC VCC VSS PA0/RTO20_0/TIOA8_0/AIN2_0/INT00_0/MADATA00_ P83/UDP1 PA1/RTO21_0/TIOA9_0/BIN2_0/MADATA01_ P82/UDM1 PA2/RTO22_0/TIOA10_0/ZIN2_0/MADATA02_ USBVCC1 PA3/RTO23_0/TIOA11_0/MADATA03_ P20/NMIX/WKUP0 PA4/RTO24_0/TIOA12_0/MADATA04_ P21/ADTG_4/SIN0_0/INT27_0/CROUT_0 PA5/SIN1_0/RTO25_0/TIOA13_0/INT01_0/MADATA05_ P22/AN31/SOT0_0/INT26_0 PA6/SOT1_0/DTTI2X_0/MADATA06_ P23/UHCONX1/AN30/SCK0_0/TIOB13_1 PA7/SCK1_0/IC20_0/MADATA07_ P24/AN29/TIOA13_1/MAD18_0 P50/SCS72_0/RTO00_1/TIOA8_ P25/AN28/RX1_0/INT25_0/MAD17_0 P51/SCS73_0/RTO01_1/TIOB8_ P26/TX1_0/MAD16_0 P52/RTO02_1/TIOA9_ P27/AN27/SIN5_0/INT24_0/MAD15_0 PA8/SIN7_0/IC21_0/INT02_0/WKUP1/MADATA08_ P28/AN26/SOT5_0/MAD14_0 PA9/SOT7_0/IC22_0/MADATA09_ P29/AN25/SCK5_0/MAD13_0 PAA/SCK7_0/IC23_0/MADATA10_ P2A/AN24/CTS5_0/MAD12_0 PAB/SCS70_0/RX0_0/FRCK2_0/INT03_0/MADATA11_ P1F/AN15/RTS5_0/TIOB8_1/INT27_1/MAD11_0 PAC/SCS71_0/TX0_0/TIOB8_0/AIN3_0/MADATA12_ P1E/AN14/TIOA8_1/INT26_1/MAD10_0 PAD/SCK3_0/TIOB9_0/BIN3_0/MADATA13_ PB7/AN23/TIOB12_1/TRACED7 PAE/ADTG_0/SOT3_0/TIOB10_0/ZIN3_0/MADATA14_ PB6/AN22/SCK8_1/TIOA12_1/TRACED6 PAF/SIN3_0/TIOB11_0/INT16_0/MADATA15_ PB5/AN21/SOT8_1/TIOB11_1/INT11_1/TRACED5 P08/SIN14_0/TIOB12_0/INT17_0/MDQM0_ PB4/AN20/SIN8_1/TIOA11_1/INT10_1/TRACED4 LQFP P09/SOT14_0/TIOB13_0/INT18_0/MDQM1_ P1D/AN13/SCK12_0/TIOB5_2/TRACED3 P0A/ADTG_1/SCK14_0/AIN2_1/MCLKOUT_ P1C/AN12/SOT12_0/TIOA5_2/TRACED2 P30/RX0_1/TIOA13_2/INT03_2/I2SDI0_ P1B/AN11/SIN12_0/TIOB4_2/INT11_0/TRACED1 P31/TX0_1/TIOB13_2/I2SCK0_ P1A/AN10/SCK2_0/TIOA4_2/TRACED0 P32/BIN2_1/INT19_0/S_DATA1_ P19/AN09/SOT2_0/TIOB3_2/INT24_1/TRACECLK P33/FRCK0_0/ZIN2_1/S_DATA0_ P18/AN08/SIN2_0/TIOA3_2/INT10_0 P34/IC03_0/INT00_1/S_CLK_ PB3/AN19/SCS62_1/TIOB10_1 VCC PB2/AN18/SCS61_1/TIOA10_1/INT09_1 VSS PB1/AN17/SCS60_1/TIOB9_1/INT08_1 P35/IC02_0/INT01_1/S_CMD_ PB0/AN16/SCK6_1/TIOA9_1 P36/IC01_0/INT02_1/S_DATA3_ P17/AN07/SCK11_0/TIOB2_2/ZIN1_2 P37/IC00_0/INT03_1/S_DATA2_ P16/AN06/SOT11_0/TIOA2_2/BIN1_2 P38/ADTG_2/DTTI0X_0/S_WP_ P15/AN05/SIN11_0/TIOB1_2/AIN1_2/INT09_0 P39/SIN2_1/RTO00_0/TIOA0_1/AIN3_1/INT16_1/S_CD_0/MAD24_ P14/AN04/SOT6_1/TX1_1 P3A/SOT2_1/RTO01_0/TIOA1_1/BIN3_1/INT17_1/MAD23_ P13/AN03/SIN6_1/RX1_1/INT25_1 P3B/SCK2_1/RTO02_0/TIOA2_1/ZIN3_1/INT18_1/MAD22_0/MNALE_ P12/AN02/SCK10_0/TIOA1_2/ZIN0_2 P3C/SIN13_0/RTO03_0/TIOA3_1/INT19_1/MAD21_0/MNCLE_ P11/AN01/SOT10_0/TIOB0_2/BIN0_2 P3D/SOT13_0/RTO04_0/TIOA4_1/MAD20_0/MNWEX_ P10/AN00/SIN10_0/TIOA0_2/AIN0_2/INT08_0 P3E/SCK13_0/RTO05_0/TIOA5_1/MAD19_0/MNREX_ AVRH P5D/SIN10_1/TIOB11_2/INT01_2/I2SMCLK0_ AVRL P5E/SOT10_1/TIOA12_2/I2SDO0_ AVSS P5F/SCK10_1/TIOB12_2/I2SWS0_ AVCC VSS VCC VCC P40/SIN3_1/RTO10_0/TIOA0_0/AIN0_0/INT23_0/MCSX7_0 P41/SOT3_1/RTO11_0/TIOA1_0/BIN0_0/MCSX6_0 P42/SCK3_1/RTO12_0/TIOA2_0/ZIN0_0/MCSX5_0 P43/SIN15_0/RTO13_0/TIOA3_0/INT04_0/MCSX4_0 P44/SOT15_0/RTO14_0/TIOA4_0/MCSX3_0 P45/SCK15_0/RTO15_0/TIOA5_0/MCSX2_0 C VSS VCC P7D/SCK1_1/RX2_0/DTTI1X_0/INT05_0/WKUP2/MCSX1_0 P7E/ADTG_7/TX2_0/FRCK1_0/MCSX0_0 INITX P46/X0A P47/X1A VBAT P48/VREGCTL P49/VWAKEUP PF0/SCS63_0/RX2_1/FRCK1_1/TIOA15_1/INT22_1 PF1/SCS62_0/TX2_1/TIOB15_1/INT23_1 P70/ADTG_8/SIN1_1/INT06_0/MRDY_0 P71/SOT1_1/MAD00_0 P72/SIN9_0/TIOB0_0/INT07_0/MAD01_0 P73/SOT9_0/TIOB1_0/MAD02_0 P74/SCK9_0/TIOB2_0/MAD03_0 PF2/RTO10_1/TIOA6_1/MRASX_0 PF3/RTO11_1/TIOB6_1/INT05_1/MCASX_0 PF4/RTO12_1/TIOA7_1/INT06_1/MSDWEX_0 PF5/RTO13_1/TIOB7_1/INT07_1/MCSX8_0 PF6/RTO14_1/TIOA14_1/INT20_1/MSDCKE_0 PF7/RTO15_1/TIOB14_1/INT21_1/MSDCLK_0 P75/SIN8_0/TIOB3_0/AIN1_0/INT20_0/MAD04_0 P76/SOT8_0/TIOB4_0/BIN1_0/MAD05_0 P77/SCK8_0/TIOB5_0/ZIN1_0/MAD06_0 P78/SIN6_0/IC10_0/INT21_0/MAD07_0 P79/SOT6_0/IC11_0/MAD08_0 P7A/SCK6_0/IC12_0/MAD09_0 P7B/DA1/SCS60_0/IC13_0/INT22_0 P7C/DA0/SCS61_0/INT04_1 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS Note: The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: Rev.*B Page 12 of 201

13 LQQ216 (Top View) VSS P81/UDP0 P80/UDM0 USBVCC0 P60/SIN4_0/INT31_0/WKUP3 P61/UHCONX0/SOT4_0/MALE_0/RTCCO_0/SUBOUT_0 P62/SCK4_0/MWEX_0 P63/ADTG_3/RTS4_0/INT30_0/MOEX_0 P64/CTS4_0/RTO25_1/INT29_1 P65/RTO24_1/INT28_1 P66/SIN13_1/RTO23_1/TIOA15_2/INT15_2 P67/SOT13_1/RTO22_1/TIOB15_2 P68/SCK13_1/RTO21_1/TIOA14_2 P69/RTO20_1/TIOB14_2 P6A/DTTI2X_1/TIOA7_2 P6B/SIN14_1/IC20_1/TIOB7_2/INT14_2 P6C/SOT14_1/IC21_1/TIOA6_2 P6D/SCK14_1/IC22_1/TIOB6_2 P6E/ADTG_5/SCK4_1/IC23_1/INT29_0 PD2/CTS4_1/FRCK2_1 PD1/INT31_1 PD0/INT30_1 PCF/RTS4_1/INT12_0 PCE/SIN4_1/INT15_0 PCD/SOT4_1/INT14_0 PCC PCB/INT28_0 VSS VCC PCA/TIOA15_0 PC9/TIOB15_0 PC8 PC7/INT13_0/CROUT_1 PC6/TIOA14_0 PC5/TIOB14_0 PC4/TIOA7_0 PC3/TIOB7_0 PC2/TIOA6_0 PC1/TIOB6_0 PC0 P97/TX0_2/INT13_2/Q_CS2_0 P96/RX0_2/INT12_2/Q_CS1_0 P95/RTS5_1/Q_CS0_0 P94/CTS5_1/Q_SCK_0 P93/SCK5_1/INT15_1/Q_IO0_0 P92/SOT5_1/INT14_1/Q_IO1_0 P91/SIN5_1/INT13_1/Q_IO2_0 P90/INT12_1/Q_IO3_0 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX VCC VCC VSS PA0/RTO20_0/TIOA8_0/AIN2_0/INT00_0/MADATA00_ P83/UDP1 PA1/RTO21_0/TIOA9_0/BIN2_0/MADATA01_ P82/UDM1 PA2/RTO22_0/TIOA10_0/ZIN2_0/MADATA02_ USBVCC1 PA3/RTO23_0/TIOA11_0/MADATA03_ P20/NMIX/WKUP0 PA4/RTO24_0/TIOA12_0/MADATA04_ P21/ADTG_4/SIN0_0/INT27_0/CROUT_0 PA5/SIN1_0/RTO25_0/TIOA13_0/INT01_0/MADATA05_ P22/AN31/SOT0_0/INT26_0 PA6/SOT1_0/DTTI2X_0/MADATA06_ P23/UHCONX1/AN30/SCK0_0/TIOB13_1 PA7/SCK1_0/IC20_0/MADATA07_ P24/AN29/TIOA13_1/MAD18_0 P50/SCS72_0/RTO00_1/TIOA8_2/MADATA16_ P25/AN28/RX1_0/INT25_0/MAD17_0 P51/SCS73_0/RTO01_1/TIOB8_2/MADATA17_ P26/TX1_0/MAD16_0 P52/RTO02_1/TIOA9_2/MADATA18_ PBF/SIN0_1/ZIN3_2/INT11_2/TRACED15 P53/RTO03_1/TIOB9_2/MADATA19_ PBE/SOT0_1/BIN3_2/TRACED14 PA8/SIN7_0/IC21_0/INT02_0/WKUP1/MADATA08_ PBD/SCK0_1/RX1_2/AIN3_2/INT10_2/TRACED13 PA9/SOT7_0/IC22_0/MADATA09_ PBC/TX1_2/TRACED12 PAA/SCK7_0/IC23_0/MADATA10_ P27/AN27/SIN5_0/INT24_0/MAD15_0 PAB/SCS70_0/RX0_0/FRCK2_0/INT03_0/MADATA11_ P28/AN26/SOT5_0/MAD14_0 PAC/SCS71_0/TX0_0/TIOB8_0/AIN3_0/MADATA12_ P29/AN25/SCK5_0/MAD13_0 P54/SIN15_1/RTO04_1/TIOA10_2/INT00_2/MADATA20_ P2A/AN24/CTS5_0/MAD12_0 P55/SOT15_1/RTO05_1/TIOB10_2/MADATA21_ P1F/AN15/RTS5_0/TIOB8_1/INT27_1/MAD11_0 P56/SCK15_1/DTTI0X_1/TIOB0_1/MADATA22_ P1E/AN14/TIOA8_1/INT26_1/MAD10_0 P57/IC00_1/TIOB1_1/MADATA23_ PB7/AN23/TIOB12_1/TRACED7 PAD/SCK3_0/TIOB9_0/BIN3_0/MADATA13_ PB6/AN22/SCK8_1/TIOA12_1/TRACED6 PAE/ADTG_0/SOT3_0/TIOB10_0/ZIN3_0/MADATA14_ PB5/AN21/SOT8_1/TIOB11_1/INT11_1/TRACED5 PAF/SIN3_0/TIOB11_0/INT16_0/MADATA15_ PB4/AN20/SIN8_1/TIOA11_1/INT10_1/TRACED4 P58/SIN11_1/IC01_1/TIOB2_1/INT02_2/MADATA24_ VCC P59/SOT11_1/IC02_1/TIOB3_1/MADATA25_ VSS P5A/SCK11_1/IC03_1/TIOB4_1/MADATA26_ P1D/AN13/SCK12_0/TIOB5_2/TRACED3 P5B/FRCK0_1/TIOB5_1/MADATA27_ P1C/AN12/SOT12_0/TIOA5_2/TRACED2 P08/SIN14_0/TIOB12_0/INT17_0/MDQM0_ P1B/AN11/SIN12_0/TIOB4_2/INT11_0/TRACED1 P09/SOT14_0/TIOB13_0/INT18_0/MDQM1_ P1A/AN10/SCK2_0/TIOA4_2/TRACED0 P0A/ADTG_1/SCK14_0/AIN2_1/MCLKOUT_ P19/AN09/SOT2_0/TIOB3_2/INT24_1/TRACECLK P5C/TIOA11_2/MADATA28_0/RTCCO_1/SUBOUT_ P18/AN08/SIN2_0/TIOA3_2/INT10_0 P30/RX0_1/TIOA13_2/INT03_2/MDQM2_0/I2SDI0_ PB3/AN19/SCS62_1/TIOB10_1 P31/TX0_1/TIOB13_2/MDQM3_0/I2SCK0_ PB2/AN18/SCS61_1/TIOA10_1/INT09_1 P32/BIN2_1/INT19_0/S_DATA1_ PB1/AN17/SCS60_1/TIOB9_1/INT08_1 P33/FRCK0_0/ZIN2_1/S_DATA0_ PB0/AN16/SCK6_1/TIOA9_1 P34/IC03_0/INT00_1/S_CLK_ P17/AN07/SCK11_0/TIOB2_2/ZIN1_2 VCC P16/AN06/SOT11_0/TIOA2_2/BIN1_2 VSS P15/AN05/SIN11_0/TIOB1_2/AIN1_2/INT09_0 P35/IC02_0/INT01_1/S_CMD_ PBB/SCK9_1/ZIN2_2/TRACED11 P36/IC01_0/INT02_1/S_DATA3_ PBA/SOT9_1/BIN2_2/TRACED10 P37/IC00_0/INT03_1/S_DATA2_ PB9/SIN9_1/AIN2_2/INT09_2/TRACED9 P38/ADTG_2/DTTI0X_0/S_WP_ PB8/ADTG_6/SCS63_1/INT08_2/TRACED8 P39/SIN2_1/RTO00_0/TIOA0_1/AIN3_1/INT16_1/S_CD_0/MAD24_ P14/AN04/SOT6_1/TX1_1 P3A/SOT2_1/RTO01_0/TIOA1_1/BIN3_1/INT17_1/MAD23_ P13/AN03/SIN6_1/RX1_1/INT25_1 P3B/SCK2_1/RTO02_0/TIOA2_1/ZIN3_1/INT18_1/MAD22_0/MNALE_ P12/AN02/SCK10_0/TIOA1_2/ZIN0_2 P3C/SIN13_0/RTO03_0/TIOA3_1/INT19_1/MAD21_0/MNCLE_ P11/AN01/SOT10_0/TIOB0_2/BIN0_2 P3D/SOT13_0/RTO04_0/TIOA4_1/MAD20_0/MNWEX_ P10/AN00/SIN10_0/TIOA0_2/AIN0_2/INT08_0 P3E/SCK13_0/RTO05_0/TIOA5_1/MAD19_0/MNREX_ AVRH P5D/SIN10_1/TIOB11_2/INT01_2/MADATA29_0/I2SMCLK0_ AVRL P5E/SOT10_1/TIOA12_2/MADATA30_0/I2SDO0_ AVSS P5F/SCK10_1/TIOB12_2/MADATA31_0/I2SWS0_ AVCC VSS VCC VCC P40/SIN3_1/RTO10_0/TIOA0_0/AIN0_0/INT23_0/MCSX7_0 P41/SOT3_1/RTO11_0/TIOA1_0/BIN0_0/MCSX6_0 P42/SCK3_1/RTO12_0/TIOA2_0/ZIN0_0/MCSX5_0 P43/SIN15_0/RTO13_0/TIOA3_0/INT04_0/MCSX4_0 P44/SOT15_0/RTO14_0/TIOA4_0/MCSX3_0 P45/SCK15_0/RTO15_0/TIOA5_0/MCSX2_ C LQFP VSS VCC P4A/SIN12_1/AIN0_1/INT04_2 P4B/SOT12_1/BIN0_1 P4C/SCK12_1/ZIN0_1 P4D/SCS72_1/RX2_2/INT05_2 P4E/SCS73_1/TX2_2 P7D/SCK1_1/RX2_0/DTTI1X_0/INT05_0/WKUP2/MCSX1_0 P7E/ADTG_7/TX2_0/FRCK1_0/MCSX0_0 INITX P46/X0A P47/X1A VBAT P48/VREGCTL P49/VWAKEUP PF0/SCS63_0/RX2_1/FRCK1_1/TIOA15_1/INT22_1 PF1/SCS62_0/TX2_1/TIOB15_1/INT23_1 P70/ADTG_8/SIN1_1/INT06_0/MRDY_0 P71/SOT1_1/MAD00_0 P72/SIN9_0/TIOB0_0/INT07_0/MAD01_0 P73/SOT9_0/TIOB1_0/MAD02_0 P74/SCK9_0/TIOB2_0/MAD03_0 PF2/RTO10_1/TIOA6_1/MRASX_0 PF3/RTO11_1/TIOB6_1/INT05_1/MCASX_0 PF4/RTO12_1/TIOA7_1/INT06_1/MSDWEX_0 PF5/RTO13_1/TIOB7_1/INT07_1/MCSX8_0 PF6/RTO14_1/TIOA14_1/INT20_1/MSDCKE_0 PF7/RTO15_1/TIOB14_1/INT21_1/MSDCLK_0 P75/SIN8_0/TIOB3_0/AIN1_0/INT20_0/MAD04_0 P76/SOT8_0/TIOB4_0/BIN1_0/MAD05_0 P77/SCK8_0/TIOB5_0/ZIN1_0/MAD06_0 PF8/SCS70_1/DTTI1X_1/AIN1_1 PF9/SCS71_1/IC10_1/BIN1_1 P78/SIN6_0/IC10_0/INT21_0/MAD07_0 P79/SOT6_0/IC11_0/MAD08_0 P7A/SCK6_0/IC12_0/MAD09_0 P7B/DA1/SCS60_0/IC13_0/INT22_0 P7C/DA0/SCS61_0/INT04_1 PFA/SCK7_1/IC11_1/ZIN1_1 PFB/SOT7_1/IC12_1/INT07_2 PFC/SIN7_1/IC13_1/INT06_2 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS Note: The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: Rev.*B Page 13 of 201

14 LBE192 (Top View) A UDP0 UDM0 USBV CC0 VSS PCD PCB VSS VCC PC8 VSS TCK VCC B VSS PA0 P60 P62 P64 PD1 PCA PC1 P95 P92 TDO TMS TRSTX VSS C VCC PA1 PA2 P61 P63 PD2 PCC PC5 PC0 P93 P90 TDI P20 UDP1 D PA5 PA4 PA6 PA7 PA3 P6E PCE PC6 PC2 P94 P91 P22 P21 UDM1 E VSS P50 P51 P52 PA8 P65 PCF PC7 PC3 P26 P25 P24 P23 USBV CC1 F PA9 PAA PAB PAC PAD PAE PD0 PC9 PC4 P2A P29 P28 P27 PB5 G VSS PAF P08 P09 P0A P30 VSS VSS P1F P1E PB7 PB6 PB4 P1B H VCC P32 P34 P31 VSS P35 VSS VSS P18 PB2 P1D P19 P1C P1A J P33 P39 P38 P37 P36 P71 VSS P74 PB1 PB0 P17 P16 P15 PB3 K P3A P3B P3C P3D PF0 PF1 VSS P73 P75 P79 P14 P12 P11 P13 L P3E P5D P5E P43 P7D P70 VSS P72 PF7 P78 P10 AVRH AVRL VSS M VSS P5F P42 P44 P7E P49 VSS PF3 PF6 P7A P7C AVSS AVCC VCC N VCC P40 P41 P45 INITX P48 VSS PF2 PF4 P77 P7B MD0 MD1 VSS P C VSS VCC X0A X1A VSS VBAT PF5 P76 VSS X0 X1 PFBGA-192 Note: The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: Rev.*B Page 14 of 201

15 4. Pin Descriptions List of Pin Functions The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin No LQQ216 LQP176 LQS144 LBE192 Pin Name I/O circuit type Pin state type C1 VCC - - PA B2 RTO20_0 (PPG20_0) TIOA8_0 AIN2_0 INT00_0 MADATA00_0 G K PA C2 RTO21_0 (PPG20_0) TIOA9_0 BIN2_0 MADATA01_0 G I PA C3 RTO22_0 (PPG22_0) TIOA10_0 ZIN2_0 MADATA02_0 G I PA D5 RTO23_0 (PPG22_0) TIOA11_0 MADATA03_0 G I PA D2 RTO24_0 (PPG24_0) TIOA12_0 MADATA04_0 G I PA D1 SIN1_0 RTO25_0 (PPG24_0) TIOA13_0 INT01_0 G K MADATA05_0 Document Number: Rev.*B Page 15 of 201

16 Pin No LQQ216 LQP176 LQS144 LBE D D E E E E F F F3 Pin Name PA6 SOT1_0 (SDA1_0)) DTTI2X_0 MADATA06_0 PA7 SCK1_0 (SCL1_0) IC20_0 MADATA07_0 P50 SCS72_0 RTO00_1 (PPG00_1) TIOA8_2 MADATA16_0 P51 SCS73_0 RTO01_1 (PPG00_1) TIOB8_2 MADATA17_0 P52 RTO02_1 (PPG02_1) TIOA9_2 MADATA18_0 P53 RTO03_1 (PPG02_1) TIOB9_2 MADATA19_0 PA8 SIN7_0 IC21_0 INT02_0 WKUP1 MADATA08_0 PA9 SOT7_0 (SDA7_0) IC22_0 MADATA09_0 PAA SCK7_0 (SCL7_0) IC23_0 MADATA10_0 PAB SCS70_0 RX0_0 FRCK2_0 INT03_0 MADATA11_0 I/O circuit type E E E E E E I N N E Pin state type I I I I I I Q I I K Document Number: Rev.*B Page 16 of 201

17 Pin No LQQ216 LQP176 LQS144 LBE F Pin Name PAC SCS71_0 TX0_0 TIOB8_0 AIN3_0 MADATA12_0 P54 SIN15_1 RTO04_1 (PPG04_1) TIOA10_2 INT00_2 MADATA20_0 P55 SOT15_1 (SDA15_1) RTO05_1 (PPG04_1) TIOB10_2 MADATA21_0 P56 I/O circuit type E E E Pin state type I K I F5 SCK15_1 (SCL15_1) DTTI0X_1 TIOB0_1 MADATA22_0 P57 IC00_1 TIOB1_1 MADATA23_0 PAD SCK3_0 (SCL3_0) TIOB9_0 BIN3_0 MADATA13_0 E E N I I I F G PAE ADTG_0 SOT3_0 (SDA3_0) TIOB10_0 ZIN3_0 MADATA14_0 PAF SIN3_0 TIOB11_0 INT16_0 MADATA15_0 P58 SIN11_1 IC01_1 TIOB2_1 INT02_2 MADATA24_0 N I E I K K Document Number: Rev.*B Page 17 of 201

18 Pin No LQQ216 LQP176 LQS144 LBE G G G G H H2 Pin Name P59 SOT11_1 (SDA11_1) IC02_1 TIOB3_1 MADATA25_0 P5A SCK11_1 (SCL11_1) IC03_1 TIOB4_1 MADATA26_0 P5B FRCK0_1 TIOB5_1 MADATA27_0 P08 SIN14_0 TIOB12_0 INT17_0 MDQM0_0 P09 SOT14_0 (SDA14_0) TIOB13_0 INT18_0 MDQM1_0 P0A ADTG_1 SCK14_0 (SCL14_0) AIN2_1 MCLKOUT_0 P5C TIOA11_2 MADATA28_0 RTCCO_1 SUBOUT_1 P30 RX0_1 TIOA13_2 INT03_2 MDQM2_0 I2SDI0_0 P31 TX0_1 TIOB13_2 MDQM3_0 I2SCK0_0 P32 BIN2_1 INT19_0 S_DATA1_0 I/O circuit type E E E E E L E E E L Pin state type I I I K K I I K I K Document Number: Rev.*B Page 18 of 201

19 Pin No LQQ216 LQP176 LQS144 LBE192 Pin Name I/O circuit type Pin state type P J1 FRCK0_0 ZIN2_1 S_DATA0_0 L I P H3 IC03_0 INT00_1 S_CLK_0 L K H1 VCC H5 VSS - - P H6 IC02_0 INT01_1 S_CMD_0 L K P J5 IC01_0 INT02_1 S_DATA3_0 L K P J4 IC00_0 INT03_1 S_DATA2_0 L K P J3 ADTG_2 DTTI0X_0 S_WP_0 E I P J2 SIN2_1 RTO00_0 (PPG00_0) TIOA0_1 AIN3_1 INT16_1 S_CD_0 MAD24_0 G K P3A K1 SOT2_1 (SDA2_1) RTO01_0 (PPG00_0) TIOA1_1 BIN3_1 INT17_1 MAD23_0 G K P3B K2 SCK2_1 (SCL2_1) RTO02_0 (PPG02_0) TIOA2_1 ZIN3_1 INT18_1 MAD22_0 G K MNALE_0 Document Number: Rev.*B Page 19 of 201

20 Pin No LQQ216 LQP176 LQS144 LBE192 Pin Name I/O circuit type Pin state type P3C K3 SIN13_0 RTO03_0 (PPG02_0) TIOA3_1 INT19_1 MAD21_0 MNCLE_0 G K P3D K4 SOT13_0 (SDA13_0) RTO04_0 (PPG04_0) TIOA4_1 MAD20_0 MNWEX_0 G I P3E L1 SCK13_0 (SCL13_0) RTO05_0 (PPG04_0) TIOA5_1 MAD19_0 MNREX_0 G I P5D L2 SIN10_1 TIOB11_2 INT01_2 MADATA29_0 I2SMCLK0_0 E K P5E L3 SOT10_1 (SDA10_1) TIOA12_2 MADATA30_0 I2SDO0_0 E I P5F M2 SCK10_1 (SCL10_1) TIOB12_2 MADATA31_0 I2SWS0_0 E I M1 VSS N1 VCC - - P N2 SIN3_1 RTO10_0 (PPG10_0) TIOA0_0 AIN0_0 INT23_0 G K MCSX7_0 Document Number: Rev.*B Page 20 of 201

21 Pin No LQQ216 LQP176 LQS144 LBE192 Pin Name I/O circuit type Pin state type P N3 SOT3_1 (SDA3_1) RTO11_0 (PPG10_0) TIOA1_0 BIN0_0 MCSX6_0 G I P M3 SCK3_1 (SCL3_1) RTO12_0 (PPG12_0) TIOA2_0 ZIN0_0 MCSX5_0 G I P L4 SIN15_0 RTO13_0 (PPG12_0) TIOA3_0 INT04_0 MCSX4_0 G K P M4 SOT15_0 (SDA15_0) RTO14_0 (PPG14_0) TIOA4_0 MCSX3_0 G I P N4 SCK15_0 (SCL15_0) RTO15_0 (PPG14_0) TIOA5_0 MCSX2_0 G I P2 C P3 VSS P4 VCC - - P4A SIN12_1 AIN0_1 INT04_2 E K P4B SOT12_1 (SDA12_1) BIN0_1 E I P4C SCK12_1 (SCL12_1) ZIN0_1 E I P4D SCS72_1 RX2_2 E K INT05_2 Document Number: Rev.*B Page 21 of 201

22 Pin No LQQ216 LQP176 LQS144 LBE192 Pin Name I/O circuit type Pin state type P4E SCS73_1 TX2_2 E I P7D L5 SCK1_1 (SCL1_1) RX2_0 DTTI1X_0 INT05_0 WKUP2 MCSX1_0 L Q P7E M5 ADTG_7 TX2_0 FRCK1_0 MCSX0_0 L I N5 INITX B C P5 P46 X0A P S P6 P47 X1A Q T P8 VBAT N6 P48 VREGCTL O U M6 P49 VWAKEUP O U PF K5 SCS63_0 RX2_1 FRCK1_1 TIOA15_1 INT22_1 E K PF K6 SCS62_0 TX2_1 TIOB15_1 INT23_1 E K P L6 ADTG_8 SIN1_1 INT06_0 MRDY_0 I K P J6 SOT1_1 (SDA1_1) MAD00_0 E I P L8 SIN9_0 TIOB0_0 INT07_0 MAD01_0 E K P K8 SOT9_0 (SDA9_0) TIOB1_0 E I MAD02_0 Document Number: Rev.*B Page 22 of 201

23 Pin No LQQ216 LQP176 LQS144 LBE J N M N P M L K P10 Pin Name P74 SCK9_0 (SCL9_0) TIOB2_0 MAD03_0 PF2 RTO10_1 (PPG10_1) TIOA6_1 MRASX_0 PF3 RTO11_1 (PPG10_1) TIOB6_1 INT05_1 MCASX_0 PF4 RTO12_1 (PPG12_1) TIOA7_1 INT06_1 MSDWEX_0 PF5 RTO13_1 (PPG12_1) TIOB7_1 INT07_1 MCSX8_0 PF6 RTO14_1 (PPG14_1) TIOA14_1 INT20_1 MSDCKE_0 PF7 RTO15_1 (PPG14_1) TIOB14_1 INT21_1 MSDCLK_0 P75 SIN8_0 TIOB3_0 AIN1_0 INT20_0 MAD04_0 P76 SOT8_0 (SDA8_0) TIOB4_0 BIN1_0 MAD05_0 I/O circuit type E L L L L L L E E Pin state type I I K K K K K K I Document Number: Rev.*B Page 23 of 201

24 Pin No LQQ216 LQP176 LQS144 LBE N L K M N M N13 Pin Name P77 SCK8_0 (SCL8_0) TIOB5_0 ZIN1_0 MAD06_0 PF8 SCS70_1 DTTI1X_1 AIN1_1 PF9 SCS71_1 IC10_1 BIN1_1 P78 SIN6_0 IC10_0 INT21_0 MAD07_0 P79 SOT6_0 (SDA6_0) IC11_0 MAD08_0 P7A SCK6_0 (SCL6_0) IC12_0 MAD09_0 P7B DA1 SCS60_0 IC13_0 INT22_0 P7C DA0 SCS61_0 INT04_1 PFA SCK7_1 (SCL7_1) IC11_1 ZIN1_1 PFB SOT7_1 (SDA7_1) IC12_1 INT07_2 PFC SIN7_1 IC13_1 INT06_2 PE0 MD1 I/O circuit type E E E E L L R R E Pin state type N12 MD0 J D E E C I I I K I I J J I K K E Document Number: Rev.*B Page 24 of 201

25 Pin No LQQ216 LQP176 LQS144 LBE P P13 Pin Name PE2 X0 PE3 X1 I/O circuit type A A Pin state type N14 VSS M14 VCC M13 AVCC M12 AVSS L13 AVRL L12 AVRH L K K K K P10 AN00 SIN10_0 TIOA0_2 AIN0_2 INT08_0 P11 AN01 SOT10_0 (SDA10_0) TIOB0_2 BIN0_2 P12 AN02 SCK10_0 (SCL10_0) TIOA1_2 ZIN0_2 P13 AN03 SIN6_1 RX1_1 INT25_1 P14 AN04 SOT6_1 (SDA6_1) TX1_1 PB8 ADTG_6 SCS63_1 INT08_2 TRACED8 PB9 SIN9_1 AIN2_2 INT09_2 TRACED9 PBA SOT9_1 (SDA9_1) BIN2_2 TRACED10 F F F F F E E E A B M L L M L O O N Document Number: Rev.*B Page 25 of 201

26 Pin No LQQ216 LQP176 LQS144 LBE J J J J J H J H H12 Pin Name PBB SCK9_1 (SCL9_1) ZIN2_2 TRACED11 P15 AN05 SIN11_0 TIOB1_2 AIN1_2 INT09_0 P16 AN06 SOT11_0 (SDA11_0) TIOA2_2 BIN1_2 P17 AN07 SCK11_0 (SCL11_0) TIOB2_2 ZIN1_2 PB0 AN16 SCK6_1 (SCL6_1) TIOA9_1 PB1 AN17 SCS60_1 TIOB9_1 INT08_1 PB2 AN18 SCS61_1 TIOA10_1 INT09_1 PB3 AN19 SCS62_1 TIOB10_1 P18 AN08 SIN2_0 TIOA3_2 INT10_0 P19 AN09 SOT2_0 (SDA2_0) TIOB3_2 INT24_1 TRACECLK I/O circuit type E F F F F F F F F F Pin state type N M L L L M M L M O Document Number: Rev.*B Page 26 of 201

27 Pin No LQQ216 LQP176 LQS144 LBE H G H H11 Pin Name P1A AN10 SCK2_0 (SCL2_0) TIOA4_2 TRACED0 P1B AN11 SIN12_0 TIOB4_2 INT11_0 TRACED1 P1C AN12 SOT12_0 (SDA12_0) TIOA5_2 TRACED2 P1D AN13 SCK12_0 (SCL12_0) TIOB5_2 TRACED3 I/O circuit type F F F F Pin state type VSS VCC G F G G G10 PB4 AN20 SIN8_1 TIOA11_1 INT10_1 TRACED4 PB5 AN21 SOT8_1 (SDA8_1) TIOB11_1 INT11_1 TRACED5 PB6 AN22 SCK8_1 (SCL8_1) TIOA12_1 TRACED6 PB7 AN23 TIOB12_1 TRACED7 P1E AN14 TIOA8_1 INT26_1 MAD10_0 F F F F F N O N N O O N N M Document Number: Rev.*B Page 27 of 201

28 Pin No LQQ216 LQP176 LQS144 LBE G F F F F E E11 Pin Name P1F AN15 RTS5_0 TIOB8_1 INT27_1 MAD11_0 P2A AN24 CTS5_0 MAD12_0 P29 AN25 SCK5_0 (SCL5_0) MAD13_0 P28 AN26 SOT5_0 (SDA5_0) MAD14_0 P27 AN27 SIN5_0 INT24_0 MAD15_0 PBC TX1_2 TRACED12 PBD SCK0_1 (SCL0_1) RX1_2 AIN3_2 INT10_2 TRACED13 PBE SOT0_1 (SDA0_1) BIN3_2 TRACED14 PBF SIN0_1 ZIN3_2 INT11_2 TRACED15 P26 TX1_0 MAD16_0 P25 AN28 RX1_0 INT25_0 MAD17_0 I/O circuit type F F F F F E E E E E F Pin state type M L L L M N O N O I M Document Number: Rev.*B Page 28 of 201

29 Pin No LQQ216 LQP176 LQS144 LBE E E D D C13 Pin Name P24 AN29 TIOA13_1 MAD18_0 P23 UHCONX1 AN30 SCK0_0 (SCL0_0) TIOB13_1 P22 AN31 SOT0_0 (SDA0_0) INT26_0 P21 ADTG_4 SIN0_0 INT27_0 CROUT_0 P20 NMIX WKUP0 I/O circuit type Pin state type E14 USBVCC D C14 P82 UDM1 P83 UDP B14 VSS A13 VCC B A C B B C D B10 P00 TRSTX P01 TCK SWCLK P02 TDI P03 TMS SWDIO P04 TDO SWO P90 INT12_1 Q_IO3_0 P91 SIN5_1 INT13_1 Q_IO2_0 P92 SOT5_1 (SDA5_1) INT14_1 Q_IO1_0 Document Number: Rev.*B Page 29 of 201 F F F I I H H E E E E E S S S L L M K F R R G G G G G K K K

30 Pin No LQQ216 LQP176 LQS144 LBE192 Pin Name I/O circuit type Pin state type P C10 SCK5_1 (SCL5_1) INT15_1 Q_IO0_0 S K P D10 CTS5_1 Q_SCK_0 S I P B9 RTS5_1 Q_CS0_0 S I P RX0_2 INT12_2 Q_CS1_0 S K P TX0_2 INT13_2 Q_CS2_0 S K C9 PC0 K I PC B8 TIOB6_0 K I D E F C D E8 PC2 TIOA6_0 PC3 TIOB7_0 PC4 TIOA7_0 PC5 TIOB14_0 PC6 TIOA14_0 PC7 INT13_0 CROUT_ A10 PC8 K I F8 PC9 TIOB15_0 K I B7 PCA TIOA15_ A9 VCC A8 VSS A7 PCB INT28_0 L K C7 PCC K I PCD A6 SOT4_1 (SDA4_1) L K INT14_0 K K K K K E K I I I I I K I Document Number: Rev.*B Page 30 of 201

31 Pin No LQQ216 LQP176 LQS144 LBE D7 Pin Name PCE SIN4_1 INT15_0 I/O circuit type L Pin state type K E F B6 PCF RTS4_1 INT12_0 PD0 INT30_1 PD1 INT31_1 L L L K K K C D PD2 CTS4_1 FRCK2_1 P6E ADTG_5 SCK4_1 (SCL4_1) IC23_1 INT29_0 P6D SCK14_1 (SCL14_1) IC22_1 TIOB6_2 P6C SOT14_1 (SDA14_1) IC21_1 TIOA6_2 P6B SIN14_1 IC20_1 TIOB7_2 INT14_2 P6A DTTI2X_1 TIOA7_2 P69 RTO20_1 (PPG20_1) TIOB14_2 P68 SCK13_1 (SCL13_0) RTO21_1 (PPG20_1) TIOA14_2 P67 SOT13_1 (SDA13_1) RTO22_1 (PPG22_1) TIOB15_2 L E E E E E E E E I K I I K I I I I Document Number: Rev.*B Page 31 of 201

32 Pin No LQQ216 LQP176 LQS144 LBE E B C B C B3 Pin Name P66 SIN13_1 RTO23_1 (PPG22_1) TIOA15_2 INT15_2 P65 RTO24_1 (PPG24_1) INT28_1 P64 CTS4_0 RTO25_1 (PPG24_1) INT29_1 P63 ADTG_3 RTS4_0 INT30_0 MOEX_0 P62 SCK4_0 (SCL4_0) MWEX_0 P61 UHCONX0 SOT4_0 (SDA4_0) MALE_0 RTCCO_0 SUBOUT_0 P60 SIN4_0 INT31_0 WKUP3 I/O circuit type E E I L L L Pin state type A4 USBVCC A A2 P80 UDM0 P81 UDP0 I H H K K K K I I Q R R Document Number: Rev.*B Page 32 of 201

33 Pin No LQQ216 LQP176 LQS144 LBE B1 Pin Name I/O circuit type Pin state type E G P P L A A N7 VSS M L K J G H H G8 - - Document Number: Rev.*B Page 33 of 201

34 Signal Descriptions The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin No Module Pin name Function LQQ LQP LQS LBE ADTG_ F6 ADTG_ G5 ADTG_ J3 ADTG_ C5 A/D converter external trigger ADTG_ D13 pin ADTG_ D6 ADTG_ ADTG_ M5 ADTG_ L6 AN L11 AN K13 AN K12 AN K14 AN K11 AN J13 AN J12 AN J11 AN H9 AN H12 AN H14 ADC AN G14 AN H13 AN H11 AN G10 AN15 A/D converter analog pin G9 AN16 ANxx describes ADC ch.xx J10 AN J9 AN H10 AN J14 AN G13 AN F14 AN G12 AN G11 AN F10 AN F11 AN F12 AN F13 AN E11 AN E12 AN E13 AN D12 Document Number: Rev.*B Page 34 of 201

35 Pin No Module Pin name Function LQQ LQP LQS LBE TIOA0_ N2 TIOA0_1 Base Timer ch.0 TIOA Pin J2 Base Timer TIOA0_ L11 0 TIOB0_ L8 TIOB0_1 Base Timer ch.0 TIOB Pin TIOB0_ K13 TIOA1_ N3 TIOA1_1 Base Timer ch.1 TIOA Pin K1 Base Timer TIOA1_ K12 1 TIOB1_ K8 TIOB1_1 Base Timer ch.1 TIOB Pin TIOB1_ J13 TIOA2_ M3 TIOA2_1 Base Timer ch.2 TIOA Pin K2 Base Timer TIOA2_ J12 2 TIOB2_ J8 TIOB2_1 Base Timer ch.2 TIOB Pin TIOB2_ J11 TIOA3_ L4 TIOA3_1 Base Timer ch.3 TIOA Pin K3 Base Timer TIOA3_ H9 3 TIOB3_ K9 TIOB3_1 Base Timer ch.3 TIOB Pin TIOB3_ H12 Base Timer 4 Base Timer 5 Base Timer 6 TIOA4_ M4 TIOA4_1 Base Timer ch.4 TIOA Pin K4 TIOA4_ H14 TIOB4_ P10 TIOB4_1 Base Timer ch.4 TIOB Pin TIOB4_ G14 TIOA5_ N4 TIOA5_1 Base Timer ch.5 TIOA Pin L1 TIOA5_ H13 TIOB5_ N10 TIOB5_1 Base Timer ch.5 TIOB Pin TIOB5_ H11 TIOA6_ D9 TIOA6_1 Base Timer ch.6 TIOA Pin N8 TIOA6_ TIOB6_ B8 TIOB6_1 Base Timer ch.6 TIOB Pin M8 TIOB6_ Document Number: Rev.*B Page 35 of 201

36 Module Pin name Function Base Timer 7 Base Timer 8 Base Timer 9 Base Timer 10 Base Timer 11 Base Timer 12 TIOA7_0 LQQ 216 LQP 176 Pin No LQS 144 TIOA7_1 Base Timer ch.7 TIOA Pin N9 LBE F9 TIOA7_ TIOB7_ E9 TIOB7_1 Base Timer ch.7 TIOB Pin P9 TIOB7_ TIOA8_ B2 TIOA8_1 Base Timer ch.8 TIOA Pin G10 TIOA8_ E2 TIOB8_ F4 TIOB8_1 Base Timer ch.8 TIOB Pin G9 TIOB8_ E3 TIOA9_ C2 TIOA9_1 Base Timer ch.9 TIOA Pin J10 TIOA9_ E4 TIOB9_ F5 TIOB9_1 Base Timer ch.9 TIOB Pin J9 TIOB9_ TIOA10_ C3 TIOA10_1 Base Timer ch.10 TIOA Pin H10 TIOA10_ TIOB10_ F6 TIOB10_1 Base Timer ch.10 TIOB Pin J14 TIOB10_ TIOA11_ D5 TIOA11_1 Base Timer ch.11 の TIOA Pin G13 TIOA11_ TIOB11_ G2 TIOB11_1 Base Timer ch.11 TIOB Pin F14 TIOB11_ L2 TIOA12_ D2 TIOA12_1 Base Timer ch.12 TIOA Pin G12 TIOA12_ L3 TIOB12_ G3 TIOB12_1 Base Timer ch.12 TIOB Pin G11 TIOB12_ M2 Document Number: Rev.*B Page 36 of 201

37 Module Pin name Function Base Timer 13 Base Timer 14 Base Timer 15 CAN 0 CAN 1 CAN 2 (CAN-FD) TIOA13_0 LQQ 216 LQP 176 Pin No LQS 144 LBE D1 TIOA13_1 Base Timer ch.13 TIOA Pin E12 TIOA13_ G6 TIOB13_ G4 TIOB13_1 Base Timer ch.13 TIOB Pin E13 TIOB13_ H4 TIOA14_ D8 TIOA14_1 Base Timer ch.14 TIOA Pin M9 TIOA14_ TIOB14_ C8 TIOB14_1 Base Timer ch.14 TIOB Pin L9 TIOB14_ TIOA15_ B7 TIOA15_1 Base Timer ch.15 TIOA Pin K5 TIOA15_ TIOB15_ F8 TIOB15_1 Base Timer ch.15 TIOB Pin K6 TIOB15_ TX0_ F4 TX0_1 CAN interface ch.0 TX output pin H4 TX0_ RX0_ F3 RX0_1 CAN interface ch.0 RX output pin G6 RX0_ TX1_ E10 TX1_1 CAN interface ch.1 TX output pin K11 TX1_ RX1_ E11 RX1_1 CAN interface ch.1 RX output pin K14 RX1_ TX2_ M5 TX2_1 CAN-FD interface ch.2 TX output pin K6 TX2_ RX2_ L5 RX2_1 CAN-FD interface ch.2 RX pin K5 RX2_ Document Number: Rev.*B Page 37 of 201

38 Module Pin name Function Debugger SWCLK SWDIO Serial wire debug interface clock pin Serial wire debug interface data / output pin LQQ 216 LQP 176 Pin No LQS 144 LBE A B12 SWO Serial wire viewer output pin B11 TCK JTAG test clock pin A12 TDI JTAG test data pin C12 TDO JTAG debug data output pin B11 TMS JTAG test mode state /output pin B12 TRACECLK Trace CLK output pin of ETM/HTM H12 TRACED H14 TRACED1 Trace data output pin of ETM/ G14 TRACED2 Trace data output pin of HTM H13 TRACED H11 TRACED G13 TRACED F14 TRACED G12 TRACED G11 TRACED TRACED Trace data output pin of HTM TRACED TRACED TRACED TRACED TRACED TRACED TRSTX JTAG test reset Input pin B13 Document Number: Rev.*B Page 38 of 201

39 Module Pin name Function External Bus MAD00_0 LQQ 216 LQP 176 Pin No LQS 144 LBE J6 MAD01_ L8 MAD02_ K8 MAD03_ J8 MAD04_ K9 MAD05_ P10 MAD06_ N10 MAD07_ L10 MAD08_ K10 MAD09_ M10 MAD10_ G10 MAD11_ G9 MAD12_0 External bus interface address bus F10 MAD13_ F11 MAD14_ F12 MAD15_ F13 MAD16_ E10 MAD17_ E11 MAD18_ E12 MAD19_ L1 MAD20_ K4 MAD21_ K3 MAD22_ K2 MAD23_ K1 MAD24_ J2 MCSX0_ M5 MCSX1_ L5 MCSX2_ N4 MCSX3_ M4 MCSX4_0 External bus interface chip select output pin L4 MCSX5_ M3 MCSX6_ N3 MCSX7_ N2 MCSX8_ P9 Document Number: Rev.*B Page 39 of 201

40 Module Pin name Function External Bus MADATA00_0 Pin No Document Number: Rev.*B Page 40 of 201 LQQ 216 LQP 176 LQS 144 MADATA15_0 External bus interface data bus G2 MADATA16_0 (Address / data multiplex bus) LBE B2 MADATA01_ C2 MADATA02_ C3 MADATA03_ D5 MADATA04_ D2 MADATA05_ D1 MADATA06_ D3 MADATA07_ D4 MADATA08_ E5 MADATA09_ F1 MADATA10_ F2 MADATA11_ F3 MADATA12_ F4 MADATA13_ F5 MADATA14_ F6 MADATA17_ MADATA18_ MADATA19_ MADATA20_ MADATA21_ MADATA22_ MADATA23_ MADATA24_ MADATA25_ MADATA26_ MADATA27_ MADATA28_ MADATA29_ MADATA30_ MADATA31_ MDQM0_ G3 MDQM1_0 External bus interface byte mask signal G4 MDQM2_0 output pin MDQM3_ MALE_0 External bus interface Address Latch enable output signal for multiplex C4 MRDY_0 External bus interface external RDY signal L6 MCLKOUT_0 External bus clock signal G5

41 Module Pin name Function External Bus External Interrupt MNALE_0 MNCLE_0 MNREX_0 MNWEX_0 MOEX_0 MWEX_0 MSDCLK_0 MSDCKE_0 MRASX_0 MCASX_0 MSDWEX_0 INT00_0 External bus interface ALE signal to control NAND Flash output pin External bus interface CLE signal to control NAND Flash output pin External bus interface read enable signal to control NAND Flash External bus interface write enable signal to control NAND Flash External bus interface read enable signal for SRAM External bus interface write enable signal for SRAM SDRAM interface SDRAM clock output pin SDRAM interface SDRAM clock enable output pin SDRAM interface SDRAM row active output pin SDRAM interface SDRAM column active output pin SDRAM interface SDRAM write enable output pin LQQ 216 LQP 176 Pin No LQS 144 LBE K K L K C B L M N M N B2 INT00_1 External interrupt request 00 pin H3 INT00_ INT01_ D1 INT01_1 External interrupt request 01 pin H6 INT01_ L2 INT02_ E5 INT02_1 External interrupt request 02 pin J5 INT02_ INT03_ F3 INT03_1 External interrupt request 03 pin J4 INT03_ G6 INT04_ L4 INT04_1 External interrupt request 04 pin M11 INT04_ INT05_ L5 INT05_1 External interrupt request 05 pin M8 INT05_ Document Number: Rev.*B Page 41 of 201

42 Module Pin name Function External Interrupt INT06_0 LQQ 216 LQP 176 Pin No LQS 144 INT06_1 External interrupt request 06 pin N9 LBE L6 INT06_ INT07_ L8 INT07_1 External interrupt request 07 pin P9 INT07_ INT08_ L11 INT08_1 External interrupt request 08 pin J9 INT08_ INT09_ J13 INT09_1 External interrupt request 09 pin H10 INT09_ INT10_ H9 INT10_1 External interrupt request 10 pin G13 INT10_ INT11_ G14 INT11_1 External interrupt request 11 pin F14 INT11_ INT12_ E7 INT12_1 External interrupt request 12 pin C11 INT12_ INT13_ E8 INT13_1 External interrupt request 13 pin D11 INT13_ INT14_ A6 INT14_1 External interrupt request 14 pin B10 INT14_ INT15_ D7 INT15_1 External interrupt request 15 pin C10 INT15_ INT16_ G2 External interrupt request 16 pin INT16_ J2 INT17_ G3 External interrupt request 17 pin INT17_ K1 INT18_ G4 External interrupt request 18 pin INT18_ K2 INT19_ H2 External interrupt request 19 pin INT19_ K3 INT20_0 External interrupt request 20 pin K9 Document Number: Rev.*B Page 42 of 201

43 Module Pin name Function External Interrupt LQQ 216 LQP 176 Pin No LQS 144 INT20_ M9 LBE 192 INT21_ L10 External interrupt request 21 pin INT21_ L9 INT22_ N11 External interrupt request 22 pin INT22_ K5 INT23_ N2 External interrupt request 23 pin INT23_ K6 INT24_ F13 External interrupt request 24 pin INT24_ H12 INT25_ E11 External interrupt request 25 pin INT25_ K14 INT26_ D12 External interrupt request 26 pin INT26_ G10 INT27_ D13 External interrupt request 27 pin INT27_ G9 INT28_ A7 External interrupt request 28 pin INT28_ E6 INT29_ D6 External interrupt request 29 pin INT29_ B5 INT30_ C5 External interrupt request 30 pin INT30_ F7 INT31_ B3 External interrupt request 31 pin INT31_ B6 NMIX Non-Maskable Interrupt pin C13 Document Number: Rev.*B Page 43 of 201

44 Module Pin name Function GPIO P00 LQQ 216 LQP 176 Pin No LQS 144 LBE B13 P A12 P C12 P B12 General-purpose I/O port 0 P B11 P G3 P G4 P0A G5 P L11 P K13 P K12 P K14 P K11 P J13 P J12 P J11 General-purpose I/O port 1 P H9 P H12 P1A H14 P1B G14 P1C H13 P1D H11 P1E G10 P1F G9 P C13 P D13 P D12 P E13 P E12 P25 General-purpose I/O port E11 P E10 P F13 P F12 P F11 P2A F10 Document Number: Rev.*B Page 44 of 201

45 Module Pin name Function GPIO P30 LQQ 216 LQP 176 Pin No LQS 144 P37 General-purpose I/O port J4 LBE G6 P H4 P H2 P J1 P H3 P H6 P J5 P J3 P J2 P3A K1 P3B K2 P3C K3 P3D K4 P3E L1 P N2 P N3 P M3 P L4 P M4 P N4 P P5 P47 General-purpose I/O port P6 P N6 P M6 P4A P4B P4C P4D P4E Document Number: Rev.*B Page 45 of 201

46 Module Pin name Function GPIO P50 LQQ 216 LQP 176 Pin No LQS 144 P General-purpose I/O port 5 P LBE E2 P E3 P E4 P P P P P P5A P5B P5C P5D L2 P5E L3 P5F M2 P B3 P C4 P B4 P C5 P B5 P E6 P P67 General-purpose I/O port P P P6A P6B P6C P6D P6E D6 Document Number: Rev.*B Page 46 of 201

47 Module Pin name Function GPIO P70 LQQ 216 LQP 176 Pin No LQS 144 LBE L6 P J6 P L8 P K8 P J8 P K9 P P10 P77 General-purpose I/O port N10 P L10 P K10 P7A M10 P7B N11 P7C M11 P7D L5 P7E M5 P A3 P A2 General-purpose I/O port 8 P D14 P C14 P C11 P D11 P B10 P C10 General-purpose I/O port 9 P D10 P B9 P P Document Number: Rev.*B Page 47 of 201

48 Module Pin name Function GPIO PA0 LQQ 216 LQP 176 Pin No LQS 144 PA D4 General-purpose I/O port A PA E5 LBE B2 PA C2 PA C3 PA D5 PA D2 PA D1 PA D3 PA F1 PAA F2 PAB F3 PAC F4 PAD F5 PAE F6 PAF G2 PB J10 PB J9 PB H10 PB J14 PB G13 PB F14 PB G12 PB G11 General-purpose I/O port B PB PB PBA PBB PBC PBD PBE PBF Document Number: Rev.*B Page 48 of 201

49 Module Pin name Function GPIO PC0 LQQ 216 LQP 176 Pin No LQS 144 LBE C9 PC B8 PC D9 PC E9 PC F9 PC C8 PC D8 PC E8 General-purpose I/O port C PC A10 PC F8 PCA B7 PCB A7 PCC C7 PCD A6 PCE D7 PCF E7 PD F7 PD1 General-purpose I/O port D B6 PD C6 PE N13 PE2 General-purpose I/O port E P12 PE P13 PF K5 PF K6 PF N8 PF M8 PF N9 PF P9 PF6 General-purpose I/O port F M9 PF L9 PF PF PFA PFB PFC Document Number: Rev.*B Page 49 of 201

50 Module Pin name Function Multifunction serial 0 Multifunction serial 1 Multifunction serial 2 LQQ 216 LQP 176 Pin No LQS 144 LBE 192 SIN0_0 Multi-function serial interface ch D13 SIN0_1 pin SOT0_0 (SDA0_0) SOT0_1 (SDA0_1) SCK0_0 (SCL0_0) SCK0_1 (SCL0_1) Multi-function serial interface ch.0 output pin This pin operates as SOT0 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA0 when it is used in an I 2 C (operation mode 4). Multi-function serial interface ch.0 clock I/O pin. This pin operates as SCK0 when it is used in a CSIO (operation mode 2) and as SCL0 when it is used in an I 2 C (operation mode 4) D E SIN1_0 Multi-function serial interface ch D1 SIN1_1 pin L6 SOT1_0 (SDA1_0) SOT1_1 (SDA1_1) SCK1_0 (SCL1_0) SCK1_1 (SCL1_1) Multi-function serial interface ch.1 output pin This pin operates as SOT1 when it is used in a UART/CSIO/LIN(operation modes 0 to 3) and as SDA1 when it is used in an I 2 C (operation mode 4). Multi-function serial interface ch.1 clock I/O pin. This pin operates as SCK1 when it is used in a CSIO (operation modes 2) and as SCL1 when it is used in an I 2 C (operation mode 4) D J D L5 SIN2_0 Multi-function serial interface ch H9 SIN2_1 pin J2 SOT2_0 (SDA2_0) SOT2_1 (SDA2_1) SCK2_0 (SCL2_0) SCK2_1 (SCL2_1) Multi-function serial interface ch.2 output pin This pin operates as SOT2 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA2 when it is used in an I 2 C (operation mode 4). Multi-function serial interface ch.2 clock I/O Pin. This pin operates as SCK2 when it is used in a CSIO (operation modes 2) and as SCL2 when it is used in an I 2 C (operation mode 4) H K H K2 Document Number: Rev.*B Page 50 of 201

51 Module Pin name Function Multifunction serial 3 Multifunction serial 4 LQQ 216 LQP 176 Pin No LQS 144 SIN3_0 Multi-function serial interface ch G2 SIN3_1 pin N2 SOT3_0 (SDA3_0) SOT3_1 (SDA3_1) SCK3_0 (SCL3_0) SCK3_1 (SCL3_1) Multi-function serial interface ch.3 output pin. This pin operates as SOT3 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA3 when it is used in an I 2 C (operation mode 4). Multi-function serial interface ch.3 clock I/O pin. This pin operates as SCK3 when it is used in a CSIO (operation modes 2) and as SCL3 when it is used in an I 2 C (operation mode 4). LBE F N F M3 SIN4_0 Multi-function serial interface ch B3 SIN4_1 pin D7 SOT4_0 (SDA4_0) SOT4_1 (SDA4_1) SCK4_0 (SCL4_0) SCK4_1 (SCL4_1) Multi-function serial interface ch.4 output pin. This pin operates as SOT4 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA4 when it is used in an I 2 C (operation mode 4). Multi-function serial interface ch.4 clock I/O pin. This pin operates as SCK4 when it is used in a CSIO (operation modes 2) and as SCL4 when it is used in an I 2 C (operation mode 4) C A B D6 CTS4_0 Multi-function serial interface ch.4 CTS B5 CTS4_1 pin C6 RTS4_0 Multi-function serial interface ch.4 RTS C5 RTS4_1 output pin E7 Document Number: Rev.*B Page 51 of 201

52 Module Pin name Function Multifunction serial 5 Multifunction serial 6 LQQ 216 LQP 176 Pin No LQS 144 LBE 192 SIN5_0 Multi-function serial interface ch F13 SIN5_1 pin D11 SOT5_0 (SDA5_0) SOT5_1 (SDA5_1) SCK5_0 (SCL5_0) SCK5_1 (SCL5_1) Multi-function serial interface ch.5 output pin. This pin operates as SOT5 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA5 when it is used in an I 2 C (operation mode 4). Multi-function serial interface ch.5 clock I/O pin. This pin operates as SCK5 when it is used in a CSIO (operation modes 2) and as SCL5 when it is used in an I 2 C (operation mode 4) F B F C10 CTS5_0 Multi-function serial interface ch.5 CTS F10 CTS5_1 pin D10 RTS5_0 Multi-function serial interface ch.5 RTS G9 RTS5_1 output pin B9 SIN6_0 Multi-function serial interface ch L10 SIN6_1 pin K14 SOT6_0 (SDA6_0) SOT6_1 (SDA6_1) SCK6_0 (SCL6_0) SCK6_1 (SCL6_1) Multi-function serial interface ch.6 output pin. This pin operates as SOT6 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA6 when it is used in an I 2 C (operation mode 4). Multi-function serial interface ch.6 clock I/O pin. This pin operates as SCK6 when it is used in a CSIO (operation modes 2) and as SCL6 when it is used in an I 2 C (operation mode 4) K K M J10 SCS60_0 Multi-function serial interface ch.6 chip N11 SCS60_1 select 0 /output pin J9 SCS61_0 Multi-function serial interface ch.6 chip M11 SCS61_1 select1 /output pin H10 SCS62_0 Multi-function serial interface ch.6 chip K6 SCS62_1 select2 /output pin J14 SCS63_0 Multi-function serial interface ch.6 chip K5 SCS63_1 select3 /output pin Document Number: Rev.*B Page 52 of 201

53 Pin No Module Pin name Function LQQ LQP LQS LBE SIN7_0 Multi-function serial interface ch E5 SIN7_1 pin SOT7_0 (SDA7_0) F1 Multifunction serial 7 Multifunction serial 8 Multifunction serial 9 SOT7_1 (SDA7_1) SCK7_0 (SCL7_0) SCK7_1 (SCL7_1) Multi-function serial interface ch.7 output pin. This pin operates as SOT7 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA7 when it is used in an I 2 C (operation mode 4). Multi-function serial interface ch.7 clock I/O pin. This pin operates as SCK7 when it is used in a CSIO (operation modes 2) and as SCL7 when it is used in an I 2 C (operation mode 4) F SCS70_0 Multi-function serial interface ch.7 chip F3 SCS70_1 select 0 /output pin SCS71_0 Multi-function serial interface ch.7 chip F4 SCS71_1 select1 /output pin SCS72_0 Multi-function serial interface ch.7 chip E2 SCS72_1 select 2 /output pin SCS73_0 Multi-function serial interface ch.7 chip E3 SCS73_1 select 3 /output pin SIN8_0 Multi-function serial interface ch K9 SIN8_1 pin G13 SOT8_0 (SDA8_0) P10 SOT8_1 (SDA8_1) SCK8_0 (SCL8_0) SCK8_1 (SCL8_1) Multi-function serial interface ch.8 output pin. This pin operates as SOT8 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA8 when it is used in an I 2 C (operation mode 4). Multi-function serial interface ch.8 clock I/O pin. This pin operates as SCK8 when it is used in a CSIO (operation modes 2) and as SCL8 when it is used in an I 2 C (operation mode 4) F N G12 SIN9_0 Multi-function serial interface ch L8 SIN9_1 pin SOT9_0 (SDA9_0) K8 SOT9_1 (SDA9_1) SCK9_0 (SCL9_0) SCK9_1 (SCL9_1) Multi-function serial interface ch.9 output pin. This pin operates as SOT9 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA9 when it is used in an I 2 C (operation mode 4). Multi-function serial interface ch.9 clock I/O pin. This pin operates as SCK9 when it is used in a CSIO (operation modes 2) and as SCL9 when it is used in an I 2 C (operation mode 4) J Document Number: Rev.*B Page 53 of 201

54 Pin No Module Pin name Function LQQ LQP LQS LBE SIN10_0 Multi-function serial interface ch L11 SIN10_1 pin L2 SOT10_0 (SDA10_0) K13 Multifunction serial 10 Multifunction serial 11 Multifunction serial 12 Multifunction serial 13 SOT10_1 (SDA10_1) SCK10_0 (SCL10_0) SCK10_1 (SCL10_1) Multi-function serial interface ch.10 output pin. This pin operates as SOT10 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA10 when it is used in an I 2 C (operation mode 4). Multi-function serial interface ch.10 clock I/O pin. This pin operates as SCK10 when it is used in a CSIO (operation modes 2) and as SCL10 when it is used in an I 2 C (operation mode 4) L K M2 SIN11_0 Multi-function serial interface ch J13 SIN11_1 pin SOT11_0 (SDA11_0) J12 SOT11_1 (SDA11_1) SCK11_0 (SCL11_0) SCK11_1 (SCL11_1) Multi-function serial interface ch.11 output pin. This pin operates as SOT11 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA11 when it is used in an I 2 C (operation mode 4). Multi-function serial interface ch.11 clock I/O pin. This pin operates as SCK11 when it is used in a CSIO (operation modes 2) and as SCL11 when it is used in an I 2 C (operation mode 4) J SIN12_0 Multi-function serial interface ch G14 SIN12_1 pin SOT12_0 (SDA12_0) H13 SOT12_1 (SDA12_1) SCK12_0 (SCL12_0) SCK12_1 (SCL12_1) Multi-function serial interface ch.12 output pin. This pin operates as SOT12 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA12 when it is used in an I 2 C (operation mode 4). Multi-function serial interface ch.12 clock I/O pin. This pin operates as SCK12 when it is used in a CSIO (operation modes 2) and as SCL12 when it is used in an I 2 C (operation mode 4) H SIN13_0 Multi-function serial interface ch K3 SIN13_1 pin SOT13_0 (SDA13_0) K4 SOT13_1 (SDA13_1) SCK13_0 (SCL13_0) SCK13_1 (SCL13_1) Multi-function serial interface ch.13 output pin. This pin operates as SOT13 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA13 when it is used in an I 2 C (operation mode 4). Multi-function serial interface ch.13 clock I/O pin. This pin operates as SCK13 when it is used in a CSIO (operation modes 2) and as SCL13 when it is used in an I 2 C (operation mode 4) L Document Number: Rev.*B Page 54 of 201

55 Pin No Module Pin name Function LQQ LQP LQS LBE SIN14_0 Multi-function serial interface ch G3 SIN14_1 pin SOT14_0 (SDA14_0) G4 Multifunction serial 14 Multifunction serial 15 SOT14_1 (SDA14_1) SCK14_0 (SCL14_0) SCK14_1 (SCL14_1) Multi-function serial interface ch.14 output pin. This pin operates as SOT14 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA14 when it is used in an I 2 C (operation mode 4). Multi-function serial interface ch.14 clock I/O pin. This pin operates as SCK14 when it is used in a CSIO (operation modes 2) and as SCL14 when it is used in an I 2 C (operation mode 4) G SIN15_0 Multi-function serial interface ch L4 SIN15_1 pin SOT15_0 (SDA15_0) M4 SOT15_1 (SDA15_1) SCK15_0 (SCL15_0) SCK15_1 (SCL15_1) Multi-function serial interface ch.15 output pin. This pin operates as SOT15 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA15 when it is used in an I 2 C (operation mode 4). Multi-function serial interface ch.15 clock I/O pin. This pin operates as SCK15 when it is used in a CSIO (operation modes 2) and as SCL15 when it is used in an I 2 C (operation mode 4) N Document Number: Rev.*B Page 55 of 201

56 Module Pin name Function Multifunction Timer Timer 0 LQQ 216 LQP 176 Pin No LQS 144 DTTI0X_0 Input signal controlling wave form J3 generator outputs RTO00 to RTO05 of DTTI0X_1 Multi-function timer FRCK0_0 16-bit free-run timer ch.0 external J1 FRCK0_1 clock pin IC00_0 IC01_1 16-bit capture pin of Multi-function timer 0. IC02_0 ICxx describes channel number H6 LBE J4 IC00_ IC01_ J5 IC02_ IC03_ H3 IC03_ RTO00_0 (PPG00_0) RTO00_1 (PPG00_1) RTO01_0 (PPG00_0) RTO01_1 (PPG00_1) RTO02_0 (PPG02_0) RTO02_1 (PPG02_1) RTO03_0 (PPG02_0) RTO03_1 (PPG02_1) RTO04_0 (PPG04_0) RTO04_1 (PPG04_1) RTO05_0 (PPG04_0) RTO05_1 (PPG04_1) Wave form generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output modes. Wave form generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output modes. Wave form generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output modes. Wave form generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output modes. Wave form generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output modes. Wave form generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output modes J E K E K E K K L Document Number: Rev.*B Page 56 of 201

57 Module Pin name Function Multifunction Timer 1 LQQ 216 LQP 176 Pin No LQS 144 DTTI1X_0 Input signal controlling wave form L5 generator outputs RTO10 to RTO15 of DTTI1X_1 Multi-function timer FRCK1_0 16-bit free-run timer ch.1 external clock M5 FRCK1_1 pin K5 IC10_0 LBE L10 IC10_ IC11_ K10 IC11_1 16-bit capture pin of Multi-function timer 1. IC12_0 ICxx describes channel number M10 IC12_ IC13_ N11 IC13_ RTO10_0 (PPG10_0) RTO10_1 (PPG10_1) RTO11_0 (PPG10_0) RTO11_1 (PPG10_1) RTO12_0 (PPG12_0) RTO12_1 (PPG12_1) RTO13_0 (PPG12_0) RTO13_1 (PPG12_1) RTO14_0 (PPG14_0) RTO14_1 (PPG14_1) RTO15_0 (PPG14_0) RTO15_1 (PPG14_1) Wave form generator output pin of Multi-function timer 1. This pin operates as PPG10 when it is used in PPG1 output modes. Wave form generator output pin of Multi-function timer 1. This pin operates as PPG10 when it is used in PPG1 output modes. Wave form generator output pin of Multi-function timer 1. This pin operates as PPG12 when it is used in PPG1 output modes. Wave form generator output pin of Multi-function timer 1. This pin operates as PPG12 when it is used in PPG1 output modes. Wave form generator output pin of Multi-function timer 1. This pin operates as PPG14 when it is used in PPG1 output modes. Wave form generator output pin of Multi-function timer 1. This pin operates as PPG14 when it is used in PPG1 output modes N N N M M N L P M M N L9 Document Number: Rev.*B Page 57 of 201

58 Module Pin name Function Multifunction Timer 2 LQQ 216 LQP 176 Pin No LQS 144 DTTI2X_0 Input signal controlling wave form D3 generator outputs RTO20 to RTO25 of DTTI2X_1 Multi-function timer FRCK2_0 16-bit free-run timer ch.2 external clock F3 FRCK2_1 pin C6 IC20_0 IC21_1 16-bit capture pin of Multi-function timer 2. IC22_0 ICxx describes channel number F1 LBE D4 IC20_ IC21_ E5 IC22_ IC23_ F2 IC23_ D6 RTO20_0 (PPG20_0) RTO20_1 (PPG20_1) RTO21_0 (PPG20_0) RTO21_1 (PPG20_1) RTO22_0 (PPG22_0) RTO22_1 (PPG22_1) RTO23_0 (PPG22_0) RTO23_1 (PPG22_1) RTO24_0 (PPG24_0) RTO24_1 (PPG24_1) RTO25_0 (PPG24_0) RTO25_1 (PPG24_1) Wave form generator output pin of Multi-function timer 2. This pin operates as PPG20 when it is used in PPG2 output modes. Wave form generator output pin of Multi-function timer 2. This pin operates as PPG20 when it is used in PPG2 output modes. Wave form generator output pin of Multi-function timer 2. This pin operates as PPG22 when it is used in PPG2 output modes. Wave form generator output pin of Multi-function timer 2. This pin operates as PPG22 when it is used in PPG2 output modes. Wave form generator output pin of Multi-function timer 2. This pin operates as PPG24 when it is used in PPG2 output modes. Wave form generator output pin of Multi-function timer 2. This pin operates as PPG24 when it is used in PPG2 output modes B C C D D E D B5 Document Number: Rev.*B Page 58 of 201

59 Module Pin name Function Quadrature Position/ Revolution Counter 0 Quadrature Position/ Revolution Counter 1 Quadrature Position/ Revolution Counter 2 AIN0_0 LQQ 216 LQP 176 Pin No LQS 144 AIN0_1 QPRC ch.0 AIN pin LBE N2 AIN0_ L11 BIN0_ N3 BIN0_1 QPRC ch.0 BIN pin BIN0_ K13 ZIN0_ M3 ZIN0_1 QPRC ch.0 ZIN pin ZIN0_ K12 AIN1_ K9 AIN1_1 QPRC ch.1 AIN pin AIN1_ J13 BIN1_ P10 BIN1_1 QPRC ch.1 BIN pin BIN1_ J12 ZIN1_ N10 ZIN1_1 QPRC ch.1 ZIN pin ZIN1_ J11 AIN2_ B2 AIN2_1 QPRC ch.2 AIN pin G5 AIN2_ BIN2_ C2 BIN2_1 QPRC ch.2 BIN pin H2 BIN2_ ZIN2_ C3 ZIN2_1 QPRC ch.2 ZIN pin J1 ZIN2_ Document Number: Rev.*B Page 59 of 201

60 Module Pin name Function Quadrature Position/ Revolution Counter 3 Real-time clock USB0 USB1 Low-Power Consumption Mode DAC VBAT AIN3_0 LQQ 216 LQP 176 Pin No LQS 144 AIN3_1 QPRC ch.3 AIN pin J2 LBE F4 AIN3_ BIN3_ F5 BIN3_1 QPRC ch.3 BIN pin K1 BIN3_ ZIN3_ F6 ZIN3_1 QPRC ch.3 ZIN pin K2 ZIN3_ RTCCO_0 0.5 seconds pulse output pin of C4 RTCCO_1 Real-time clock SUBOUT_ C4 Sub clock output pin SUBOUT_ UDM0 USB ch.0 device/host D pin A3 UDP0 USB ch.0 device/host D + pin A2 UHCONX0 USB ch.0 external pull-up control pin C4 UDM1 USB ch.1 device/host D pin D14 UDP1 USB ch.1 device/host D + pin C14 UHCONX1 USB ch.1 external pull-up control pin E13 WKUP0 Deep standby mode return signal pin C13 WKUP1 Deep standby mode return signal pin E5 WKUP2 Deep standby mode return signal pin L5 WKUP3 Deep standby mode return signal pin B3 DA0 D/A converter ch.0 analog output pin M11 DA1 D/A converter ch.1 analog output pin N11 VREGCTL On-board regulator control pin N6 VWAKEUP The return signal pin from a hibernation state M6 Document Number: Rev.*B Page 60 of 201

61 Module Pin name Function SD I/F I 2 S High-Speed Quad SPI Reset S_CLK_0 S_CMD_0 S_DATA1_0 SD memory card interface SD memory card clock output pin SD memory card interface SD memory card command output LQQ 216 LQP 176 Pin No LQS 144 LBE H H H2 S_DATA0_0 SD memory card interface J1 S_DATA3_0 SD memory card data bus J5 S_DATA2_ J4 S_CD_0 SD memory card interface SD memory card detection pin J2 S_WP_0 SD memory card interface SD memory card write protection J3 I2SMCLK0_0 I 2 S external clock pin L2 I2SDO0_0 I 2 S serial transition data output pin L3 I2SWS0_0 I2 S frame synchronization signal pin M2 I2SDI0_0 I 2 S serial received data pin G6 I2SCK0_0 I 2 S bit clock pin H4 Q_SCK_0 SPI clock output pin D10 Q_IO0_ C10 Q_IO1_ B10 SPI data /output pin Q_IO2_ D11 Q_IO3_ C11 Q_CS0_ B9 Q_CS1_0 SPI chip select output pin Q_CS2_ INITX External Reset Input pin. A reset is valid when INITX=L N5 Document Number: Rev.*B Page 61 of 201

62 Module Pin name Function Mode Power MD1 MD0 VCC Mode 1 pin. During serial programming to Flash memory, MD1=L must be. Mode 0 pin. During normal operation, MD0=L must be. During serial programming to Flash memory, MD0=H must be. Power supply Pin LQQ 216 LQP 176 Pin No LQS 144 LBE N N C H N P M A A9 USBVCC A4 3.3V Power supply port for USB I/O USBVCC E14 GND VSS GND Pin H M P N B A B E G P P L A A N M K J G H H G8 Document Number: Rev.*B Page 62 of 201

63 Module Pin name Function Clock Analog Power VBAT Power Analog GND LQQ 216 LQP 176 Pin No LQS 144 LBE 192 X0 Main clock (oscillation) pin P12 X1 Main clock (oscillation) I/O pin P13 X0A Sub clock (oscillation) pin P5 X1A Sub clock (oscillation) I/O pin P6 CROUT_0 Built-in High-speed CR-osc clock output D13 CROUT_1 port E8 AVCC A/D converter and D/A converter analog power supply pin M13 AVRL A/D converter analog reference voltage pin L13 AVRH A/D converter analog reference voltage pin L12 VBAT power supply pin. VBAT Backup power supply (battery etc.) and P8 system power supply. AVSS A/D converter and D/A converter GND pin M12 C Pin C Power supply stabilization capacity pin P2 Note: While this device contains a Test Access Port (TAP) based on the IEEE JTAG standard, it is not fully compliant to all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP controller. Document Number: Rev.*B Page 63 of 201

64 5. I/O Circuit Type Type Circuit Remarks A Pull-up resistor P-ch P-ch Digital output X1 N-ch Digital output R It is possible to select the main oscillation/gpio function. Feedback Pull-up resistor control Digital Standby mode control Clock When the main oscillation is selected: Oscillation feedback resistor: approximately 1 MΩ Standby mode control resistor Pull-up Standby mode control Digital Standby mode control When the GPIO is selected: CMOS level output. CMOS level hysteresis Pull-up resistor control Standby mode control Pull-up resistor: approximately 50 kω I OH = -4 ma, I OL = 4 ma R resistor X0 P-ch P-ch Digital output N-ch Digital output Pull-up resistor control B Pull-up resistor Digital CMOS level hysteresis Pull-up resistor: approximately 50 kω Document Number: Rev.*B Page 64 of 201

65 Type Circuit Remarks C Digital N-ch Digital output Open drain output CMOS level hysteresis E R P-ch P-ch N-ch Digital output Digital output Pull-up resistor control CMOS level output CMOS level hysteresis Pull-up resistor control Standby mode control Pull-up resistor: approximately 50 kω I OH = -4 ma, I OL = 4 ma When this pin is used as an I 2 C pin, the digital output P-ch transistor is always off. Digital Standby mode control F P-ch P-ch Digital output CMOS level output CMOS level hysteresis Input control R N-ch Digital output Pull-up resistor control Digital Standby mode control Analog Pull-up resistor control Standby mode control Pull-up resistor: approximately 50 kω I OH = -4 ma, I OL = 4 ma When this pin is used as an I 2 C pin, the digital output P-ch transistor is always off. Analog Input control Document Number: Rev.*B Page 65 of 201

66 Type Circuit Remarks G R P-ch P-ch N-ch Digital output Digital output Pull-up resistor control Digital CMOS level output CMOS level hysteresis Pull-up resistor control Standby mode control Pull-up resistor: approximately 50 kω I OH = -12 ma, I OL = 12 ma When this pin is used as an I 2 C pin, the digital output P-ch transistor is always off. Standby mode control H UDP/Pxx UDM/Pxx Differential GPIO Digital output GPIO Digital /output direction GPIO Digital GPIO Digital circuit control UDP output USB Full-speed/Low-speed control UDP Differential USB/GPIO select UDM UDM output USB Digital /output direction GPIO Digital output It is possible to select either USB I/O or GPIO function. When the USB I/O is selected: Full-speed, low-speed control When the GPIO is selected: CMOS level output CMOS level hysteresis Standby mode control I OH = ma, I OL = 18.5 ma GPIO Digital /output direction GPIO Digital GPIO Digital circuit control Document Number: Rev.*B Page 66 of 201

67 Type Circuit Remarks I CMOS level output CMOS level hysteresis 5V tolerant R P-ch P-ch N-ch Digital output Digital output Pull-up resistor control Digital Pull-up resistor control Standby mode control Pull-up resistor: approximately 50 kω I OH = -4 ma, I OL = 4 ma Available to control of PZR registers (pseudo-open drain control) For PZR registers, refer to GPIO in the FM4 Family Peripheral Manual Main Part ( ). Standby mode control J Mode CMOS level hysteresis K R P-ch P-ch N-ch Digital output Digital output CMOS level output TTL level hysteresis Pull-up resistor control Standby mode control Pull-up resistor: approximately 50 kω I OH = -4mA, I OL = 4mA Pull-up resistor control Digital Standby mode control Document Number: Rev.*B Page 67 of 201

68 Type Circuit Remarks L P-ch R P-ch N-ch Digital output Digital output Pull-up resistor control CMOS level output CMOS level hysteresis Pull-up resistor control Standby mode control Pull-up resistor: approximately 50 kω I OH = -8 ma, I OL = 8 ma When this pin is used as an I 2 C pin, the digital output P-ch transistor is always off. Digital Standby mode control N CMOS level output CMOS level hysteresis P-ch R N-ch P-ch N-ch Pull-up resistor control Digital output Digital output Fast mode control Digital Standby mode control 5V tolerant Pull-up resistor control Standby mode control Pull-up resistor: approximately 50 kω I OH = -4 ma, I OL = 4 ma (GPIO) I OL = 20mA (Fast mode Plus) Available to control of PZR register (pseudo-open drain control) For PZR registers, refer to GPIO in the FM4 Family Peripheral Manual Main Part ( ). When this pin is used as an I 2 C pin, the digital output P-ch transistor is always off. Document Number: Rev.*B Page 68 of 201

69 Type Circuit Remarks O P P-ch R P-ch N-ch Pull-up resistor control Digital output Digital output Digital CMOS level output CMOS level hysteresis 5V tolerant Pull-up resistor control Pull-up resistor: approximately 50 kω I OH = -4 ma, I OL = 4 ma Available to control of PZR register (pseudo-open drain control) For PZR registers, refer to GPIO in the FM4 Family Peripheral Manual Main Part ( ). For I/O setting, refer to VBAT Domain in the "FM4 Family Peripheral Manual Main Part ( ). X0A P-ch R P-ch N-ch Pull-up resistor control Digital output Digital output CMOS level output CMOS level hysteresis Pull-up resistor control Pull-up resistor: approximately 50 kω I OH = -4 ma, I OL = 4 ma For I/O setting, refer to VBAT Domain in the "FM4 Family Peripheral Manual Main Part ( ). Digital Standby mode control OSC Document Number: Rev.*B Page 69 of 201

70 Type Circuit Remarks Q X1A P-ch P-ch N-ch Pull-up resistor control Digital output Digital output It is possible to select the sub oscillation/gpio function. When the sub oscillation is selected: Oscillation feedback resistor: approximately 10 MΩ R RX Digital Standby mode control OSC Standby mode control When the GPIO is selected: CMOS level output. CMOS level hysteresis Pull-up resistor control Pull-up resistor: approximately 50 kω I OH = -4 ma, I OL = 4 ma For I/O setting, refer to VBAT Domain in the "FM4 Family Peripheral Manual Main Part ( ). Clock R P-ch R P-ch N-ch Pull-up resistor control Digital output Digital output Digital CMOS level output CMOS level hysteresis Analog output Pull-up resistor control Standby mode control Pull-up resistor: approximately 50 kω I OH = -4 ma, I OL = 4 ma (4.5V to 5.5V) I OH = -2 ma, I OL = 2 ma (2.7V to 4.5V) Standby mode control Analog output Document Number: Rev.*B Page 70 of 201

71 Type Circuit Remarks S CMOS level output (It is possible to select by port P-ch R P-ch N-ch Pull-up resistor control Digital output Port Drive Select Digital Standby mode Control drive capability. Select register [PDSR]) CMOS level hysteresis Pull-up resistor control Standby mode control Pull-up resistor: approximately 50 kω I OH = -10 ma, I OL = 10 ma (PDSR = 1) I OH = -4 ma, I OL = 4 ma (PDSR = 0) When this pin is used as an I 2 C pin, the digital output P-ch transistor is always off. Document Number: Rev.*B Page 71 of 201

72 6. Handling Precautions Every semiconductor device has a characteristic, inherent rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices. 6.1 Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices. Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Processing and Protection of Pins These precautions must be followed when handling the pins that connect semiconductor devices to power supply and I/O functions. 1. Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. 2. Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions, if present for extended periods of time, can damage the device; therefore, avoid this type of connection. 3. Handling of Unused Input Pins Unconnected pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power-supply pin or ground pin. Document Number: Rev.*B Page 72 of 201

73 Latch-Up Semiconductor devices are constructed by the formation of p-type and n-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic pnpn junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred milliamps to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: 1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. 2. Be sure that abnormal current flows do not occur during the power-on sequence. Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. Fail-Safe Design As ly mentioned, all semiconductor devices have inherent rates of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Precautions Related to Usage of Devices Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 6.2 Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Cypress's recommended conditions. For detailed information about mount conditions, contact your sales representative. Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. Document Number: Rev.*B Page 73 of 201

74 Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended conditions. Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent this, do the following: 1. Avoid exposure to rapid temperature changes, which can cause moisture to condense inside the product. Store products in locations where temperature changes are slight. 2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5 C and 30 C. 3. When Dry Packages are opened, it is recommended to have humidity between 40% and 70%. 4. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in these aluminum laminate bags for storage. 5. Avoid storing packages where they are exposed to corrosive gases or high levels of dust. Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended conditions for baking. Condition: 125 C/24 h Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: 1. relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. 2. Electrically ground all conveyors, solder vessels, soldering irons, and peripheral equipment. 3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, and the use of conductive floor mats and other measures to minimize shock loads is recommended. 4. Ground all fixtures and instruments, or protect with anti-static measures. 5. Avoid the use of Styrofoam or other highly static-prone materials for storage of completed board assemblies. Document Number: Rev.*B Page 74 of 201

75 6.3 Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: 1. Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. 2. Discharge of static electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. 3. Corrosive gases, dust, or oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. 4. Radiation, including cosmic radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. 5. Smoke, flame CAUTION: Plastic molded devices are flammable and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Cypress products in other special environmental conditions should consult with sales representatives. Document Number: Rev.*B Page 75 of 201

76 7. Handling Devices Power-Supply Pins In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. All of these pins should be connected externally to the power supply or ground lines, however, in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Be sure to connect the current-supply source with the power pins and GND pins of this device at low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µf be connected as a bypass capacitor between VCC and VSS near this device. A malfunction may occur when the power-supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed operating range of the VCC power supply voltage. As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient fluctuation rate does not exceed 0.1V/μs at a momentary fluctuation such as switching the power supply. Crystal Oscillator Circuit Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1, X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by ground plane, as this is expected to produce stable operation. Evaluate the oscillation introduced by the use of the crystal oscillator by your mount board. Sub Crystal Oscillator The sub-oscillator circuit for devices in this family is low gain to keep current consumption low. To stabilize the oscillation, Cypress recommends a crystal oscillator that meets the following conditions: Surface mount type Size: More than 3.2 mm 1.5 mm Load capacitance: Approximately 6 pf to 7 pf Lead type Load capacitance: Approximately 6 pf to 7 pf Document Number: Rev.*B Page 76 of 201

77 Using an External Clock When using an external clock as an of the main clock, set X0/X1 to the external clock, and the clock to X0. X1(PE3) can be used as a general-purpose I/O port. Similarly, when using an external clock as an of the sub clock, set X0A/X1A to the external clock and the clock to X0A. X1A (P47) can be used as a general-purpose I/O port. Example of Using an External Clock Device Can be used as general-purpose I/O ports. X0(X0A) X1(PE3), X1A (P47) Set as external clock Handling When Using Multi-Function Serial Pin as I 2 C Pin If the application uses the multi-function serial pin as an I 2 C pin, the P-channel transistor of the digital output must be disabled. I 2 C pins need to conform to electrical limitations like other pins, however, and avoid connecting to live external systems with the MCU power off. C Pin Devices in this series contain a regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. Some laminated ceramic capacitors have a large capacitance variation due to thermal fluctuation. Please select a capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of the device. A smoothing capacitor of about 4.7 μf would be recommended for this series. Device C VSS CS GND Mode Pins (MD0) Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays low, the distance between the mode pins and VCC pins or VSS pins is as short as possible, and the connection impedance is low when the pins are pulled up/down such as for switching the pin level and rewriting the flash memory data. This is important to prevent the device from erroneously switching to test mode as a result of noise. Document Number: Rev.*B Page 77 of 201

78 Notes on Power-on Turn power on/off in the following order or at the same time. The device operates normally after all power on. VBAT only Power-on is possible when VBAT and VCC turns Power-on and Hibernation control is setting and then VCC turns Power-off. About Hibernation control, see Chapter 7-2: VBAT Domain(B) in FM4 Family Peripheral Manual Main Part( ). Turning on: Turning off: VBAT VCC USBVCC0 VBAT VCC USBVCC1 VCC AVCC AVRH AVRH AVCC VCC USBVCC1 VCC VBAT USBVCC0 VCC VBAT Serial Communication There is a possibility of receiving incorrect data as a result of noise or other issues introduced by the serial communication. Take care to design the printed circuit board to minimize noise. Consider the case of introducing error as a result of noise, perform error detection such as by applying a checksum of data at the end. If an error is detected, retransmit the data. Differences in Characteristics within the Product Line The electric characteristics including power consumption, ESD, latch-up, noise, and oscillation differ among members of the product line because chip layout and memory structures are not the same; for example, different sizes, flash versus ROM, etc. If you are switching to a different product of the same series, please make sure to evaluate the electric characteristics. Pull-up Function of 5 V Tolerant I/O Please do not the signal more than VCC voltage at the time of Pull-Up function use of 5 V tolerant I/O. Pin Doubled as Debug Function The pin doubled as TDO/TMS/TDI/TCK/TRSTX, SWO/SWDIO/SWCLK should be used as output only. Do not use as. Document Number: Rev.*B Page 78 of 201

79 AHB-APB Bridge : APB2 (Max 100 MHz) AHB-APB Bridge : APB1 (Max 200 MHz) AHB-AHB Bridge (Master) AHB-AHB Bridge (Slave) AHB-APB Bridge: APB0(Max 100 MHz) Multi-layer AHB (Max 200 MHz) S6E2C5 Series 8. Block Diagram S6E2C5AH/J/L, S6E2C59H/J/L, S6E2C58H/J/L TRSTX,TCK, TDI,TMS TDO TRACEDx, TRACECLK INITX SWJ-DP TPIU/ETB* Cortex-M4 Core MHz(Max) D FPU MPU NVIC Sys CLK Dual-Timer Watchdog Timer (Software) Clock Reset Generator Watchdog Timer (Hardware) CSV ETM/HTM* ROM Table MainFlash I/F Trace Buffer (16 Kbytes) Security DualFlash I/F SRAM0 96/144/192 Kbytes SRAM1 32 Kbytes SRAM2 32 Kbytes MainFlash/DualFlash 2 Mbytes(1M+1M)/ 1.5 Mbytes(1M+0.5M)/ 1 Mbytes(MainOnly) USB2.0 (Host/ Func) USB2.0 (Host/ Func) DMAC 8ch. PHY PHY USBVCC0 UDP0,UDM0 UHCONX0 USBVCC1 UDP1,UDM1 UHCONX1 DSTC CAN ch.0 TX0,RX0 CAN ch.1 TX1,RX1 CAN ch.2 TX2,RX2 X0 X1 X0A X1A CROUT AVCC, AVSS, AVRH, AVRL ANxx ADTGx Source Clock Main Osc 12-bit A/D Converter Unit 0 Unit 1 PLL VBAT Domain Sub Osc Unit 2 CR 100 khz CR 4 MHz PRG-CRC Accelerator I2S 1unit GPIO PIN-Function-Ctrl MODE-Ctrl SD-CARD I/F I2SMCLK, I2SWS, I2SCK I2SDI I2SDO P0x, P1x,... PFx MD0, MD1 S_CLK,S_CMD S_DATAx S_CD,S_WP TIOAx TIOBx Base Timer 16-bit 32ch./ 32-bit 16ch. Hi-Speed Quad SPI Q_SCK, Q_CSx Q_IOx MADx AINx BINx ZINx IC0x FRCK0 DTTI0X RTO0x QPRC 4ch. A/D Activation Compare 6ch. 16-bit Input Capture 4ch. 16-bit Free-run Timer 3ch. 16-bit Output Compare 6ch. Waveform Generator 3ch. External Bus I/F CAN Prescaler USB Clock Ctrl I2S Clock Ctrl LVD Ctrl IRQ-Monitor CRC Accelerator PLL PLL Power-On Reset LVD Regulator MADATAx MCSXx,MDQMx, MOEX,MWEX, MALE,MRDY, MNALE,MNCLE, MNWEX,MNREX, MCLKOUT,MSDWEX, MSDCLK,MSDCKE, MRASX,MCASX C 16-bit PPG 3ch. Watch Counter Multi-function Timer 3 Deep Standby Ctrl WKUPx VBAT VWAKEUP VREGCTL RTCCO, SUBOUT DAx VBAT Domain Real-Time Clock Port Ctrl. 12-bit D/A Converter 2units Peripheral Clock Gating Low-speed CR Prescaler External Interrupt Controller 32-pin + NMI Multi-function Serial I/F 16ch. (with FIFO ch.0 to ch.7) HW flow control(ch.4,5) INTx NMIX SCKx SINx SOTx CTSx RTSx Document Number: Rev.*B Page 79 of 201

80 9. Memory Size See Memory size in 1. Product Lineup to confirm the memory size. 10. Memory Map Memory Map (1) 0x41FF_FFFF Peripherals Area Reserved See "Memory Map (2) and (3)" for メモリサイズの詳細は次項の メモリマップ (2) memory を参照してください size details. 0x4008_1000 0x4008_0000 Programmable-CRC 0x4007_0000 CAN-FD (CAN ch.2) 0x4006_F000 GPIO 0x4006_E000 SD-Card I/F 0xFFFF_FFFF 0x4006_D000 Reserved Reserved 0x4006_C000 I2S 0xE010_0000 0xE000_0000 0xD000_0000 Cortex-M4 Private Peripherals Reg. Area Reserved 0x4006_4000 0x4006_3000 CAN ch.1 External Device 0x4006_2000 CAN ch.0 Area 0x4006_1000 DSTC 0x4006_0000 DMAC 0x6000_0000 0x4005_0000 USB ch.1 0x4004_0000 USB ch.0 Reserved 0x4003_F000 EXT-bus I/F 0x4400_0000 0x4003_E000 Reserved 32 Mbytes 0x4003_D000 I2S prescaler 0x4200_0000 Bit band alias 0x4003_C800 Reserved 0x4003_C100 Peripheral Clock Gating Peripherals 0x4003_C000 Low Speed CR Prescaler 0x4000_0000 0x4003_B000 RTC/Port Ctrl 0x4003_A000 Watch Counter Reserved 0x4003_9000 CRC 0x2400_0000 0x4003_8000 MFS 32 Mbytes 0x4003_7000 CAN prescaler 0x2200_0000 Bit band alias 0x4003_6000 USB Clock ctrl 0x4003_5000 LVD/DS mode DualFlash 0x4003_4000 Reserved 0x200F_0000 0x4003_3000 D/AC 0x4003_2000 Reserved Reserved 0x4003_1000 Int-Req.Read 0x4003_0000 EXTI 0x2004_8000 0x4002_F000 Reserved 0x2004_0000 SRAM2 0x4002_E000 CR Trim 0x2003_8000 SRAM1 0x2000_0000 Reserved Reserved 0x1FFF_0000 SRAM0 0x4002_8000 0x0050_0000 Reserved 0x4002_7000 A/DC 0x0040_0000 Security/CR Trim 0x4002_6000 QPRC 0x4002_5000 Base Timer MainFlash 0x4002_4000 PPG 0x4002_3000 Reserved 0x0000_0000 0x4002_2000 MFT Unit2 0x4002_1000 MFT Unit1 0x4002_0000 MFT Unit0 0x4001_6000 0x4001_5000 0x4001_3000 0x4001_2000 0x4001_1000 0x4001_0000 0x4000_1000 0x4000_0000 Reserved Dual Timer Reserved SW WDT HW WDT Clock/Reset Reserved MainFlash I/F Document Number: Rev.*B Page 80 of 201

81 MainFlash 40 Kbytes MainFlash 40 Kbytes MainFlash 40 Kbytes MainFlash 1 Mbytes MainFlash 1.5 Mbytes MainFlash 2 Mbytes S6E2C5 Series Memory Map (2) S6E2C5AH/J/L S6E2C59H/J/L S6E2C58H/J/L 0x2020_0000 0x2020_0000 0x2020_0000 Reserved Reserved Reserved 0x2004_8000 0x2004_8000 0x2004_8000 SRAM2 SRAM2 0x2004_ Kbytes 0x2004_ Kbytes 0x2004_0000 SRAM1 SRAM1 0x2003_ Kbytes 0x2003_ Kbytes 0x2003_8000 SRAM2 32 Kbytes SRAM1 32 Kbytes Reserved Reserved Reserved 0x2000_0000 0x2000_0000 0x2000_0000 0x1FFD_0000 SRAM0 192 Kbytes Reserved 0x1FFE_0000 SRAM0 128 Kbytes Reserved 0x1FFF_0000 0x0041_0000 0x0041_0000 0x0041_0000 SRAM0 64 Kbytes Reserved SA0-3(#1) (8KBx4) SA0-3(#1) (8KBx4) SA0-3(#1) (8KBx4) 0x0040_8000 0x0040_8000 0x0040_8000 0x0040_6000 SA3(#0) (8KB) 0x0040_6000 SA3(#0) (8KB) 0x0040_6000 SA3(#0) (8KB) 0x0040_4000 General purpose 0x0040_4000 General purpose 0x0040_4000 General purpose 0x0040_2000 CR trimming 0x0040_2000 CR trimming 0x0040_2000 CR trimming 0x0040_0000 Security 0x0040_0000 Security 0x0040_0000 Security Reserved 0x0020_0000 Reserved SA9-23(#1) (64KBx15) 0x0018_0000 SA9-15(#1) (64KBx7) SA8(#1) (32KB) SA8(#1) (32KB) 0x0010_0000 SA4-7(#1) (8KBx4) 0x0010_0000 SA4-7(#1) (8KBx4) 0x0010_0000 Reserved SA9-23(#0) (64KBx15) SA9-23(#0) (64KBx15) SA9-23(#0) (64KBx15) SA8(#0) (32KB) SA8(#0) (32KB) SA8(#0) (32KB) 0x0000_0000 SA4-7(#0) (8KBx4) 0x0000_0000 SA4-7(#0) (8KBx4) 0x0000_0000 SA4-7(#0) (8KBx4) * See S6E2CC/S6E2C5/S6E2C4/S6E2C3/S6E2C2/S6E2C1 Series Flash Programming Manual to confirm the detail of flash Memory. Document Number: Rev.*B Page 81 of 201

82 DualFlash 32 Kbytes DualFlash 512 Kbytes +32 Kbytes DualFlash 1 Mbytes +32 Kbytes MainFlash 8 Kbytes MainFlash 8 Kbytes MainFlash 8 Kbytes MainFlash 1 Mbytes MainFlash 1 Mbytes MainFlash 1 Mbytes S6E2C5 Series Memory Map (2) during Dual Flash Mode S6E2C5AH/J/L S6E2C59H/J/L S6E2C58H/J/L 0x2020_0000 0x2020_0000 0x2020_0000 Reserved SA9-23(#1) (64KBx15) 0x2018_0000 SA9-15(#1) (64KBx7) Reserved SA8(#1) (32KB) SA8(#1) (32KB) 0x2010_0000 SA4-7(#1) (8KBx4) 0x2010_0000 SA4-7(#1) (8KBx4) 0x2010_0000 0x200F_8000 SA0-3(#1) (8KBx4) 0x200F_8000 SA0-3(#1) (8KBx4) 0x200F_8000 SA0-3(#1) (8KBx4) Reserved Reserved Reserved 0x2004_8000 0x2004_8000 0x2004_8000 SRAM2 SRAM2 0x2004_ Kbytes 0x2004_ Kbytes 0x2004_0000 SRAM1 SRAM1 0x2003_ Kbytes 0x2003_ Kbytes 0x2003_8000 SRAM2 32 Kbytes SRAM1 32 Kbytes Reserved Reserved Reserved 0x2000_0000 0x2000_0000 0x2000_0000 0x1FFD_0000 SRAM0 192 Kbytes Reserved 0x1FFE_0000 SRAM0 128 Kbytes Reserved 0x1FFF_0000 0x0041_0000 0x0041_0000 0x0041_0000 SRAM0 64 Kbytes Reserved Reserved Reserved 0x0040_8000 0x0040_8000 0x0040_8000 Reserved 0x0040_6000 SA3(#0) (8KB) 0x0040_6000 SA3(#0) (8KB) 0x0040_6000 SA3(#0) (8KB) 0x0040_4000 General purpose 0x0040_4000 General purpose 0x0040_4000 General purpose 0x0040_2000 CR trimming / HTM 0x0040_2000 CR trimming / HTM 0x0040_2000 CR trimming / HTM 0x0040_0000 Security 0x0040_0000 Security 0x0040_0000 Security Reserved Reserved Reserved 0x0010_0000 0x0010_0000 0x0010_0000 SA9-23(#0) (64KBx15) SA9-23(#0) (64KBx15) SA9-23(#0) (64KBx15) SA8(#0) (32KB) SA8(#0) (32KB) SA8(#0) (32KB) 0x0000_0000 SA4-7(#0) (8KBx4) 0x0000_0000 SA4-7(#0) (8KBx4) 0x0000_0000 SA4-7(#0) (8KBx4) Document Number: Rev.*B Page 82 of 201

83 Memory Map (3) S6E2C5AH S6E2C5AJ S6E2C5AL 0xD000_0000 0xD000_0000 0xD000_0000 Hi-Speed Quad SPI 256 Mbytes Hi-Speed Quad SPI 256 Mbytes 0xC000_0000 0xC000_0000 0xC000_0000 Reserved Reserved Reserved 0x8000_0000 0x8000_0000 0x8000_0000 SDRAM 256 Mbytes SDRAM 256 Mbytes 0x7000_0000 0x7000_0000 0x7000_0000 SRAM /NOR Flash Memory /NAND Flash Memory 256 Mbytes SRAM /NOR Flash Memory /NAND Flash Memory 256 Mbytes 0x6000_0000 0x6000_0000 0x6000_0000 SRAM /NOR Flash Memory /NAND Flash Memory 256 Mbytes Document Number: Rev.*B Page 83 of 201

84 Peripheral Address Map Start Address End Address Bus Peripherals 0x4000_0000 0x4000_0FFF MainFlash I/F register AHB 0x4000_1000 0x4000_FFFF Reserved 0x4001_0000 0x4001_0FFF Clock/reset control 0x4001_1000 0x4001_1FFF Hardware watchdog timer 0x4001_2000 0x4001_2FFF Software watchdog timer APB0 0x4001_3000 0x4001_4FFF Reserved 0x4001_5000 0x4001_5FFF Dual-timer 0x4001_6000 0x4001_FFFF Reserved 0x4002_0000 0x4002_0FFF Multi-Function Timer unit 0 0x4002_1000 0x4002_1FFF Multi-Function Timer unit 1 0x4002_2000 0x4002_2FFF Multi-Function Timer unit 2 0x4002_3000 0x4002_3FFF Reserved 0x4002_4000 0x4002_4FFF PPG 0x4002_5000 0x4002_5FFF APB1 Base timer 0x4002_6000 0x4002_6FFF Quadrature position/revolution counter 0x4002_7000 0x4002_7FFF A/D converter 0x4002_8000 0x4002_DFFF Reserved 0x4002_E000 0x4002_EFFF Internal CR trimming 0x4002_F000 0x4002_FFFF Reserved 0x4003_0000 0x4003_0FFF External interrupt controller 0x4003_1000 0x4003_1FFF Interrupt request batch-read function 0x4003_2000 0x4003_2FFF Reserved 0x4003_3000 0x4003_3FFF D/A converter 0x4003_4000 0x4003_4FFF Reserved 0x4003_5000 0x4003_57FF Low voltage detector 0x4003_5800 0x4003_5FFF Deep standby mode Controller 0x4003_6000 0x4003_6FFF USB clock generator 0x4003_7000 0x4003_7FFF CAN prescaler 0x4003_8000 0x4003_8FFF APB2 Multi-function serial interface 0x4003_9000 0x4003_9FFF CRC 0x4003_A000 0x4003_AFFF Watch counter 0x4003_B000 0x4003_BFFF RTC/port control 0x4003_C000 0x4003_C0FF Low-speed CR prescaler 0x4003_C100 0x4003_C7FF Peripheral clock gating 0x4003_C800 0x4003_CFFF Reserved 0x4003_D000 0x4003_DFFF I 2 S prescaler 0x4003_E000 0x4003_EFFF Reserved 0x4003_F000 0x4003_FFFF External memory interface Document Number: Rev.*B Page 84 of 201

85 Start Address End Address Bus Peripherals 0x4004_0000 0x4004_FFFF USB ch 0 0x4005_0000 0x4005_FFFF USB ch 1 0x4006_0000 0x4006_0FFF DMAC register 0x4006_1000 0x4006_1FFF DSTC register 0x4006_2000 0x4006_2FFF CAN ch 0 0x4006_3000 0x4006_3FFF CAN ch 1 0x4006_4000 0x4006_BFFF Reserved 0x4006_C000 0x4006_CFFF I 2 S AHB 0x4006_D000 0x4006_DFFF Reserved 0x4006_E000 0x4006_EFFF SD card I/F 0x4006_F000 0x4006_FFFF GPIO 0x4007_0000 0x4007_FFFF CAN-FD (CAN ch 2) 0x4008_0000 0x4008_0FFF Programmable-CRC 0x4008_1000 0x41FF_FFFF Reserved 0x200E_0000 0x200E_FFFF Workflash I/F register 0xD000_0000 0xDFFF_FFFF High-speed quad SPI control register Document Number: Rev.*B Page 85 of 201

86 11. Pin Status in Each CPU State The terms used for pin status have the following meanings: INITX = 0 INITX = 1 SPL = 0 SPL = 1 Input This is the period when the INITX pin is at the L level. This is the period when the INITX pin is at the H level. This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 0. This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 1. Indicates that the function can be used. Internal fixed at 0 Hi-Z This is the status that the function cannot be used. Internal is fixed at L. Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state. Setting disabled Indicates that the setting is disabled. state s the state that was immediately prior to entering the current mode. If a built-in peripheral function is operating, the output follows the peripheral function. If the pin is being used as a port, that output is maintained. Analog is Trace output GPIO selected Indicates that the analog is. Indicates that the trace function can be used. In Deep standby mode, pins switch to the general-purpose I/O port. Setting prohibition Prohibition of a setting by specification limitation Document Number: Rev.*B Page 86 of 201

87 List of Pin Behavior by Mode State Pin Status Type A B C Function Group GPIO selected Main crystal oscillator pin/ external main clock selected GPIO selected External main clock selected Main crystal oscillator output pin INITX pin Power-On Reset or Low- Voltage Detection State INITX Input State Device Internal Reset State Run mode or Sleep mode State Timer mode, RTC mode, or Stop mode State Return Deep Standby RTC From Deep Mode or Deep Standby Standby Stop mode State Mode State Power Power Power Supply Power Supply Supply Power Supply Power Supply Supply Unstable Stable Stable Stable Stable Stable INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 SPL=0 SPL=1 SPL=0 SPL=1 - GPIO Hi-Z/intern Hi-Z/intern selected, Setting Setting al al internal disabled disabled fixed fixed state state fixed at 0 at 0 at 0 Setting disabled Input Setting disabled Setting disabled Hi-Z/ internal fixed at 0/ or enable Pull-up/ Input Setting disabled Setting disabled Hi-Z/ internal fixed at 0 Pull-up/ Input Input Setting disabled Setting disabled Hi-Z/ internal fixed at 0 Pull-up/ Input Input state state Pull-up/ Input Input state state Input Hi-Z/intern al fixed at 0 Hi-Z/intern al fixed at 0 Input GPIO selected, internal fixed at 0 state Input Hi-Z/intern al fixed at 0 Hi-Z/intern al fixed at 0 state while oscillator active/ When oscillation stops* 1, it will be Hi-Z/ Internal fixed at 0 Pull-up/ Input Pull-up/ Input Pull-up/ Input Pull-up/ Input GPIO selected Input Enabled GPIO selected State Pull-up/ Input D Mode pin Input Input Input Input Input Input Input Input Input E Mode pin GPIO selected Input Setting disabled Input Setting disabled Input Setting disabled Input state Input state Input Hi-Z/ Input GPIO selected Input Hi-Z/ Input GPIO selected Document Number: Rev.*B Page 87 of 201

88 Pin Status Type F G H I Function Group NMIX selected Resource other than above selected GPIO selected JTAG selected GPIO selected JTAG selected Resource other than above selected GPIO selected Resource selected GPIO selected Power-On Reset or Low- Voltage Detection State INITX Input State Device Internal Reset State Run mode or Sleep mode State Timer mode, RTC mode, or Stop mode State Return Deep Standby RTC From Deep Mode or Deep Standby Standby Stop mode State Mode State Power Power Power Supply Power Supply Supply Power Supply Power Supply Supply Unstable Stable Stable Stable Stable Stable INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 SPL=0 SPL=1 SPL=0 SPL=1 - Setting disabled Hi-Z Hi-Z Setting disabled Hi-Z Setting disabled Hi-Z Setting disabled Hi-Z/ Pull-up/ Setting disabled Pull-up/ Setting disabled Hi-Z/ Setting disabled Hi-Z/ Pull-up/ Setting disabled Pull-up/ Setting disabled Hi-Z/ state state state state state state state state state Hi-Z/ internal fixed at 0 state Hi-Z/ internal fixed at 0 state Hi-Z/Intern al fixed at 0 Hi-Z/Intern al fixed at 0 WKUP state GPIO selected, internal fixed at 0 state GPIO selected, internal fixed at 0 GPIO selected, internal fixed at 0 Hi-Z/ WKUP state Hi-Z/ internal fixed at 0 state Hi-Z/Intern al fixed at 0 Hi-Z/intern al fixed at 0 state GPIO selected state GPIO selected state GPIO selected GPIO selected Document Number: Rev.*B Page 88 of 201

89 Pin Status Type J K L Function Group Analog output selected External interrupt enable selected Resource other than above selected GPIO selected External interrupt enable selected Resource other than above selected GPIO selected Analog selected Resource other than above selected GPIO selected Power-On Reset or Low- Voltage Detection State Power Supply Unstable INITX Input State Device Internal Reset State Power Supply Stable Run mode or Sleep mode State Power Supply Stable Timer mode, RTC mode, or Stop mode State Power Supply Stable Return Deep Standby RTC From Deep Mode or Deep Standby Standby Stop mode State Mode State Power Supply Stable Power Supply Stable INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 SPL=0 SPL=1 SPL=0 SPL=1 - Hi-Z Setting disabled Hi-Z Hi-Z Setting disabled Hi-Z/ Setting disabled Hi-Z/ Hi-Z/ internal fixed at 0/ analog Setting disabled Hi-Z/ Setting disabled Hi-Z/ Hi-Z/ internal fixed at 0/ analog Setting disabled state state Hi-Z/ internal fixed at 0/ analog state *2 *3 state state Hi-Z/ internal fixed at 0/ analog state state Hi-Z/intern al fixed at 0 state Hi-Z/intern al fixed at 0 Hi-Z/ internal fixed at 0/ analog Hi-Z/intern al fixed at 0 GPIO selected, internal fixed at 0 GPIO selected, internal fixed at 0 Hi-Z/ internal fixed at 0/ analog GPIO selected, internal fixed at 0 Hi-Z/intern al fixed at 0 Hi-Z/intern al fixed at 0 Hi-Z/ internal fixed at 0/ analog Hi-Z/intern al fixed at 0 GPIO selected GPIO selected Hi-Z/ internal fixed at 0/ analog GPIO selected Document Number: Rev.*B Page 89 of 201

90 Pin Status Type M N Function Group Analog selected External interrupt enable selected Resource other than above selected GPIO selected Analog selected Trace selected Resource other than above selected GPIO selected Power-On Reset or Low- Voltage Detection State INITX Input State Device Internal Reset State Run mode or Sleep mode State Timer mode, RTC mode, or Stop mode State Return Deep Standby RTC From Deep Mode or Deep Standby Standby Stop mode State Mode State Power Power Power Supply Power Supply Supply Power Supply Power Supply Supply Unstable Stable Stable Stable Stable Stable INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 SPL=0 SPL=1 SPL=0 SPL=1 - Hi-Z Setting disabled Hi-Z Setting disabled Hi-Z/ internal fixed at 0/ analog Setting disabled Hi-Z/ internal fixed at0/ analog Setting disabled Hi-Z/ internal fixed at 0/ analog Setting disabled Hi-Z/ internal fixed at 0/ analog Setting disabled Hi-Z/ internal fixed at 0/ analog state Hi-Z/ internal fixed at 0/ analog state Hi-Z/ internal fixed at 0/ analog state Hi-Z/ internal fixed at 0/ analog state Hi-Z/ internal fixed at 0/ analog state Hi-Z/intern al fixed at 0 Hi-Z/ internal fixed at 0/ analog Trace output Hi-Z/intern al fixed at 0 Hi-Z/ internal fixed at 0/ analog GPIO selected, internal fixed at 0 Hi-Z/ internal fixed at 0/ analog GPIO selected, internal fixed at 0 Hi-Z/ internal fixed at 0/ analog Hi-Z/intern al fixed at 0 Hi-Z/ internal fixed at 0/ analog Hi-Z/intern al fixed at 0 Hi-Z/ internal fixed at 0/ analog GPIO selected Hi-Z/ internal fixed at 0/ analog GPIO selected Document Number: Rev.*B Page 90 of 201

91 Pin Status Type O P Function Group Analog selected Trace selected External interrupt enable selected Resource other than above selected GPIO selected Analog selected WKUP Resource other than above selected GPIO selected Power-On Reset or Low- Voltage Detection State INITX Input State Device Internal Reset State Run mode or Sleep mode State Timer mode, RTC mode, or Stop mode State Return Deep Standby RTC From Deep Mode or Deep Standby Standby Stop mode State Mode State Power Power Power Supply Power Supply Supply Power Supply Power Supply Supply Unstable Stable Stable Stable Stable Stable INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 SPL=0 SPL=1 SPL=0 SPL=1 - Hi-Z/ Hi-Z/ Hi-Z/ Hi-Z/ Hi-Z/ Hi-Z/ Hi-Z/ internal internal internal internal internal internal internal fixed fixed fixed fixed fixed fixed fixed Hi-Z at 0/ at 0/ at 0/ at 0/ at 0/ at 0/ at 0/ analog analog analog analog analog analog analog Setting disabled Hi-Z Setting disabled Setting disabled Hi-Z/ internal fixed at 0/ analog Setting disabled Setting disabled Hi-Z/ internal fixed at 0/ analog Setting disabled state Hi-Z/ internal fixed at 0/ analog state state Hi-Z/ internal fixed at 0/ analog state Trace output state Hi-Z/intern al fixed at 0 Hi-Z/ internal fixed at 0/ analog state Hi-Z/intern al fixed at 0 GPIO selected, internal fixed at 0 Hi-Z/ internal fixed at 0/ analog WKUP GPIO selected, internal fixed at 0 Hi-Z/intern al fixed at 0 Hi-Z/ internal fixed at 0/ analog Hi-Z/ WKUP Hi-Z/intern al fixed at 0 Hi-Z/ internal fixed at 0/ analog GPIO selected Hi-Z/ internal fixed at 0/ analog GPIO selected Document Number: Rev.*B Page 91 of 201

92 Pin Status Type Q R Function Group WKUP External interrupt enable selected Resource other than above selected GPIO selected GPIO selected USB I/O pin Power-On Reset or Low- Voltage Detection State INITX Input State Device Internal Reset State Run mode or Sleep mode State Timer mode, RTC mode, or Stop mode State Return Deep Standby RTC From Deep Mode or Deep Standby Standby Stop mode State Mode State Power Power Power Supply Power Supply Supply Power Supply Power Supply Supply Unstable Stable Stable Stable Stable Stable INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 SPL=0 SPL=1 SPL=0 SPL=1 - Hi-Z/ WKUP WKUP Setting disabled Hi-Z Hi-Z Setting disabled Setting disabled Hi-Z/ Hi-Z/ Setting disabled Setting disabled Hi-Z/ Hi-Z/ Setting disabled state state Hi-Z at transmission/ / internal fixed at 0 at reception state state Hi-Z at transmission/ / internal fixed at 0 at reception state Hi-Z/intern al fixed at 0 Hi-Z/intern al fixed at 0 Hi-Z at transmission/ / internal fixed at 0 at reception GPIO selected, internal fixed at 0 GPIO selected, internal fixed at 0 Hi-Z/ Hi-Z/intern al fixed at 0 Hi-Z/intern al fixed at 0 Hi-Z/ WKUP GPIO selected GPIO selected Hi-Z/ V Ethernet I/O selected *4 Resource other than above selected GPIO selected Setting disabled Hi-Z Setting disabled Hi-Z/ Setting disabled Hi-Z/ state state state Hi-Z/intern al fixed at 0 GPIO selected, internal fixed at 0 Hi-Z/intern al fixed at "0 GPIO selected Document Number: Rev.*B Page 92 of 201

93 Pin Status Type W Function Group Ethernet /output selected *4 External interrupt enable selected Resource other than above selected GPIO selected Power-On Reset or Low- Voltage Detection State Power Supply Unstable INITX Input State Device Internal Reset State Power Supply Stable Run mode or Sleep mode State Power Supply Stable Timer mode, RTC mode, or Stop mode State Power Supply Stable Return Deep Standby RTC From Deep Mode or Deep Standby Standby Stop mode State Mode State Power Supply Stable Power Supply Stable INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 SPL=0 SPL=1 SPL=0 SPL=1 - Setting disabled Hi-Z Setting disabled Hi-Z/ Setting disabled Hi-Z/ state state state Hi-Z/intern al fixed at 0 GPIO selected, internal fixed at 0 Hi-Z/intern al fixed at 0 GPIO selected *1: Oscillation is stopped at sub Timer mode, sub CR Timer mode, RTC mode, Stop mode, Deep Standby RTC mode, and Deep Standby Stop mode. *2: state at Timer mode. GPIO selected internal fixed at 0 at RTC mode, Stop mode. *3: state at Timer mode. Hi-Z/internal fixed at 0 at RTC mode, Stop mode. *4: It shows the case selected by EPFR14.E_SPLC register. Document Number: Rev.*B Page 93 of 201

94 List of VBAT Domain Pin Status VBAT Pin Status Type S T U Function Group GPIO selected Sub crystal oscillator pin/ external sub clock selected GPIO selected External sub clock selected Sub crystal oscillator output pin Resource selected GPIO selected Poweron reset*1 Power Supply Unstabl e INITX Input State Device Internal Reset State Power Supply Stable Run mode or Sleep mode State Power Supply Stable Timer Mode, RTC mode, or Stop mode State Power Supply Stable Deep Standby RTC mode or Deep Standby Stop mode State Power Supply Stable Return From Deep Standby Mode State Power Supply Stable VBAT RTC Mode State Power Supply Stable INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 - - SPL=0 SPL=1 SPL=0 SPL= Setting disabled Input state Input Setting disabled state Setting disabled state Hi-Z/ internal fixed at 0/ or enable Hi-Z state state state Input state state state state state Input state state state state state Input state state state/ When oscillation stops, Hi-Z*2 state state Input state state state/ When oscillation stops, Hi-Z*2 state state Input state state state/ When oscillation stops, Hi-Z*2 state state Input state state state/ When oscillation stops, Hi-Z*2 state state Input state state state state Setting prohibition state Setting prohibition state state state Return From VBAT RTC Mode State Power Supply Stable - state - state state state *1: When VBAT and VCC power on. *2: When the SOSCNTL bit in the WTOSCCNT register is 0, the sub crystal oscillator output pin is maintained in the state. When the SOSCNTL bit in the WTOSCCNT register is 1, oscillation is stopped at Stop mode and Deep Standby Stop mode Document Number: Rev.*B Page 94 of 201

95 12. Electrical Characteristics 12.1 Absolute Maximum Ratings Parameter Symbol Min Rating Max Unit Power supply voltage *1,*2 VCC VSS VSS V Power supply voltage (for USB) *1,*3 USBVCC0 VSS VSS V Power supply voltage (for USB) *1,*3 USBVCC1 VSS VSS V Power supply voltage (VBAT) *1,*4 VBAT VSS VSS V Remarks Analog power supply voltage *1,*5 AVCC VSS VSS V Analog reference voltage *1,*5 AVRH VSS VSS V VSS VCC ( 6.5 V) V Except for USB pin Input voltage *1 USBVCC VSS VI ( 6.5 V) V USB ch 0 pin VSS USBVCC ( 6.5 V) V USB ch 1 pin VSS VSS V 5V tolerant Analog pin voltage *1 VIA VSS AVCC ( 6.5 V) V Output voltage *1 VO VSS VCC ( 6.5 V) V 10 ma 4 ma type 20 ma 8 ma type L level maximum output current *6 IOL - 20 ma 10 ma type 20 ma 12 ma type 22.4 ma I 2 C Fm+ 4 ma 4 ma type 8 ma 8 ma type L level average output current *7 IOLAV - 10 ma 10 ma type 12 ma 12 ma type 20 ma I 2 C Fm+ L level total maximum output current IOL ma L level total maximum output current *8 IOLAV - 50 ma - 10 ma 4 ma type H level maximum output current *6 IOH ma 8 ma type - 20 ma 10 ma type - 20 ma 12 ma type - 4 ma 4 ma type H level average output current *7 IOHAV - -8 ma 8 ma type - 10 ma 10 ma type - 12 ma 12 ma type H level total maximum output current IOH ma H level total average output current *8 IOHAV ma Power consumption PD mw Storage temperature TSTG C *1: These parameters are based on the condition that VSS = AVSS = 0.0 V. *2: VCC must not drop below VSS V. *3: USBVCC0, USBVCC1 must not drop below VSS V. *4: VBAT must not drop below VSS V. *5: Ensure that the voltage does not exceed VCC V, for example, when the power is turned on. *6: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *7: The average output current is defined as the average current value flowing through any one of the corresponding pins for a 100-ms period. Document Number: Rev.*B Page 95 of 201

96 *8: The total average output current is defined as the average current value flowing through all of corresponding pins for a 100-ms period. WARNING: Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings. Document Number: Rev.*B Page 96 of 201

97 12.2 Recommended Operating Conditions Parameter Symbol Conditions Min Value Max Unit Power supply voltage VCC *7 5.5 V Power supply voltage (for USB ch 0) USBVCC0 - Power supply voltage (for USB ch 1) USBVCC ( VCC) 5.5 ( VCC) 3.6 ( VCC) 5.5 ( VCC) V V *1 *2 *3 *4 Remarks Power supply voltage (VBAT) VBAT V Analog power supply voltage AVCC V AV CC = V CC Analog reference voltage AVRH - *6 AVCC V AVRL - AVSS AVSS V Operating Junction temperature TJ C temperature Ambient temperature TA *5 C *1: When P81/UDP0 and P80/UDM0 pins are used as USB (UDP0, UDM0) *2: When P81/UDP0 and P80/UDM0 pins are used as GPIO (P81, P80) *3: When P83/UDP1 and P82/UDM1 pins are used as USB (UDP1, UDM1) *4: When P83/UDP1 and P82/UDM1 pins are used as GPIO (P83, P82) *5: The maximum temperature of the ambient temperature (TA) can guarantee a range that does not exceed the junction temperature (TJ). The calculation formula of the ambient temperature (TA) is: TA (Max) = TJ(Max) - Pd(Max) θja Pd: Power dissipation (W) θja: Package thermal resistance ( C/W) Pd (Max) = VCC ICC (Max) + Σ (IOL VOL) + Σ ((VCC-VOH) (- IOH)) IOL: L level output current IOH: H level output current VOL: L level output voltage VOH: H level output voltage *6: The minimum value of analog reference voltage depends on the value of compare clock cycle (Tcck). See bit A/D Converter for the details. *7: For the voltage range between Vcc(min) and the low voltage detection reset (VDH), the MCU must be clocked from either the High-speed CR or the low-speed CR. Document Number: Rev.*B Page 97 of 201

98 Package thermal resistance and maximum permissible power for each package are shown below. The operation is guaranteed maximum permissible power or less for semiconductor devices. Table for Package Thermal Resistance and Maximum Permissible Power Package LQS144 (0.5-mm pitch) LQP176 (0.5-mm pitch) LQQ216 (0.4-mm pitch) LBE192 (0.8-mm pitch) Printed Circuit Board Thermal Resistance θja ( C/W) Maximum Permissible Power (mw) TA = +85 C TA = +105 C Single-layered both sides layers Single-layered both sides layers Single-layered both sides layers Single-layered both sides layers WARNING: 1. The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. 2. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. 3. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. 4. Users considering application outside the listed conditions are advised to contact their representatives beforehand. Document Number: Rev.*B Page 98 of 201

99 Calculation Method of Power Dissipation (Pd) The power dissipation is shown in the following formula. Pd = VCC ICC + Σ (IOL VOL) + Σ ((VCC-VOH) (-IOH)) IOL: L level output current IOH: H level output current VOL: L level output voltage VOH: H level output voltage ICC is the current drawn by the device. It can be analyzed as follows. ICC = ICC (INT) + ΣICC (IO) ICC (INT): Current drawn by internal logic and memory, etc. through the regulator ΣICC (IO): Sum of current (I/O switching current) drawn by the output pin For ICC (INT), it can be anticipated by (1) Current Rating in DC Characteristics (This rating value does not include ICC (IO) for a value at pin fixed). For ICC (IO), it depends on system used by customers. The calculation formula is shown below. ICC (IO) = (CINT + CEXT) VCC fsw CINT: Pin internal load capacitance CEXT: External load capacitance of output pin fsw: Pin switching frequency Parameter Symbol Conditions Capacitance Value Pin internal load capacitance CINT 4 ma type 1.93 pf 8 ma type 3.45 pf 12 ma type 3.42 pf Calculate ICC (Max) as follows when the power dissipation can be evaluated by yourself: Measure current value ICC (Typ) at normal temperature (+25 C). Add maximum leakage current value ICC (leak_max) at operating on a value in (1). ICC(Max) = ICC (Typ) + ICC (leak_max) Parameter Symbol Conditions Current Value Maximum leakage current at operating ICC (leak_max) TJ = +125 C TJ = +105 C TJ = +85 C 79.2 ma 39.4 ma 26.5 ma Document Number: Rev.*B Page 99 of 201

100 Current Explanation Diagram ICC A VCC Pd=VCC ICC + Σ(IOL VOL)+Σ((VCC-VOH) (-IOH)) ICC=ICC (INT)+ΣICC (IO) Chip ICC (INT) ΣICC (IO) Regulator A IOL V VOL Flash RAM Logic ICC (IO) VOH V A CEXT IOH Document Number: Rev.*B Page 100 of 201

101 12.3 DC Characteristics Current Rating Table 12-1 Typical and Maximum Current Consumption in Normal Operation(PLL), Code Running from Flash Memory (Flash Accelerator Mode and Trace Buffer Function Enabled) Parameter Power supply current Symbol ICC Pin Name VCC *1: TA = +25 C, VCC = 3.3 V *2: TJ = +125 C, VCC = 5.5 V *3: When all ports are fixed Conditions Frequency* 4 Normal operation *7,*8 (PLL) *5 *6 *5 *6 Value Typ* 1 Max* 2 Unit 200 MHz ma 192 MHz ma 180 MHz ma 160 MHz ma 144 MHz ma 120 MHz ma 100 MHz ma 80 MHz ma 60 MHz ma 40 MHz ma 20 MHz ma 8 MHz ma 4 MHz ma 200 MHz ma 192 MHz ma 180 MHz ma 160 MHz ma 144 MHz ma 120 MHz ma 100 MHz ma 80 MHz ma 60 MHz ma 40 MHz ma 20 MHz ma 8 MHz ma 4 MHz ma *4: Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK *5: When stopping flash accelerator mode and trace buffer function (FRWTR.RWT = 11, FBFCR.BE = 1) *6: When stopping flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 1) Remarks *3 When all peripheral clocks are on *3 When all peripheral clocks are off *7: Firmware being executed during data collection for this table is not being accessed from the MainFlash memory. *8: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit) Document Number: Rev.*B Page 101 of 201

102 Table 12-2 Typical and Maximum Current Consumption in Normal Operation(PLL), Code with Data Accessing Running from Flash Memory (Flash Accelerator Mode and Trace Buffer Function Disabled) Parameter Power supply current Symbol ICC Pin Name VCC *1: TA = +25 C, VCC = 3.3 V *2: TJ = +125 C, VCC = 5.5 V *3: When all ports are fixed Conditions Frequency* 4 Normal operation *7,*8 (PLL) *5 *6 *5 Value Typ* 1 Max* 2 Unit 200 MHz ma 192 MHz ma 180 MHz ma 160 MHz ma 144 MHz ma 120 MHz ma 100 MHz ma 80 MHz ma 60 MHz ma 40 MHz ma 20 MHz ma 8 MHz ma 4 MHz ma 200 MHz ma 192 MHz ma 180 MHz ma 160 MHz ma 144 MHz ma 120 MHz ma 100 MHz ma 80 MHz ma 60 MHz ma 40 MHz ma 20 MHz ma 8 MHz ma 4 MHz ma *4: Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK *6 *3 Remarks When all peripheral clocks are on *3 When all peripheral clocks are off *5: When stopping flash accelerator mode and trace buffer function (FRWTR.RWT = 11, FBFCR.BE = 0) *6: When stopping flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 0) *7: With data access to a MainFlash memory. *8: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit) Document Number: Rev.*B Page 102 of 201

103 Table 12-3 Typical and Maximum Current Consumption in Normal Operation(PLL), Code with Data Accessing Running from Flash Memory (Flash 0 Wait-cycle Mode and Read Access 0 Wait) Parameter Power supply current Symbol ICC Pin Name VCC *1: TA = +25 C, VCC = 3.3 V *2: TJ = +125 C, VCC = 5.5 V *3: When all ports are fixed Conditions Frequency* 4 Normal operation *6,*7 (PLL) *5 *5 Value Typ* 1 Max* 2 Unit 72 MHz ma 60 MHz ma 48 MHz ma 36 MHz ma 24 MHz ma 12 MHz ma 8 MHz ma 4 MHz ma 72 MHz ma 60 MHz ma 48 MHz ma 36 MHz ma 24 MHz ma 12 MHz ma 8 MHz ma 4 MHz ma *4: Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK *3 Remarks When all peripheral clocks are on *3 When all peripheral clocks are off *5: When operating flash 0 wait-cycle mode and read access 0 wait (FRWTR.RWT = 00, FBFCR.SD = 000) *6: With data access to a MainFlash memory. *7: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit) Document Number: Rev.*B Page 103 of 201

104 Table 12-4 Typical and Maximum Current Consumption in Normal Operation (Other Than PLL), Code with Data Accessing Running from Flash Memory (Flash 0 Wait-cycle Mode and Read Access 0 Wait) Parameter Power supply current Symbol ICC Pin Name VCC *1: TA = +25 C, VCC = 3.3 V *2: TJ = +125 C, VCC = 5.5 V *3: When all ports are fixed Conditions Frequency* 4 Normal operation *6, *7 (main oscillation) Normal operation *6 (built-in High-speed CR) Normal operation *6, *8 (sub oscillation) Normal operation *6 (built-in low-speed CR) *5 4 MHz *5 4 MHz *5 32 khz *5 100 khz *4: Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK/2 Value Typ* 1 Max* 2 Unit ma ma ma ma ma ma ma ma Remarks *3 When all peripheral clocks are on *3 When all peripheral clocks are off *3 When all peripheral clocks are on *3 When all peripheral clocks are off *3 When all peripheral clocks are on *3 When all peripheral clocks are off *3 When all peripheral clocks are on *3 When all peripheral clocks are off *5: When operating flash 0 wait-cycle mode and read access 0 wait (FRWTR.RWT = 00, FBFCR.SD = 000) *6: With data access to a MainFlash memory. *7: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit) *8: When using the crystal oscillator of 32 khz (including the current consumption of the oscillation circuit) Document Number: Rev.*B Page 104 of 201

105 Table 12-5 Typical and Maximum Current Consumption in Sleep Operation (PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK/2 Parameter Symbol Pin Name Conditions Frequency* 4 Power supply current ICCS VCC *1: TA = +25 C, VCC = 3.3 V *2: TJ = +125 C, VCC = 5.5 V *3: When all ports are fixed Sleep operation *5 (PLL) Value Typ* 1 Max* 2 Unit 200 MHz ma 192 MHz ma 180 MHz ma 160 MHz ma 144 MHz ma 120 MHz ma 100 MHz ma 80 MHz ma 60 MHz ma 40 MHz ma 20 MHz ma 8 MHz ma 4 MHz ma 200 MHz ma 192 MHz ma 180 MHz ma 160 MHz ma 144 MHz ma 120 MHz ma 100 MHz ma 80 MHz ma 60 MHz ma 40 MHz ma 20 MHz ma 8 MHz ma 4 MHz ma *4: Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK/2 *5: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit) Remarks *3 When all peripheral clocks are on *3 When all peripheral clocks are off Document Number: Rev.*B Page 105 of 201

106 Table 12-6 Typical and Maximum Current Consumption in Sleep Operation(PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK Parameter Symbol Pin Name Conditions Frequency* 4 Power supply current ICCS VCC *1: TA = +25 C, VCC = 3.3 V *2: TJ = +125 C, VCC = 5.5 V *3: When all ports are fixed Sleep operation *5 (PLL) Value Typ* 1 Max* 2 Unit 72 MHz ma 60 MHz ma 48 MHz ma 36 MHz ma 24 MHz ma 12 MHz ma 8 MHz ma 4 MHz ma 72 MHz ma 60 MHz ma 48 MHz ma 36 MHz ma 24 MHz ma 12 MHz ma 8 MHz ma 4 MHz ma *4: Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK *5: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit) Remarks *3 When all peripheral clocks are on *3 When all peripheral clocks are off Document Number: Rev.*B Page 106 of 201

107 Table 12-7 Typical and Maximum Current Consumption in Sleep Operation (Other Than PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK/2 Parameter Power supply current Symbol ICCS Pin Name VCC *1: TA = +25 C, VCC = 3.3 V *2: TJ = +125 C, VCC = 5.5 V *3: When all ports are fixed. Conditions Frequency* 4 Sleep operation *5 (main oscillation) Sleep operation (built-in High-speed CR) Sleep operation *6 (sub oscillation) Sleep operation (built-in low-speed CR) 4 MHz 4 MHz 32 khz 100 khz Value Typ* 1 Max* 2 *4: Frequency is a value of HCLK when PCLK0 = PCLK1 = PCLK2 = HCLK/2 Unit ma ma ma ma ma ma ma ma *5: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit) *6: When using the crystal oscillator of 32 khz (including the current consumption of the oscillation circuit) Remarks *3 When all peripheral clocks are on *3 When all peripheral clocks are off *3 When all peripheral clocks are on *3 When all peripheral clocks are off *3 When all peripheral clocks are on *3 When all peripheral clocks are off *3 When all peripheral clocks are on *3 When all peripheral clocks are off Document Number: Rev.*B Page 107 of 201

108 Table 12-8 Typical and Maximum Current Consumption in Stop Mode, Timer Mode and RTC Mode Parameter Symbol Pin Name Conditions Frequency Value Typ* 1 Max* 2 Unit ma Remarks *3, *4 TA = +25 C ICCH Stop mode ma *3, *4 TA = +85 C ma *3, *4 TA = +105 C ma *3, *4 TA = +25 C Timer mode *5 (main oscillation) 4 MHz ma *3, *4 TA = +85 C ma *3, *4 TA = +105 C ma *3, *4 TA = +25 C Timer mode (built-in High-speed CR) 4 MHz ma *3, *4 TA = +85 C Power supply current ICCT VCC ma ma *3, *4 TA = +105 C *3, *4 TA = +25 C Timer mode *6 (sub oscillation) 32 khz ma *3, *4 TA = +85 C ma *3, *4 TA = +105 C Timer mode (built-in low-speed CR) 100 khz ma ma ma *3, *4 TA = +25 C *3, *4 TA = +85 C *3, *4 TA = +105 C ma *3, *4 TA = +25 C ICCR RTC mode *6 (sub oscillation) 32 khz ma *3, *4 TA = +85 C ma *3, *4 TA = +105 C *1: VCC = 3.3V *2: VCC = 5.5V *3: When all ports are fixed *4: When LVD is off *5: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit) *6: When using the crystal oscillator of 32 khz (including the current consumption of the oscillation circuit) Document Number: Rev.*B Page 108 of 201

109 Table 12-9 Typical and Maximum Current Consumption in Deep Standby Stop Mode, Deep Standby RTC Mode and VBAT Parameter Symbol ICCHD Pin Name Conditions Deep standby Stop mode (When RAM is off) Deep standby Stop mode (When RAM is on) Frequency - - Value Typ* 1 Max* 2 Unit μa μa μa μa μa μa Remarks *3, *4 TA = +25 C *3, *4 TA = +85 C *3, *4 TA = +105 C *3, *4 TA = +25 C *3, *4 TA = +85 C *3, *4 TA = +105 C Power supply current ICCRD VCC Deep Standby RTC mode (When RAM is off) Deep Standby RTC mode (When RAM is on) 32 khz μa μa μa μa μa μa *3, *4 TA = +25 C *3, *4 TA = +85 C *3, *4 TA = +105 C *3, *4 TA = +25 C *3, *4 TA = +85 C *3, *4 TA = +105 C μa *3, *4, *5 TA = +25 C RTC stop*6-1.4 μa *3, *4, *5 TA = +85 C ICCVBAT VBAT μa μa *3, *4, *5 TA = +105 C *3, *4 TA = +25 C RTC operation*6-3.2 μa *3, *4 TA = +85 C μa *3, *4 TA = +105 C *1: VCC = 3.3 V *2: VCC = 5.5 V *3: When all ports are fixed *4: When LVD is off *5: When sub oscillation is off *6: In the case of setting RTC after VCC power on Document Number: Rev.*B Page 109 of 201

110 Table Typical and Maximum Current Consumption in Low-voltage Detection Circuit, Main Flash Memory Write/erase Parameter Low-voltage detection circuit (LVD) power supply current MainFlash memory write/erase current Symbol ICCLVD ICCFLASH Pin Name VCC Conditions Value Min Typ Max Unit At operation μa At write/erase ma *1 Remarks For occurrence of interrupt *1: When programming or erase in flash memory, Flash Memory Write/Erase current (ICCFLASH) is added to the Power supply current (ICC). Peripheral Current Dissipation Clock system Peripheral HCLK Unit Frequency (MHz) GPIO All ports DMAC DSTC External bus I/F SD card I/F CAN 1 ch CAN-FD 1 ch USB 1 ch I 2 S High-Speed Quad SPI Programmable CRC Unit ma Remarks PCLK1 Base timer 4 ch Multi-functional timer/ppg Quadrature position/revolution counter 1 unit/4 ch unit A/D converter 1 unit PCLK2 Multi-function serial 1 ch ma ma Document Number: Rev.*B Page 110 of 201

111 Pin Characteristics (VCC = USBVCC0 = USBVCC1 = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V) Parameter Symbol Pin Name Conditions H level voltage (hysteresis ) L level voltage (hysteresis ) VIHS VILS CMOS hysteresis pin, MD0, MD1 MADATAxx 5 V tolerant pin Input pin doubled as I 2 C Fm+ TTL Schmitt pin CMOS hysteresis pin, MD0, MD1 5 V tolerant pin Input pin doubled as I 2 C Fm+ TTL Schmitt pin Value Min Typ Max Unit - VCC VCC V VCC > 3.0 V, VCC 3.6 V, VCC V - VCC VSS V - VCC VSS V VCC+0.3 V - VSS VCC 0.2 V VSS VCC 0.2 V - VSS VCC 0.2 V - VSS - VCC 0.3 V - VSS V VCC 4.5 V, IOH = - 4 ma Remarks At External Bus 4 ma type VCC < 4.5 V, IOH = - 2 ma VCC VCC V 8 ma type VCC 4.5 V, IOH = - 8 ma VCC < 4.5 V, IOH = - 4 ma VCC VCC V H level output voltage VOH 10 ma type 12 ma type VCC 4.5 V, IOH = - 10 ma VCC < 4.5 V, IOH = - 8 ma VCC 4.5 V, IOH = - 12 ma VCC < 4.5 V, IOH = - 8 ma VCC VCC V VCC VCC V The pin doubled as USB I/O USBVCC 4.5 V, IOH = ma USBVCC < 4.5 V, IOH = ma USBVCC USBVCC V *1 The pin doubled as I 2 C Fm+ VCC 4.5 V, IOH = - 4 ma VCC < 4.5 V, IOH = - 3 ma VCC VCC V At GPIO Document Number: Rev.*B Page 111 of 201

112 Parameter Symbol Pin Name Conditions 4 ma type VCC 4.5 V, IOL = 4 ma VCC < 4.5 V, IOL = 2 ma Value Unit Min Typ Max VSS V Remarks 8 ma type VCC 4.5 V, IOL = 8 ma VCC < 4.5 V, IOL = 4 ma VSS V L level output voltage Input leak current Pull-up resistor value Input capacitance VOL 10 ma type 12 ma type The pin doubled as USB I/O The pin doubled as I 2 C Fm+ VCC 4.5 V, IOL = 10 ma VCC < 4.5 V, IOL = 8 ma VCC 4.5 V, IOL = 12 ma VCC < 4.5 V, IOL = 8 ma USBVCC 4.5 V, IOL = 18.5 ma USBVCC < 4.5 V, IOL = 10.5 ma VCC 4.5 V, IOL = 4 ma VCC < 4.5 V, IOL = 3 ma VCC 4.5 V, IOL = 20 ma VSS V VSS V VSS V *1 VSS V IIL μa RPU CIN Pull-up pin Other than VCC, USBVCC0, USBVCC1, VBAT, VSS, AVCC, AVSS, AVRH *1: USBVcc0 and USBVcc1 are described as USBVcc. VCC 4.5 V VCC < 4.5 V pf kω At GPIO At I 2 C Fm+ Document Number: Rev.*B Page 112 of 201

113 12.4 AC Characteristics Main Clock Input Characteristics (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = -40 C to +105 C) Parameter Input frequency Input clock cycle Symbol fch tcylh Input clock pulse width - Input clock rise time and fall time Internal operating clock *1 frequency Internal operating clock *1 cycle time tcf, tcr Pin Name X0, X1 Conditions Min Value Max VCC 4.5 V 4 48 VCC < 4.5 V 4 20 VCC 4.5 V 4 48 VCC < 4.5 V 4 20 VCC 4.5 V VCC < 4.5 V PWH/tCYLH, PWL/tCYLH Unit MHz MHz ns Remarks When crystal oscillator is connected When using external clock When using external clock % When using external clock ns When using external clock fcc MHz Base clock (HCLK/FCLK) fcp MHz APB0bus clock *2 fcp MHz APB1bus clock *2 fcp MHz APB2bus clock *2 tcycc ns Base clock (HCLK/FCLK) tcycp ns APB0bus clock *2 tcycp ns APB1bus clock *2 tcycp ns APB2bus clock *2 *1: For more information about each internal operating clock, see Chapter 2-1: Clock in FM4 Family Peripheral Manual Main Part ( ). *2: For more about each APB bus to which each peripheral is connected, see 8. Block Diagram in this data sheet. X0 Document Number: Rev.*B Page 113 of 201

114 Sub Clock Input Characteristics (VBAT = 1.65V to 5.5V, VSS = 0V) Parameter Input frequency Symbol 1/tCYLL Pin Name Conditions Value Min Typ Max X0A, X1A khz Input clock cycle tcyll μs Input clock pulse width - Unit khz PWH/tCYLL, PWL/tCYLL % *: For more information about crystal oscillator, see Sub crystal oscillator in 7. Handling Devices. Remarks When crystal oscillator is connected * When using external clock When using external clock When using external clock t CYLL 0.8 VBAT 0.8 VBAT 0.8 VBAT X0A 0.2 VBAT 0.2 VBAT P WH P WL Built-In CR Oscillation Characteristics Built-In High-speed CR Parameter Symbol Conditions Value Min Typ Max (VCC = 2.7V to 5.5V, VSS = 0V) Unit Remarks Clock frequency Frequency stabilization time fcrh TJ = - 20 C to C TJ = - 40 C to C TJ = - 40 C to C MHz tcrwt μs *2 When trimming *1 When not trimming *1: In the case of using the values in CR trimming area of flash memory at shipment for frequency/temperature trimming *2: This is the time to stabilize the frequency of the High-speed CR clock after setting trimming value. During this period, it is able to use the High-speed CR clock as a source clock. Built-In Low-speed CR (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Condition Value Min Typ Max Unit Remarks Clock frequency fcrl khz Document Number: Rev.*B Page 114 of 201

115 Operating Conditions of Main PLL (in the Case of Using Main Clock for Input Clock of PLL) Parameter Symbol Value Min Typ Max PLL oscillation stabilization wait time* 1 (lock up time) tlock μs PLL clock frequency fplli 4-16 MHz PLL multiplication rate multiplier PLL macro oscillation clock frequency fpllo MHz Main PLL clock frequency* 2 fclkpll MHz *1: Time from when the PLL starts operating until the oscillation stabilizes (VCC = 2.7V to 5.5V, VSS = 0V) Unit Remarks *2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM4 Family Peripheral Manual Main Part ( ) Operating Conditions of USB PLL I 2 S PLL (in the Case of Using Main Clock for Input Clock of PLL) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Value Min Typ Max Unit Remarks PLL oscillation stabilization wait time *1 (lock up time) tlock μs PLL clock frequency fplli 4-16 MHz PLL multiplication rate multiplier PLL macro oscillation clock frequency fpllo MHz USB 384 MHz I 2 S USB clock frequency *2 fclkpll MHz After the M frequency division I 2 S clock frequency *3 fclkpll MHz After the M frequency division *1: Time from when the PLL starts operating until the oscillation stabilizes *2: For more information about USB/Ethernet clock, see Chapter 2-2: USB/Ethernet Clock Generation in FM4 Family Peripheral Manual Communication Macro Part ( ). *3: For more information about I 2 S clock, see Chapter 7-1: I 2 S Clock Generation in FM4 Family Peripheral Manual Communication Macro Part ( ). Document Number: Rev.*B Page 115 of 201

116 Operating Conditions of Main PLL (in the Case of Using Built-in High-speed CR Clock for Input Clock of Main PLL) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter PLL oscillation stabilization wait time *1 (lock up time) Symbol Value Min Typ Max Unit tlock μs PLL clock frequency fplli MHz PLL multiplication rate multiplier PLL macro oscillation clock frequency fpllo MHz Main PLL clock frequency *2 fclkpll MHz *1: Time from when the PLL starts operating until the oscillation stabilizes Remarks *2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM4 Family Peripheral Manual Main Part ( ). Note: The High-speed CR clock (CLKHC) should be set with frequency/temperature trimming to act as the source clock of the Main PLL Reset Input Characteristics (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Reset time tinitx INITX ns Min Typ Unit Remarks Document Number: Rev.*B Page 116 of 201

117 Power-On Reset Timing (VSS = 0V) Parameter Power supply shut down time Symbol toff Pin Name VCC Conditions Value Min Typ Max Unit ms *1 Power ramp rate dv/dt VCC: 0.2V to 2.70V mv/µs *2 Time until releasing Power-on reset tprt ms Remarks *1: VCC must be held below 0.2V for a minimum period of toff. Improper initialization may occur if this condition is not met. *2: This dv/dt characteristic is applied at the power-on of cold start (toff>1ms). Note: If toff cannot be satisfied designs must assert external reset(initx) at power-up and at any brownout event per V V CC V DH 0.2V dv/dt 0.2V 0.2V tprt toff Internal RST CPU Operation RST Active release start Glossary VDH: detection voltage of Low Voltage detection reset. See Low-Voltage Detection Characteristics GPIO Output Characteristics (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Output frequency tpcycle Pxx* *: GPIO is a target. Conditions Value Min Typ Unit VCC 4.5 V - 50 MHz VCC < 4.5 V - 32 MHz Remarks Pxx t PCYCLE Document Number: Rev.*B Page 117 of 201

118 External Bus Timing External Bus Clock Output Characteristics Parameter Symbol Pin Name Conditions Min Value Typ Unit Remarks Output frequency tcycle MCLKOUT *1-50 *2 MHz *1: The external bus clock (MCLKOUT) is a divided clock of HCLK. For more information about setting of clock divider, see Chapter 14: External Bus Interface in FM4 Family Peripheral Manual Main Part ( ). *2: Generate MCLKOUT at setting more than four divisions when the AHB bus clock exceeds 100 MHz. 0.8 Vcc 0.8 Vcc MCLK t CYCLE External Bus Signal I/O characteristics (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions Value Unit Remarks Signal characteristics Signal output characteristics VIH 0.8 VCC V VIL 0.2 VCC V - VOH 0.8 VCC V VOL 0.2 VCC V Input signal VIH VIL VIH VIL VOH VOL VOH VOL Document Number: Rev.*B Page 118 of 201

119 Separate Bus Access Asynchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions MOEX Minimum pulse width MCSX Address output delay time MOEX Address hold time MCSX MOEX delay time MOEX MCSX time MCSX MDQM delay time Data set up MOEX time MOEX Data hold time MWEX Minimum pulse width MWEX Address output delay time MCSX MWEX delay time MWEX MCSX delay time MCSX MDQM delay time MCSX Data output time MWEX Data hold time Min Value Max toew MOEX - MCLK n-3 - ns tcsl AV toeh - AX MCSX[7: 0], MAD[24: 0] MOEX, MAD[24: 0] Unit ns - 0 MCLK m+9 ns tcsl - OEL MOEX, - MCLK m-9 MCLK m+9 ns toeh - CSH MCSX[7: 0] - 0 MCLK m+9 ns tcsl - RDQML tds - OE tdh - OE MCSX, MDQM[3: 0] MOEX, MADATA[31: 0] MOEX, MADATA[31: 0] - MCLK m-9 MCLK m+9 ns ns ns twew MWEX - MCLK n-3 - ns tweh - AX MWEX, MAD[24: 0] - 0 MCLK m+9 ns tcsl - WEL MWEX, - MCLK n-9 MCLK n+9 ns tweh - CSH MCSX[7: 0] - 0 MCLK m+9 ns tcsl-wdqml tcsl-dx tweh - DX MCSX, MDQM[3: 0] MCSX, MADATA[31: 0] MWEX, MADATA[31: 0] - MCLK n-9 MCLK n+9 ns - MCLK-9 MCLK+9 ns - 0 MCLK m+9 ns Remarks Note: When the external load capacitance CL = 30 pf (m = 0 to 15, n = 1 to 16) Document Number: Rev.*B Page 119 of 201

120 t CYCLE MCLK MCSX[7: 0] t OEH-CSH t WEH-CSH MAD[24: 0] t CSL-AV t OEH-AX Address t CSL-AV Address t WEH-AX MOEX MDQM[1: 0] t CSL-OEL tcsl-rdqml t OEW t CSL-WDQML t CSL-WEL MWEX t WEW MADATA[15: 0] t DS-OE RD t DH-OE Invalid WD t WEH-DX t CSL-DX Document Number: Rev.*B Page 120 of 201

121 Separate Bus Access Synchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Address delay time MCSX delay time tav MCLK, MAD[24: 0] Condition s Min Value Max Unit ns tcsl MCLK, ns tcsh MCSX[7: 0] ns Remark s MOEX delay time Data set up MCLK time MCLK Data hold time MWEX delay time MDQM[1: 0] delay time MCLK Data output time MCLK Data hold time trel MCLK, ns treh MOEX ns tds MCLK, MADATA[31: 0] ns MCLK, tdh MADATA[31: ns 0] twel MCLK, ns tweh MWEX ns tdqml MCLK, ns tdqmh MDQM[3: 0] ns tods tod MCLK, MADATA[31: 0] MCLK, MADATA[31: 0] - MCLK+1 MCLK+18 ns ns Note: When the external load capacitance CL = 30 pf t CYCLE MCLK t CSL t CSH MCSX[7: 0] MAD[24: 0] t AV Address t AV Address MOEX t REL t REH MDQM[3: 0] t DQML t DQMH t DQML t DQMH t WEL t WEH MWEX MADATA[31: 0] t DS RD t DH Invalid WD t OD t ODS Document Number: Rev.*B Page 121 of 201

122 Multiplexed Bus Access Asynchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Multiplexed address delay time Multiplexed address hold time tale-chmadv Min Value Max MALE, ns tchmadh MAD[24: 0] - MCLK n+0 MCLK n+10 ns Unit Remarks Note: When the external load capacitance CL = 30 pf (m = 0 to 15, n = 1 to 16) MCLK MCSX[7: 0] MALE MAD [24: 0] MOEX MDQM [3: 0] MWEX MADATA[31: 0] Document Number: Rev.*B Page 122 of 201

123 Multiplexed Bus Access Synchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions MALE delay time MCLK Multiplexed address delay time MCLK Multiplexed data output time Min Value tchal MCLK, tchah MALE Max tchmadv MCLK, - 1 tod ns MADATA[31: tchmadx 0] - 1 tod ns Unit Remarks Note: When the external load capacitance CL = 30 pf MCLK MCSX[7: 0] MALE MAD [24: 0] MOEX MDQM [3: 0] MWEX MADATA[31: 0] Document Number: Rev.*B Page 123 of 201

124 NAND Flash Mode (VCC = 2.7V to 5.5V, VSS = 0V) Value Parameter Symbol Pin Name Conditions Unit Min Max MNREX Min pulse width tnrew MNREX - MCLK n-3 - ns Data set up MNREX time MNREX Data hold time MNALE MNWEX delay time MNALE MNWEX delay time MNCLE MNWEX delay time MNWEX MNCLE delay time MNWEX Min pulse width MNWEX Data output time MNWEX Data hold time tds NRE tdh NRE taleh - NWEL talel - NWEL tcleh - NWEL tnweh - CLEL MNREX, MADATA[31: 0] MNREX, MADATA[31: 0] MNALE, MNWEX MNALE, MNWEX MNCLE, MNWEX MNCLE, MNWEX ns ns - MCLK m-9 MCLK m+9 ns - MCLK m-9 MCLK m+9 ns - MCLK m-9 MCLK m+9 ns - 0 MCLK m+9 ns tnwew MNWEX - MCLK n-3 - ns tnwel DV tnweh DX MNWEX, MADATA[31: 0] MNWEX, MADATA[31: 0] ns - 0 MCLK m+9 ns Remarks Note: When the external load capacitance CL = 30 pf (m = 0 to 15, n = 1 to 16) NAND Flash Read MCLK MNREX MADATA[31: 0] Read Document Number: Rev.*B Page 124 of 201

125 NAND Flash Address Write MCLK MNALE MNCLE MNWEX MADATA[31: 0] Write NAND Flash Command Write MCLK MNALE MNCLE MNWEX MADATA[31: 0] Write Document Number: Rev.*B Page 125 of 201

126 External Ready Input Timing (VCC = 2.7V to 5.5V, VSS = 0V) MCLK MRDY setup time Parameter Symbol Pin Name Conditions trdyi MCLK, MRDY Min Value Max Unit ns Remarks When RDY is MCLK Original MOEX MWEX Over 2cycle t RDYI MRDY When RDY is released MCLK 2 cycles Extended MOEX MWEX trdyi MRDY 0.5 V CC Document Number: Rev.*B Page 126 of 201

127 SDRAM Mode (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Name Value Min Unit Max Unit Remarks Output frequency tcycsd MSDCLK MHz Address delay time MSDCLK Data output delay time MSDCLK Data output Hi-Z time MDQM[3: 0] delay time MCSX delay time taosd tdosd tdozsd twrosd tmcssd MSDCLK, MAD[15: 0] MSDCLK, MADATA[31: 0] MSDCLK, MADATA[31: 0] MSDCLK, MDQM[1: 0] MSDCLK, MCSX ns ns ns ns ns MRASX delay time MCASX delay time MSDWEX delay time MSDCKE delay time Data set up time Data hold time trassd tcassd tmwesd tckesd tdssd tdhsd MSDCLK, MRASX MSDCLK, MCASX MSDCLK, MSDWEX MSDCLK, MSDCKE MSDCLK, MADATA[31: 0] MSDCLK, MADATA[31: 0] ns ns ns ns ns ns Note: When the external load capacitance CL = 30 pf Document Number: Rev.*B Page 127 of 201

128 SDRAM Access t CYCSD MSDCLK MAD[24:0] t AOSD Address MDQM[1:0] t WROSD MCSX t MCSSD MRASX t RASSD MCASX t CASSD MSDWEX t MWESD MSDCKE t CKESD MADATA[15:0] t DSSD RD t DHSD MADATA[15:0] t DOSD WD t DOZSD Document Number: Rev.*B Page 128 of 201

129 Base Timer Input Timing Timer Input Timing Parameter Symbol Pin Name Conditions Input pulse width ttiwh, ttiwl TIOAn/TIOBn (when using as ECK, TIN) Value Min Max (VCC = 2.7V to 5.5V, VSS = 0V) Unit - 2tCYCP - ns Remarks ECK t TIWH t TIWL TIN V IHS V IHS V ILS V ILS Trigger Input Timing Parameter Symbol Pin Name Conditions Input pulse width ttrgh, ttrgl TIOAn/TIOBn (when using as TGIN) Value Min Max (VCC = 2.7V to 5.5V, VSS = 0V) Unit - 2tCYCP - ns Remarks t TRGH t TRGL TGIN V IHS V IHS V ILS V ILS Note: tcycp indicates the APB bus clock cycle time. For more information about the APB bus number to which the base timer is connected, see 8. Block Diagram in this data sheet. Document Number: Rev.*B Page 129 of 201

130 CSIO (SPI) Timing Synchronous serial (SPI = 0, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions VCC < 4.5 V VCC 4.5 V Min Max Min Max Baud rate Mbps Serial clock cycle time tscyc SCKx 4tCYCP - 4tCYCP - ns SCK SOT delay time tslovi SCKx, SOTx Internal shift ns SIN SCK SCKx, clock tivshi setup time SINx operation ns SCK SIN hold time tshixi SCKx, SINx ns Serial clock L pulse width tslsh SCKx 2tCYCP tCYCP ns Serial clock H pulse width tshsl SCKx tcycp tcycp ns SCKx, SCK SOT delay time tslove ns SOTx External shift SIN SCK SCKx, tivshe clock ns setup time SINx operation SCKx, SCK SIN hold time tshixe ns SINx SCK fall time tf SCKx ns SCK rise time tr SCKx ns Unit Notes: The above characteristics apply to CLK synchronous mode. tcycp indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. These characteristics only guarantee the same relocate port number; for example, the combination of SCKx_0 and SOTx_1 is not guaranteed. When the external load capacitance CL = 30 pf. Document Number: Rev.*B Page 130 of 201

131 tscyc SCK VOL VOH VOL t SLOVI SOT VOH VOL SIN VIH VIL tivshi tshixi VIH VIL MS bit = 0 tslsh tshsl SCK VIH tf VIL t SLOVE VIL VIH tr VIH SOT VOH VOL SIN tivshe VIH VIL MS bit = 1 tshixe VIH VIL Document Number: Rev.*B Page 131 of 201

132 Synchronous Serial (SPI = 0, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin VCC < 4.5 V VCC 4.5 V Conditions Name Min Max Min Max Unit Baud rate Mbps Serial clock cycle time tscyc SCKx 4tCYCP - 4tCYCP - ns SCK SOT delay time tshovi SCKx, SOTx SIN SCK setup time tivsli SCKx, SINx SCK SIN hold time tslixi SCKx, SINx Serial clock L pulse width tslsh SCKx Internal shift clock operation ns ns ns 2tCYCP tCYCP ns Serial clock H pulse width tshsl SCKx tcycp tcycp ns SCK SOT delay time SIN SCK setup time tshove tivsle SCKx, SOTx External shift SCKx, clock SINx operation ns ns SCK SIN hold time tslixe SCKx, SINx ns SCK fall time tf SCKx ns SCK rise time tr SCKx ns Notes: The above characteristics apply to CLK synchronous mode. tcycp indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. These characteristics only guarantee the same relocate port number; for example, the combination of SCKx_0 and SOTx_1 is not guaranteed. When the external load capacitance CL = 30 pf. Document Number: Rev.*B Page 132 of 201

133 tscyc SCK VOH VOH VOL t SHOVI SOT VOH VOL SIN VIH VIL tivsli tslixi VIH VIL MS bit = 0 tshsl tslsh SCK VIH VIH tr VIL t SHOVE tf VIL VIL SOT VOH VOL tivsle tslixe SIN VIH VIH VIL VIL MS bit = 1 Document Number: Rev.*B Page 133 of 201

134 Synchronous Serial (SPI = 1, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin VCC < 4.5 V VCC 4.5 V Conditions Name Min Max Min Max Unit Baud rate Mbps Serial clock cycle time tscyc SCKx 4tCYCP - 4tCYCP - ns SCK SOT delay time SIN SCK setup time SCK SIN hold time SOT SCK delay time tshovi tivsli tslixi tsovli SCKx, SOTx SCKx, SINx SCKx, SINx SCKx, SOTx Internal shift clock operation ns ns ns 2tCYCP tCYCP ns Serial clock L pulse width tslsh SCKx 2tCYCP tCYCP ns Serial clock H pulse width tshsl SCKx tcycp tcycp ns SCKx, SCK SOT delay time tshove ns SOTx External shift SIN SCK SCKx, tivsle clock ns setup time SINx operation SCKx, SCK SIN hold time tslixe ns SINx SCK fall time tf SCKx ns SCK rise time tr SCKx ns Notes: The above characteristics apply to CLK synchronous mode. tcycp indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. These characteristics only guarantee the same relocate port number; for example, the combination of SCKx_0 and SOTx_1 is not guaranteed. When the external load capacitance CL = 30 pf. Document Number: Rev.*B Page 134 of 201

135 tscyc SCK tsovli VOL VOH tshovi VOL SOT VOH VOL VOH VOL tivsli tslixi SIN VIH VIL VIH VIL MS bit = 0 tslsh tshsl SCK VIH VIH VIH VIL VIL SOT * VOH VOL tf tr tshove VOH VOL tivsle tslixe SIN VIH VIL VIH VIL * Changes when writing to TDR register MS bit = 1 Document Number: Rev.*B Page 135 of 201

136 Synchronous Serial (SPI = 1, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin VCC < 4.5 V VCC 4.5 V Conditions Name Min Max Min Max Unit Baud rate Mbps Serial clock cycle time tscyc SCKx 4tCYCP - 4tCYCP - ns SCK SOT delay time tslovi SCKx, SOTx ns SIN SCK setup time tivshi SCKx, Internal shift SINx clock ns SCK SIN hold time tshixi SCKx, operation SINx ns SOT SCK delay time tsovhi SCKx, SOTx 2tCYCP tCYCP ns Serial clock L pulse width tslsh SCKx 2tCYCP tCYCP ns Serial clock H pulse width tshsl SCKx tcycp tcycp ns SCKx, SCK SOT delay time tslove ns SOTx External shift SCKx, SIN SCK setup time tivshe clock ns SINx operation SCKx, SCK SIN hold time tshixe ns SINx SCK fall time tf SCKx ns SCK rise time tr SCKx ns Notes: The above characteristics apply to CLK synchronous mode. tcycp indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. These characteristics only guarantee the same relocate port number; for example, the combination of SCKx_0 and SOTx_1 is not guaranteed. When the external load capacitance CL = 30 pf. Document Number: Rev.*B Page 136 of 201

137 tscyc SCK VOH VOL VOH tsovhi tslovi SOT VOH VOL VOH VOL tivshi tshixi SIN VIH VIL VIH VIL MS bit = 0 tr tshsl tslsh tf SCK VIL VIH VIH VIL VIL VIH tslove SOT VOH VOH VOL VOL tivshe tshixe SIN VIH VIL VIH VIL MS bit = 1 Document Number: Rev.*B Page 137 of 201

138 When Using Synchronous Serial Chip Select (SCINV = 0, CSLVL = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions VCC < 4.5 V VCC 4.5 V Min Max Min Max SCS SCK setup time tcssi (*1)-50 (*1)+0 (*1)-50 (*1)+0 ns Internal shift SCK SCS hold time tcshi clock ( *2)+0 ( *2)+50 ( *2)+0 ( *2)+50 ns SCS deselect time operation (*3)-50 (*3)+50 (*3)-50 (*3)+50 tcsdi ns SCS SCK setup time tcsse +5tCYCP +5tCYCP +5tCYCP +5tCYCP SCK SCS hold time tcshe External shift ns SCS deselect time tcsde clock 3tCYCP+30-3tCYCP+30 - ns SCS SOT delay time tdse operation ns Unit 3tCYCP+30-3tCYCP+30 - ns SCS SOT delay time tdee ns (*1): CSSU bit value serial chip select timing operating clock cycle [ns] (*2): CSHD bit value serial chip select timing operating clock cycle [ns] (*3): CSDS bit value serial chip select timing operating clock cycle [ns] Notes: tcycp indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family Peripheral Manual Main Part ( ). When the external load capacitance CL = 30 pf. Document Number: Rev.*B Page 138 of 201

139 SCS output tcssi tcshi tcsdi SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 SCS tcsse tcshe tcsde SCK tdee SOT (SPI=0) tdse SOT (SPI=1) MS bit = 1 Document Number: Rev.*B Page 139 of 201

140 When Using Synchronous Serial Chip Select (SCINV = 1, CSLVL = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions VCC < 4.5 V VCC 4.5 V Min Max Min Max SCS SCK setup time tcssi (*1)-50 (*1)+0 (*1)-50 (*1)+0 ns Internal shift SCK SCS hold time tcshi clock ( *2)+0 ( *2)+50 ( *2)+0 ( *2)+50 ns SCS deselect time operation (*3)-50 (*3)+50 (*3)-50 (*3)+50 tcsdi ns SCS SCK setup time tcsse +5tCYCP +5tCYCP +5tCYCP +5tCYCP SCK SCS hold time tcshe External shift ns SCS deselect time tcsde clock 3tCYCP+30-3tCYCP+30 - ns SCS SOT delay time tdse operation ns Unit 3tCYCP+30-3tCYCP+30 - ns SCS SOT delay time tdee ns (*1): CSSU bit value serial chip select timing operating clock cycle [ns] (*2): CSHD bit value serial chip select timing operating clock cycle [ns] (*3): CSDS bit value serial chip select timing operating clock cycle [ns] Notes: tcycp indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family Peripheral Manual Main Part ( ). When the external load capacitance CL = 30 pf. Document Number: Rev.*B Page 140 of 201

141 SCS output tcssi tcshi tcsdi SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 SCS tcsse tcshe tcsde SCK tdee SOT (SPI=0) tdse SOT (SPI=1) MS bit = 1 Document Number: Rev.*B Page 141 of 201

142 When Using Synchronous Serial Chip Select (SCINV = 0, CSLVL = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions VCC < 4.5 V VCC 4.5 V Min Max Min Max SCS SCK setup time tcssi (*1)-50 (*1)+0 (*1)-50 (*1)+0 ns Internal shift SCK SCS hold time tcshi clock ( *2)+0 ( *2)+50 ( *2)+0 ( *2)+50 ns SCS deselect time operation (*3)-50 (*3)+50 (*3)-50 (*3)+50 tcsdi ns SCS SCK setup time tcsse +5tCYCP +5tCYCP +5tCYCP +5tCYCP SCK SCS hold time tcshe External ns SCS deselect time tcsde shift clock 3tCYCP+30-3tCYCP+30 - ns SCS SOT delay time tdse operation ns Unit 3tCYCP+30-3tCYCP+30 - ns SCS SOT delay time tdee ns (*1): CSSU bit value serial chip select timing operating clock cycle [ns] (*2): CSHD bit value serial chip select timing operating clock cycle [ns] (*3): CSDS bit value serial chip select timing operating clock cycle [ns] Notes: tcycp indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family Peripheral Manual Main Part ( ). When the external load capacitance CL = 30 pf. Document Number: Rev.*B Page 142 of 201

143 tcsdi SCS output tcssi tcshi SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 tcsde SCS tcsse tcshe SCK tdee SOT (SPI=0) tdse SOT (SPI=1) MS bit = 1 Document Number: Rev.*B Page 143 of 201

144 When Using Synchronous Serial Chip Select (SCINV = 1, CSLVL = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions VCC < 4.5 V VCC 4.5 V Min Max Min Max SCS SCK setup time tcssi (*1)-50 (*1)+0 (*1)-50 (*1)+0 ns Internal shift SCK SCS hold time tcshi clock ( *2)+0 ( *2)+50 ( *2)+0 ( *2)+50 ns SCS deselect time operation (*3)-50 (*3)+50 (*3)-50 (*3)+50 ns SCS SCK setup time tcsdi tcsse +5tCYCP +5tCYCP +5tCYCP +5tCYCP SCK SCS hold time tcshe External ns SCS deselect time tcsde shift clock 3tCYCP+30-3tCYCP+30 - ns SCS SOT delay time tdse operation ns Units 3tCYCP+30-3tCYCP+30 - ns SCS SOT delay time tdee ns (*1): CSSU bit value serial chip select timing operating clock cycle [ns] (*2): CSHD bit value serial chip select timing operating clock cycle [ns] (*3): CSDS bit value serial chip select timing operating clock cycle [ns] Notes: tcycp indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family Peripheral Manual Main Part ( ). When the external load capacitance CL = 30 pf. Document Number: Rev.*B Page 144 of 201

145 tcsdi SCS output tcssi tcshi SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 SCS tcsse tcshe tcsde SCK tdee SOT (SPI=0) tdse SOT (SPI=1) MS bit = 1 Document Number: Rev.*B Page 145 of 201

146 High-Speed Synchronous Serial (SPI = 0, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin VCC < 4.5 V VCC 4.5 V Conditions Name Min Max Min Max Unit Serial clock cycle time tscyc SCKx 4tCYCP - 4tCYCP - ns SCK SOT delay time tslovi SCKx, SOTx Internal shift ns SIN SCK setup time tivshi SCKx, clock 14 SINx operation 12.5* ns SCK SIN hold time tshixi SCKx, SINx ns Serial clock L pulse width tslsh SCKx 2tCYCP - 5-2tCYCP ns Serial clock H pulse width tshsl SCKx tcycp tcycp ns SCKx, SCK SOT delay time tslove ns SOTx External shift SCKx, SIN SCK setup time tivshe clock ns SINx operation SCKx, SCK SIN hold time tshixe ns SINx SCK fall time tf SCKx ns SCK rise time tr SCKx ns Notes: The above characteristics apply to CLK synchronous mode. tcycp indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. These characteristics only guarantee the following pins: No chip select: SIN4_0, SOT4_0, SCK4_0 Chip select: SIN6_0, SOT6_0, SCK6_0, SCS60_0, SCS61_0, SCS62_0, SCS63_0 When the external load capacitance CL = 30 pf. (For *, when CL = 10 pf) Document Number: Rev.*B Page 146 of 201

147 tscyc SCK VOL VOH VOL t SLOVI SOT VOH VOL SIN VIH VIL tivshi tshixi VIH VIL MS bit = 0 tslsh tshsl SCK VIH tf VIL t SLOVE VIL VIH tr VIH SOT VOH VOL SIN tivshe VIH VIL MS bit = 1 tshixe VIH VIL Document Number: Rev.*B Page 147 of 201

148 High-Speed Synchronous Serial (SPI = 0, SCINV = 1) Parameter Symbol Pin Name Serial clock cycle time tscyc SCKx SCK SOT delay time tshovi SCKx, SOTx Conditions Internal shift clock operation (VCC = 2.7V to 5.5V, VSS = 0V) VCC < 4.5 V VCC 4.5 V Unit Min Max Min Max 4tCYCP - 4tCYCP - ns ns SIN SCK setup time tivsli SCKx, 14 SINx 12.5* ns SCK SIN hold time tslixi SCKx, SINx ns Serial clock L pulse width tslsh SCKx 2tCYCP - 5-2tCYCP ns Serial clock H pulse width tshsl SCKx tcycp tcycp ns SCKx, SCK SOT delay time tshove ns SOTx External shift SCKx, SIN SCK setup time tivsle clock ns SINx operation SCKx, SCK SIN hold time tslixe ns SINx SCK fall time tf SCKx ns SCK rise time tr SCKx ns Notes: The above characteristics apply to CLK synchronous mode. tcycp indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. These characteristics only guarantee the following pins: No chip select: SIN4_0, SOT4_0, SCK4_0 Chip select: SIN6_0, SOT6_0, SCK6_0, SCS60_0, SCS61_0, SCS62_0, SCS63_0 When the external load capacitance CL = 30 pf. (For *, when CL = 10 pf) Document Number: Rev.*B Page 148 of 201

149 tscyc SCK VOH VOH VOL t SHOVI SOT VOH VOL SIN VIH VIL tivsli tslixi VIH VIL MS bit = 0 tshsl tslsh SCK tr VIL VIH t SHOVE tf VIH VIL VIL SOT VOH VOL tivsle tslixe SIN VIH VIH VIL VIL MS bit = 1 Document Number: Rev.*B Page 149 of 201

150 High-Speed Synchronous Serial (SPI = 1, SCINV = 0) Parameter Symbol Pin Name Serial clock cycle time tscyc SCKx SCK SOT delay time tshovi SCKx, SOTx Conditions (VCC = 2.7V to 5.5V, VSS = 0V) VCC < 4.5 V VCC 4.5 V Unit Min Max Min Max 4tCYCP - 4tCYCP - ns ns SCKx, Internal shift 14 SIN SCK setup time tivsli SINx clock ns 12.5* operation SCKx, SCK SIN hold time tslixi ns SINx SOT SCK delay time tsovli SCKx, SOTx 2tCYCP tCYCP ns Serial clock L pulse width tslsh SCKx 2tCYCP - 5-2tCYCP ns Serial clock H pulse width tshsl SCKx tcycp tcycp ns SCKx, SCK SOT delay time tshove ns SOTx External shift SCKx, SIN SCK setup time tivsle clock ns SINx operation SCKx, SCK SIN hold time tslixe ns SINx SCK fall time tf SCKx ns SCK rise time tr SCKx ns Notes: The above characteristics apply to CLK synchronous mode. tcycp indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. These characteristics only guarantee the following pins: No chip select: SIN4_0, SOT4_0, SCK4_0 Chip select: SIN6_0, SOT6_0, SCK6_0, SCS60_0, SCS61_0, SCS62_0, SCS63_0 When the external load capacitance CL = 30 pf. (for *, when CL = 10 pf) Document Number: Rev.*B Page 150 of 201

151 tscyc SCK tsovli VOL VOH tshovi VOL SOT VOH VOL VOH VOL tivsli tslixi SIN VIH VIL VIH VIL MS bit = 0 tslsh tshsl SCK VIH VIH VIH VIL VIL SOT * VOH VOL tf tr tshove VOH VOL tivsle tslixe SIN VIH VIL VIH VIL * Changes when writing to TDR register MS bit = 1 Document Number: Rev.*B Page 151 of 201

152 High-Speed Synchronous Serial (SPI = 1, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin VCC < 4.5 V VCC 4.5 V Conditions Name Min Max Min Max Unit Serial clock cycle time tscyc SCKx 4tCYCP - 4tCYCP - ns SCK SOT delay time tslovi SCKx, SOTx ns SCKx, Internal shift 14 SIN SCK setup time tivshi ns SINx clock 12.5* SCKx, operation SCK SIN hold time tshixi ns SINx SOT SCK delay time tsovhi SCKx, SOTx 2tCYCP tCYCP ns Serial clock L pulse width tslsh SCKx 2tCYCP - 5-2tCYCP ns Serial clock H pulse width tshsl SCKx tcycp tcycp ns SCKx, SCK SOT delay time tslove ns SOTx External shift SCKx, SIN SCK setup time tivshe clock ns SINx operation SCKx, SCK SIN hold time tshixe ns SINx SCK fall time tf SCKx ns SCK rise time tr SCKx ns Notes: The above characteristics apply to CLK synchronous mode. tcycp indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. These characteristics only guarantee the following pins: No chip select: SIN4_0, SOT4_0, SCK4_0 Chip select: SIN6_0, SOT6_0, SCK6_0, SCS60_0, SCS61_0, SCS62_0, SCS63_0 When the external load capacitance CL = 30 pf. (for *, when CL = 10 pf) Document Number: Rev.*B Page 152 of 201

153 tscyc SCK VOH VOL VOH tsovhi tslovi SOT VOH VOL VOH VOL tivshi tshixi SIN VIH VIL VIH VIL MS bit = 0 SCK tr tshsl tslsh tf VIL VIH VIH VIL VIL VIH tslove SOT VOH VOL VOH VOL tivshe tshixe SIN VIH VIL VIH VIL MS bit = 1 Document Number: Rev.*B Page 153 of 201

154 When Using High-Speed Synchronous Serial Chip Select (SCINV = 0, CSLVL = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions VCC < 4.5 V VCC 4.5 V Min Max Min Max SCS SCK setup time tcssi (*1)-20 (*1)+0 (*1)-20 (*1)+0 ns Internal SCK SCS hold time tcshi shift clock ( *2)+0 ( *2)+20 ( *2)+0 ( *2)+20 ns SCS deselect time operation (*3)-20 (*3)+20 (*3)-20 (*3)+20 tcsdi ns SCS SCK setup time tcsse +5tCYCP +5tCYCP +5tCYCP +5tCYCP SCK SCS hold time tcshe External ns SCS deselect time tcsde shift clock 3tCYCP+15-3tCYCP+15 - ns SCS SOT delay time tdse operation ns Unit 3tCYCP+15-3tCYCP+15 - ns SCS SOT delay time tdee ns (*1): CSSU bit value serial chip select timing operating clock cycle [ns] (*2): CSHD bit value serial chip select timing operating clock cycle [ns] (*3): CSDS bit value serial chip select timing operating clock cycle [ns] Notes: tcycp indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family Peripheral Manual Main Part ( ). When the external load capacitance CL = 30 pf. Document Number: Rev.*B Page 154 of 201

155 SCS output tcssi tcshi tcsdi SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 SCS tcsde tcsse tcshe SCK tdee SOT (SPI=0) tdse SOT (SPI=1) MS bit = 1 Document Number: Rev.*B Page 155 of 201

156 When Using High-Speed Synchronous Serial Chip Select (SCINV = 1, CSLVL = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions VCC < 4.5 V VCC 4.5 V Min Min Min Max SCS SCK setup time tcssi (*1)-20 (*1)+0 (*1)-20 (*1)+0 ns Internal shift SCK SCS hold time tcshi clock ( *2)+0 ( *2)+20 ( *2)+0 ( *2)+20 ns SCS deselect time operation (*3)-20 (*3)+20 (*3)-20 (*3)+20 tcsdi ns SCS SCK setup time tcsse +5tCYCP +5tCYCP +5tCYCP +5tCYCP SCK SCS hold time tcshe External shift ns SCS deselect time tcsde clock 3tCYCP+15-3tCYCP+15 - ns SCS SOT delay time tdse operation ns Unit 3tCYCP+15-3tCYCP+15 - ns SCS SOT delay time tdee ns (*1): CSSU bit value serial chip select timing operating clock cycle [ns] (*2): CSHD bit value serial chip select timing operating clock cycle [ns] (*3): CSDS bit value serial chip select timing operating clock cycle [ns] Notes: tcycp indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family Peripheral Manual Main Part ( ). When the external load capacitance CL = 30 pf. Document Number: Rev.*B Page 156 of 201

157 SCS output tcsdi tcssi tcshi SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 SCS tcsde tcsse tcshe SCK tdee SOT (SPI=0) tdse SOT (SPI=1) MS bit = 1 Document Number: Rev.*B Page 157 of 201

158 When Using High-Speed Synchronous Serial Chip Select (SCINV = 0, CSLVL = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions VCC < 4.5 V VCC 4.5 V Min Max Min Max SCS SCK setup time tcssi (*1)-20 (*1)+0 (*1)-20 (*1)+0 ns Internal shift SCK SCS hold time tcshi clock ( *2)+0 ( *2)+20 ( *2)+0 ( *2)+20 ns SCS deselect time operation (*3)-20 (*3)+20 (*3)-20 (*3)+20 tcsdi ns SCS SCK setup time tcsse +5tCYCP +5tCYCP +5tCYCP +5tCYCP SCK SCS hold time tcshe External ns SCS deselect time tcsde shift clock 3tCYCP+15-3tCYCP+15 - ns SCS SOT delay time tdse operation ns Unit 3tCYCP+15-3tCYCP+15 - ns SCS SOT delay time tdee ns (*1): CSSU bit value serial chip select timing operating clock cycle [ns] (*2): CSHD bit value serial chip select timing operating clock cycle [ns] (*3): CSDS bit value serial chip select timing operating clock cycle [ns] Notes: tcycp indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family Peripheral Manual Main Part ( ). When the external load capacitance CL = 30 pf. Document Number: Rev.*B Page 158 of 201

159 SCS output tcsdi tcssi tcshi SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 tcsde SCS tcsse tcshe SCK tdee SOT (SPI=0) tdse SOT (SPI=1) MS bit = 1 Document Number: Rev.*B Page 159 of 201

160 When Using High-Speed Synchronous Serial Chip Select (SCINV = 1, CSLVL = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions VCC < 4.5 V VCC 4.5 V Min Max Min Max SCS SCK setup time tcssi (*1)-20 (*1)+0 (*1)-20 (*1)+0 ns Internal shift SCK SCS hold time tcshi clock ( *2)+0 ( *2)+20 ( *2)+0 ( *2)+20 ns SCS deselect time operation (*3)-20 (*3)+20 (*3)-20 (*3)+20 tcsdi ns SCS SCK setup time tcsse +5tCYCP +5tCYCP +5tCYCP +5tCYCP SCK SCS hold time tcshe External shift ns SCS deselect time tcsde clock 3tCYCP+15-3tCYCP+15 - ns SCS SOT delay time tdse operation ns Unit 3tCYCP+15-3tCYCP+15 - ns SCS SOT delay time tdee ns (*1): CSSU bit value serial chip select timing operating clock cycle [ns] (*2): CSHD bit value serial chip select timing operating clock cycle [ns] (*3): CSDS bit value serial chip select timing operating clock cycle [ns] Notes: tcycp indicates the APB bus clock cycle time. For more information about the APB bus number to which the multi-function serial is connected, see 8. Block Diagram in this data sheet. For more information about CSSU, CSHD, CSDS, and the serial chip select timing operating clock, see FM4 Family Peripheral Manual Main Part ( ). When the external load capacitance CL = 30 pf. Document Number: Rev.*B Page 160 of 201

161 SCS output tcsdi tcssi tcshi SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 SCS tcsse tcshe tcsde SCK tdee SOT (SPI=0) tdse SOT (SPI=1) MS bit = 1 Document Number: Rev.*B Page 161 of 201

162 External clock (EXT = 1): When in Asynchronous Mode Only Parameter Symbol Condition Min Value Max Unit Serial clock L pulse width tslsh tcycp ns Serial clock H pulse width tshsl tcycp ns CL = 30 pf SCK fall time tf - 5 ns SCK rise time tr - 5 ns (VCC = 2.7V to 5.5V, VSS = 0V) Remarks SCK tr tshsl tslsh V IH V IH V IH V IL V IL V IL tf Document Number: Rev.*B Page 162 of 201

163 External Input Timing Parameter Symbol Pin Name Conditions Input pulse width tinh, tinl ADTGx FRCKx INT00 to INT31, NMIX Value Min Max Unit - 2tCYCP *1 - ns - (VCC = 2.7V to 5.5V, VSS = 0V) Remarks A/D converter trigger Free-run timer clock ICxx Input capture DTTIxX - 2tCYCP *1 - ns Waveform generator 2tCYCP *1 - ns 500 *2 - ns External interrupt, NMI WKUPx *3 - ns Deep standby wake up *1: tcycp indicates the APB bus clock cycle time except stop when in Stop mode, in Timer mode. For more information about the APB bus number to which the A/D converter, multi-function timer, and external interrupt are connected, see 8. Block Diagram in this data sheet. *2: When in Stop mode, in Timer mode *3: When in Deep Standby RTC mode, in Deep Standby Stop mode Document Number: Rev.*B Page 163 of 201

164 Quadrature Position/Revolution Counter Timing (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = -40 C to +105 C) Parameter Symbol Conditions AIN pin H width tahl - AIN pin L width tall - BIN pin H width tbhl - BIN pin L width tbll - BIN rise time from PC_Mode2 or taubu AIN pin H level PC_Mode3 AIN fall time from PC_Mode2 or tbuad BIN pin H level PC_Mode3 BIN fall time from PC_Mode2 or tadbd AIN pin L level PC_Mode3 AIN rise time from PC_Mode2 or tbdau BIN pin L level PC_Mode3 AIN rise time from PC_Mode2 or tbuau BIN pin H level PC_Mode3 BIN fall time from PC_Mode2 or taubd AIN pin H level PC_Mode3 AIN fall time from PC_Mode2 or tbdad BIN pin L level PC_Mode3 BIN rise time from PC_Mode2 or tadbu AIN pin L level PC_Mode3 2tCYCP* - ns ZIN pin H width tzhl QCR: CGSC = 0 ZIN pin L width tzll QCR: CGSC = 0 AIN/BIN rise and fall time from determined ZIN level tzabe QCR: CGSC = 1 Determined ZIN level from AIN/BIN rise and fall time tabez QCR: CGSC = 1 *: tcycp indicates the APB bus clock cycle time except when in Stop mode, in Timer mode. For more information about the APB bus number to which the quadrature position/revolution counter is connected, see "8. Block Diagram" in this data sheet. Min Value Max Unit tahl tall AIN taubu tbuad tadbd tbdau BIN tbhl tbll Document Number: Rev.*B Page 164 of 201

165 tbhl tbll BIN tbuau taubd tbdad tadbu AIN tahl tall ZIN Document Number: Rev.*B Page 165 of 201

166 ZIN AIN/BIN Document Number: Rev.*B Page 166 of 201

167 I 2 C Timing Standard-mode, Fast-mode Parameter Symbol Conditions Standard-mode Fast-mode Min Max Min Max (VCC = 2.7V to 5.5V, VSS = 0V) SCL clock frequency fscl (Repeated) START condition hold time thdsta μs SDA SCL SCL clock L width tlow μs SCL clock H width thigh μs (Repeated) START condition setup time SCL SDA Data hold time SCL SDA Data setup time SDA SCL Stop condition setup time SCL SDA Bus free time between "Stop condition" and "START condition" tsusta μs CL = 30 pf, R = (Vp/IOL) *1 thddat * *3 μs Unit khz tsudat ns tsusto μs tbuf μs 2 MHz tcycp<40 MHz 2 tcycp *4-2 tcycp *4 - ns Remarks 40 MHz 4 tcycp tcycp <60 MHz *4-4 tcycp *4 - ns Noise filter tsp *5 60 MHz 6 tcycp tcycp <80 MHz *4-6 tcycp *4 - ns 80 MHz 8 tcycp tcycp 100 MHz *4-8 tcycp *4 - ns *1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current. *2: The maximum thddt must not extend beyond the low period (tlow) of the device s SCL signal. *3: Fast-mode I 2 C bus device can be used on a Standard-mode I 2 C bus system as long as the device satisfies the requirement of "tsudat 250 ns. *4: tcycp is the APB bus clock cycle time. For more information about the APB bus number to which the I 2 C is connected, see "8.Block Diagram" in this data sheet. When using Standard-mode, the peripheral bus clock must be set more than 2 MHz. When using Fast-mode, the peripheral bus clock must be set more than 8 MHz. *5: The noise filter time can be changed by register settings. Change the number of the noise filter steps according to the APB bus clock frequency. Document Number: Rev.*B Page 167 of 201

168 Fast Mode Plus (Fm+) Parameter Symbol Conditions Fast Mode Plus (Fm+)*6 Min Max (VCC = 2.7V to 5.5V, VSS = 0V) Unit Remarks SCL clock frequency fscl khz (Repeated) START condition hold time thdsta μs SDA SCL SCL clock L width tlow μs SCL clock H width thigh μs SCL clock frequency tsusta μs (Repeated) START condition CL = 30 pf, hold time thddat R = (Vp/IOL) *1 SDA SCL *2, *3 μs Data setup time SDA SCL tsudat 50 - ns Stop condition setup time SCL SDA tsusto μs Bus free time between "Stop condition" and "START condition" tbuf μs Noise filter tsp 60 MHz tcycp<80 MHz 6 tcycp *4 - ns 80 MHz tcycp 100 MHz 8 tcycp *4 - ns *5 *1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current. *2: The maximum thddt must not extend beyond the low period (tlow) of the device s SCL signal. *3: The Fast mode I 2 C bus device can be used on a Standard-mode I 2 C bus system as long as the device satisfies the requirement of "tsudat 250 ns. *4: tcycp is the APB bus clock cycle time. For more information about the APB bus number to which the I 2 C is connected, see "8.Block Diagram" in this data sheet. To use fast mode plus (Fm+), set the peripheral bus clock at 64 MHz or more. *5: The noise filter time can be changed by register settings. Change the number of the noise filter steps according to the APB bus clock frequency. *6: When using fast mode plus (Fm+), set the I/O pin to the mode corresponding to I 2 C Fm+ in the EPFR register. See Chapter12: I/O PORT in FM4 Family Peripheral Manual Main Part ( ) for the details. Document Number: Rev.*B Page 168 of 201

169 SD Card Interface Timing Default-Speed Mode Clock CLK (All values are referenced to VIH and VIL transition points) (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Name Conditions Min Value Max Remarks Clock frequency Data Transfer Mode fpp S_CLK 0 25 MHz Clock frequency fod S_CLK CCARD Identification Mode 10 0/ khz pf Clock low time twl S_CLK (1card) 10 - ns Clock high time twh S_CLK 10 - ns Clock rise time ttlh S_CLK - 10 ns Clock fall time tthl S_CLK - 10 ns *: 0 Hz means to stop the clock. The given minimum frequency range is for cases where a continuous clock is required. Card Inputs CMD, DAT (referenced to Clock CLK) Parameter Symbol Pin Name Conditions Input set-up time Input hold time tisu tih S_CMD, S_DATA3: 0 S_CMD, S_DATA3: 0 CCARD 10 pf (1card) Min Value Max Remarks 5 - ns 5 - ns Card Outputs CMD, DAT (referenced to Clock CLK) Parameter Symbol Pin Name Conditions Output Delay time during Data Transfer Mode Output Delay time during Identification Mode todly todly S_CMD, S_DATA3: 0 S_CMD, S_DATA3: 0 CCARD 40 pf (1card) Min Value Max Remarks 0 14 ns 0 50 ns twl twh S_CLK (SD Clock) S_CMD, S_DATA3: 0 (Card Input) VIH tthl VIL todly(max) tisu VIL VIH VIL VIH ttlh VIH VIL tih todly(min) VIH S_CMD, S_DATA3: 0 (Card Output) VOH VOL VOH VOL Default-Speed Mode Notes: The Card Input corresponds to the Host Output and the Card Output corresponds to the Host Input because this model is the Host. For more information about clock frequency (fpp), see Chapter 15: SD card Interface in FM4 Family Peripheral Manual Main Part ( ). Document Number: Rev.*B Page 169 of 201

170 High-Speed Mode Clock CLK (All values are referred to VIH and VIL) (VCC = 2.7V to 3.6V, VSS = 0V) Value Parameter Symbol Pin Name Conditions Remarks Min Max Clock frequency Data fpp S_CLK 0 50 MHz Transfer Mode CCARD Clock low time 10 twl S_CLK 7 - ns pf Clock high time twh S_CLK 7 - ns (1 card) Clock rise time ttlh S_CLK - 3 ns Clock fall time tthl S_CLK - 3 ns Card Inputs CMD, DAT (referenced to Clock CLK) Parameter Symbol Pin Name Conditions Input set-up time Input hold time tisu tih S_CMD, S_DATA3: 0 S_CMD, S_DATA3: 0 CCARD 10 pf (1 card) Min Value Max Remarks 6 - ns 2 - ns Card Outputs CMD, DAT (referenced to Clock CLK) Value Parameter Symbol Pin Name Conditions Remarks Min Max Output delay time during S_CMD, CL 40 pf todly 0 14 ns data transfer mode S_DATA3: 0 (1 card) S_CMD, CL 15 pf Output hold time toh ns S_DATA3: 0 (1 card) Total system capacitance CL - 1 card - 40 pf for each line* *: In order to satisfy severe timing, host shall drive only one card. twl twh S_CLK (SD Clock) S_CMD, S_DATA3: 0 (Card Input) 50%V CC todly(max) VIH tthl VIL tisu VIL VIH VIL VIH ttlh tih VIH VIL toh(min) 50%V CC VIH S_CMD, S_DATA3: 0 (Card Output) VOH VOL VOH VOL High-Speed Mode Notes: The Card Input corresponds to the Host Output and the Card Output corresponds to the Host Input because this model is the Host. For more information about clock frequency (fpp), see Chapter 15: SD card Interface in FM4 Family Peripheral Manual Main Part ( ). Document Number: Rev.*B Page 170 of 201

171 ETM/ HTM Timing (VCC = 2.7V to 5.5V, VSS = 0V) Data hold Parameter Symbol Pin Name Conditions TRACECLK frequency TRACECLK clock cycle tetmh 1/tTRACE ttrace TRACECLK, TRACED[15: 0] TRACECLK Min Value Max Unit VCC 4.5 V 2 9 ns VCC <4.5 V 2 15 VCC 4.5 V 50 MHz VCC <4.5 V 32 MHz VCC 4.5 V 20 - ns VCC <4.5 V ns Remarks Note: When the external load capacitance CL = 30 pf. HCLK TRACECLK TRACED[15: 0] Document Number: Rev.*B Page 171 of 201

172 JTAG Timing Parameter Symbol Pin Name Conditions TMS, TDI setup time TMS, TDI hold time TDO delay time tjtags tjtagh tjtagd TCK, TMS, TDI TCK, TMS, TDI TCK, TDO Note: When the external load capacitance CL = 30 pf. VCC 4.5 V VCC <4.5 V VCC 4.5 V VCC <4.5 V Min Value Max (VCC = 2.7V to 5.5V, VSS = 0V) Unit 15 - ns 15 - ns VCC 4.5 V - 25 VCC <4.5 V - 45 ns Remarks TCK TMS/TDI TDO Document Number: Rev.*B Page 172 of 201

173 I 2 S Timing Master Mode Timing Parameter Symbol Pin Name Conditions Min Value Max Unit Output frequency fmcyc I2SCK MHz Output clock pulse width tmhw % I2SCK - tmlw % I2SCK I2SWS I2SCK, tdfs delay time I2SWS ns I2SCK I2SDO I2SCK, tddo delay time* I2SDO ns I2SDI I2SCK thsdi setup time I2SCK, ns I2SDI I2SCK I2SDI thdi hold time ns Input signal rise time tfi ns I2SDI Input signal fall time tfi ns *: Except for the first bit of transmission frame Notes: When the external load capacitance CL = 20 pf (VCC = 2.7V to 5.5V, VSS = 0V) Remarks When I2SWS = 48 khz, I2MCLK = 256 I2SWS Frame synchronization signal (I2SWS) is settable to 48 khz, 32 khz, 16 khz. See Chapter7-2: I 2 S (Inter-IC Sound bus) Interface in FM4 Family Peripheral Manual Communication Macro Part ( ) for the details. Document Number: Rev.*B Page 173 of 201

174 t mcyc I2SCK (CPOL=0) t mhw t mlw I2SCK (CPOL=1) t dfs t dfs I2SWS (FSPH=0, FSLN=0) I2SWS (FSPH=1, FSLN=0) t dfs t dfs t dfs t dfs I2SWS (FSPH=0, FSLN=1) t dfs t dfs I2SWS (FSPH=1, FSLN=1) t ddo I2SDO t sdi t hdi t sdi t hdi I2SDI (SMPL=0) I2SDI (SMPL=1) t sdi t hdi Note: See Chapter7-2: I 2 S (Inter-IC Sound bus) Interface in FM4 Family Peripheral Manual Communication Macro Part ( ) for the details of CPOL, FSPH, FSLIN, and SMPL. I2SDI 0.8 V CC 0.8 V CC 0.8 V CC 0.2 V CC 0.2 V CC t fi t ri Document Number: Rev.*B Page 174 of 201

175 Slave Mode Timing Value Parameter Symbol Pin Name Conditions Unit Min Max Input frequency fscyc I2SCK MHz Input clock pulse width tshw % I2SCK - tslw % I2SWS I2SCK I2SCK, tsfi Setup time I2SWS ns I2SWS I2SCK I2SCK, thfi Hole time I2SWS ns I2SCK I2SDO Delay time *1 tddo ns I2SCK, I2SDO I2SCK I2SDO Delay time *2 tdfb ns I2SDI I2SCK tsdi ns Setup time I2SCK, I2SDI I2SDI I2SCK thdi ns Hole time Input signal rise time tfi I2SCK, ns Input signal fall time tfi I2SWS, I2SDI ns *1: Except for the first bit of transmission frame *2: When FSPH bit = 1. Notes: When the external load capacitance CL = 20 pf (VCC = 2.7V to 5.5V, VSS = 0V) Remarks When I2SWS = 48 khz, I2MCLK = 256 I2SWS Frame synchronization signal (I2SWS) is settable to 48 khz, 32 khz, 16 khz. See Chapter7-2: I 2 S (Inter-IC Sound bus) Interface in FM4 Family Peripheral Manual Communication Macro Part ( ) for the details. Document Number: Rev.*B Page 175 of 201

176 t scyc I2SCK (CPOL=0) t shw t slw I2SCK (CPOL=1) t sfi t hfi I2SWS (FSPH=0, FSLN=0) I2SWS (FSPH=1, FSLN=0) t sfi t hfi t sfi I2SWS (FSPH=0, FSLN=1) I2SWS (FSPH=1, FSLN=1) t sfi t dfb1 t ddo I2SDO t sdi t hdi t sdi t hdi I2SDI (SMPL=0) I2SDI (SMPL=1) t sdi t hdi Notes: See Chapter7-2: I 2 S (Inter-IC Sound bus) Interface in FM4 Family Peripheral Manual Communication Macro Part ( ) for the details of FSPH, FSLN, SMPL I2SCK is selectable polarity by CPOL bit of CNTREG register I2SCK I2SWS I2SDI 0.8 V CC 0.8 V CC 0.2 V CC 0.8 V CC 0.2 V CC t fi t ri Document Number: Rev.*B Page 176 of 201

177 I2SMCLK Input Characteristics (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Min Value Max Unit Remarks Input frequency fchs I2SMCK MHz Input clock cycle tcylhs ns Input clock pulse width - - Input clock rise time and fall time tcfs tcrs PWHS/tCYLHS PWLS/tCYLHS % ns When using external clock When using external clock t CYLHS I2SMCLK 0.8 V CC 0.8 V CC 0.8 V CC 0.2 V CC 0.2 V CC P WHS t CFS P WLS t CRS I2SMCLK Output Characteristics (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Min Value Max Unit Remarks Output frequency fchs I2SMCK MHz Document Number: Rev.*B Page 177 of 201

178 High-Speed Quad SPI Timing Parameter Symbol Pin Name Conditions Serial clock frequency tscycm Q_SCK_0 Enabled CS CLK Starting Time (mode0/mode2) Enabled CS CLK Starting Time (mode1/mode3) CLK Last Disabled CS Time (mode0/mode2) CLK Last Disabled CS Time (mode1/mode3) toslsk02 SIO Data output time tosdat Q_SCK_0, Q_IO0_0, Q_IO1_0, Q_IO2_0, Q_IO3_0 CL = 15 pf, VCC = 3.0 to 3.6V Min Value (VCC = 2.7V to 3.6V, VSS = 0V) Max Unit Remarks - 66 MHz *1 CL = 30 pf - 50 MHz *2 1.5 tscycm ns toslsk13 Q_SCK_0, tscycm ns Q_CS0_0, CL = 30 pf Q_CS1_0, tosksl02 Q_CS2_0 tscycm - ns tosksl tscycm - ns CL = 15 pf, VCC = 3.0 to 3.6V SIO Setup tdsset CL = 30 pf 0 5 ns CL = 30 pf ns * *2 SIO Hold tsdhold CL = 30 pf 0.5 tscycm - ns *1: When RTM = 1 and mode = 0, 1, 3 *2: When RTM = 1 and mode = 2 or RTM = 0 and mode = 0, 1, 2, 3 Notes: See Chapter8-3: High-Speed Quad SPI controller in FM4 Family Peripheral Manual Communication Macro Part ( ) for the detail of RTM mode. When using High-Speed Quad SPI, please set PDSR register to set the pin drive capability for VCC = 3V. See Chapter12: I/O Port in FM4 Family Peripheral Manual Main Part ( ) for the details. Document Number: Rev.*B Page 178 of 201

179 Q_CS0, Q_CS1, Q_CS2 t SCYCM Q_SCK mode0 mode2 mode1 mode3 t OSLSK13 t OSLSK02 t OSKSL13 t OSKSL02 Q_IO0, Q_IO1, Q_IO2, Q_IO3 t DSSET output t SDHOLD t OSDAT Document Number: Rev.*B Page 179 of 201

180 bit A/D Converter Electrical Characteristics for the A/D Converter (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V) Parameter Symbol Pin Value Name Min Typ Max Unit Resolution bit Integral nonlinearity LSB Differential nonlinearity LSB Zero transition voltage VZT ANxx mv Full-scale transition voltage VFST ANxx AVRH 15 - AVRH + 15 mv AVCC AVCC + 15 mv Remarks AVRH = 2.7 V to 5.5 V Conversion time *1 - - μs AVCC 4.5 V Sampling time *2 ts - Compare clock cycle *3 tcck - State transition time to operation permission Power supply current (analog + digital) Reference power supply current (AVRH) AVCC 4.5 V 10 μs AVCC < 4.5 V AVCC 4.5 V ns AVCC < 4.5 V tstt μs - AVCC - AVRH ma A/D 1 unit operation μa When A/D stop ma A/D 1 unit operation AVRH = 5.5 V μa When A/D stop Analog capacity CAIN pf Analog resistance RAIN AVCC 4.5 V kω 1.8 AVCC < 4.5 V Interchannel disparity LSB Analog port leak current - ANxx μa Analog voltage - ANxx AVSS - AVRH V AVSS - AVCC V AVCC Tcck < 50 ns - AVRH V Reference voltage AVCC Tcck 50 ns - AVRL AVSS - AVSS V *1: The conversion time is the value of sampling time (TS) + compare time (TC). The condition of the minimum conversion time is when the value of TS = 150 ns and Tc = 350 ns (AVCC 4.5V). Ensure that it satisfies the value of sampling time (TS) and compare clock cycle (TCCK). For setting of sampling time and compare clock cycle, see Chapter 1-1: A/D Converter in FM4 Family Peripheral Manual Analog Macro Part ( ). The register setting of the A/D converter is reflected by the APB bus clock timing. For more information about the APB bus number to which the A/D converter is connected, see 8. Block Diagram in this data sheet. The sampling and compare clock are set at base clock (HCLK). *2: A necessary sampling time changes by external impedance. Ensure that it sets the sampling time to satisfy (Equation 1). *3: The compare time (TC) is the value of (Equation 2). Document Number: Rev.*B Page 180 of 201

181 Rext ANxx Analog pin R AIN Rin Comparator Analog signal source Cin C AIN (Equation 1) Ts (RAIN + Rext) CAIN 9 ts: Sampling time RAIN: Input resistance of A/D = 1.2 kω at 4.5V AVCC 5.5V Input resistance of A/D = 1.8 kω at 2.7V AVCC < 4.5V CAIN: Input capacity of A/D = pf at 2.7V AVCC 5.5V Rext: Output impedance of external circuit (Equation 2) Tc = Tcck 14 tc: Compare time tcck: Compare clock cycle Document Number: Rev.*B Page 181 of 201

182 Digital output Digital output S6E2C5 Series Definition of 12-bit A/D Converter Terms Resolution: Integral Nonlinearity: Differential Nonlinearity: Analog variation that is recognized by an A/D converter. Deviation of the line between the zero-transition point (0b b ) and the full-scale transition point (0b b ) from the actual conversion characteristics. Deviation from the ideal value of the voltage that is required to change the output code by 1 LSB. Integral Nonlinearity Differential Nonlinearity 0xFFF 0xFFE 0xFFD 0x004 0x003 0x002 0x001 Actual conversion characteristics {1 LSB(N-1) + VZT} (Actuallymeasured value) (Actually-measured value) Actual conversion characteristics Ideal characteristics VZT VNT VFST (Actually-measured value) 0x(N+1) 0xN 0x(N-1) 0x(N-2) Actual conversion characteristics Ideal characteristics VNT V(N+1)T (Actually-measured value) (Actually-measured value) Actual conversion characteristics AVss AVRH AVss AVRH Analog Analog Integral Nonlinearity of digital output N = VNT - {1LSB (N - 1) + VZT} 1LSB [LSB] Differential Nonlinearity of digital output N = V(N + 1) T - VNT 1LSB - 1 [LSB] 1LSB = VFST - VZT 4094 N: A/D converter digital output value. VZT: Voltage at which the digital output changes from 0x000 to 0x001. VFST: Voltage at which the digital output changes from 0xFFE to 0xFFF. VNT: Voltage at which the digital output changes from 0x(N 1) to 0xN. Document Number: Rev.*B Page 182 of 201

183 bit D/A Converter Electrical Characteristics for the D/A Converter Parameter Symbol Resolution - Conversion time Pin Name Min Value Typ Max Unit bit (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V) tc μs Load 20 pf tc μs Load 100 pf Remarks Integral nonlinearity* INL LSB Differential DAx DNL LSB nonlinearity* mv When setting 0x000 Output voltage offset VOFF mv When setting 0xFFF Analog output kω D/A operation RO impedance MΩ When D/A stop Power supply current* *: During no load IDDA AVCC μs D/A 1ch operation AVCC = 3.3 V μs D/A 1ch operation AVCC = 5.0 V IDSA μs When D/A stop Document Number: Rev.*B Page 183 of 201

184 12.7 USB Characteristics (VCC = AVCC = 2.7V to 5.5V, USBVCC0 = USBVCC1 = 3.0V to 3.6V, VSS = AVSS = 0V) Parameter Symbol Pin Name Conditions Min Value Max Unit Remarks Input characteristics Output characteristics Input H level voltage VIH USBVCC V *1 Input L level voltage VIL - VSS V *1 Differential sensitivity VDI V *2 Different common mode range VCM V *2 Output H level voltage Output L level voltage VOH VOL UDP0/ UDM0, UDP1/ UDM1 External pull-down resistance = 15 kω External pull-up resistance = 1.5 kω V * V *3 Crossover voltage VCRS V *4 Rise time tfr Full-Speed 4 20 ns *5 Fall time tff Full-Speed 4 20 ns *5 Rise/fall time matching tfrfm Full-Speed % *5 Output impedance ZDRV Full-Speed Ω *6 Rise time tlr Low-Speed ns *7 Fall time tlf Low-Speed ns *7 Rise/fall time matching tlrfm Low-Speed % *7 *1: The switching threshold voltage of the single-end-receiver of USB I/O buffer is set as within VIL (Max) = 0.8 V, VIH (Min) = 2.0 V (TTL standard). There is some hysteresis applied to lower noise sensitivity. *2: Use differential-receiver to receive USB differential data signal. Differential-receiver has 200 mv of differential sensitivity when the differential data is within 0.8V to 2.5V to the local ground reference level. Above voltage range is the common mode voltage range. Minimum differential sensitivity [V] Common mode voltage [V] Document Number: Rev.*B Page 184 of 201

185 *3: The output drive capability of the driver is below 0.3 V at low state (VOL) (to 3.6 V and 1.5 kω load), and 2.8 V or above (to the VSS and 1.5 kω load) at high state (VOH). *4: The cross voltage of the external differential output signal (D +/D ) of USB I/O buffer is within 1.3 V to 2.0 V. VCRS specified range *5: They indicate rise time (TRISE) and fall time (TFALL) of the full-speed differential data signal. They are defined by the time between 10% and 90% of the output signal voltage. For full-speed buffer, TR/TF ratio is regulated as within ± 10% to minimize RFI emission. Rise time Falling time Document Number: Rev.*B Page 185 of 201

186 *6: USB Full-speed connection is performed via twisted-pair cable shield with 90 Ω ± 15% characteristic impedance (differential mode). USB standard defines that the output impedance of the USB driver must be in the range from 28 Ω to 44 Ω. So, a discrete series resistor (Rs) addition is defined in order to satisfy the above definition and keep balance. When using this USB I/O, use it with 25 Ω to 30 Ω (recommended value 27 Ω) series resistor Rs. 28Ω to 44Ω Equiv. Imped. 28Ω to 44Ω Equiv. Imped. Mount it as external resistance. Rs series resistor 25Ω to 30Ω Series resistor of 27Ω (recommendation value) must be added. And, use "resistance with an uncertainty of 5% by E24 sequence. *7: They indicate rise time (Trise) and fall time (Tfall) of the low-speed differential data signal. They are defined by the time between 10% and 90% of the output signal voltage. Rise time Falling time Note: See Low-Speed Load (Compliance Load) for conditions of external load. Document Number: Rev.*B Page 186 of 201

187 Low-Speed Load (Upstream Port Load) - Reference 1 CL=50pF to 150pF CL=50pF to 150pF Low-Speed Load (Downstream Port Load) - Reference 2 CL= 200pF to 600pF CL= 200pF to 600pF Low-Speed Load (Compliance Load) CL=200pF to 450pF CL=200pF to 450pF Document Number: Rev.*B Page 187 of 201