32-bit ARM Cortex -M4F FM4 Microcontroller

Transcription

1 32-bit ARM Cortex -M4F FM4 Microcontroller The MB9B360R Series are a highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance and competitive cost. These series are based on the ARM Cortex -M4F Processor with on-chip Flash memory and SRAM, and has peripheral functions such as Motor Control Timers, ADCs and Communication Interfaces (USB, UART, CSIO, I 2 C, LIN). Features 32-bit ARM Cortex -M4F Core Processor version: r0p1 Up to 160 MHz Frequency Operation FPU built-in Support DSP instruction Memory Protection Unit (MPU): improves the reliability of an embedded system Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 128 peripheral interrupts and 16 priority levels 24-bit System timer (Sys Tick): System timer for OS task management On-chip Memories [Flash memory] These series are based on two independent on-chip Flash memories. MainFlash memory Up to 1024 Kbytes Built-in Flash Accelerator System with 16 Kbytes trace buffer memory The read access to Flash memory can be achieved without wait-cycle up to operation frequency of 72 MHz. Even at the operation frequency more than 72 MHz, an equivalent access to Flash memory can be obtained by Flash Accelerator System. Security function for code protection WorkFlash memory 32 Kbytes Read cycle: 6wait-cycle: the operation frequency more than 120 MHz, and up to 160 MHz 4wait-cycle: the operation frequency more than 72 MHz, and up to 120 MHz 2wait-cycle: the operation frequency more than 40 MHz, and up to 72 MHz 0wait-cycle: the operation frequency up to 40MHz Security function is shared with code protection [SRAM] This is composed of three independent SRAMs (SRAM0, SRAM1 and SRAM2). SRAM0 is connected to I-code bus or D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are connected to System bus of Cortex-M4F core. SRAM0: Up to 64 Kbytes SRAM1: Up to 32 Kbytes SRAM2: Up to 32 Kbytes External Bus Interface Supports SRAM, NOR, NAND Flash and SDRAM device Up to 9 chip selects CS0 to CS8 (CS8 is only for SDRAM) 8-/16-bit Data width Up to 25-bit Address bit Maximum Access size: 256M byte Supports Address/Data multiplex Supports external RDY function Supports scramble function Possible to set the validity/invalidity of the scramble function for the external areas 0x6000_0000 to 0xDFFF_FFFF in 4 Mbytes units. Possible to set two kinds of the scramble key Note: It is necessary to prepare the dedicated software library to use the scramble function. USB Interface USB interface is composed of Device and Host. [USB device] USB2.0 Full-Speed supported Max 6 EndPoint supported EndPoint 0 is control transfer EndPoint 1, 2 can be selected Bulk-transfer, Interrupttransfer or Isochronous-transfer EndPoint 3 to 5 can select Bulk-transfer or Interrupttransfer EndPoint 1 to 5 comprise Double Buffer The size of each endpoint is according to the follows. Endpoint 0, 2 to 5 : 64bytes Endpoint 1 : 256bytes Cypress Semiconductor Corporation 198 Champion Court San Jose, CA Document Number: Rev.*B Revised February 2, 2017

2 [USB host] USB2.0 Full/Low-speed supported Bulk-transfer, interrupt-transfer and Isochronous-transfer support USB Device connected/dis-connected automatically detect IN/OUT token handshake packet automatically Max 256-byte packet-length supported Wake-up function supported Multi-function Serial Interface (Max 8 channels) 64 bytes with FIFO (the FIFO step numbers are variable depending on the settings of the communication mode or bit length.) Operation mode is selectable from the followings for each channel. UART CSIO LIN I 2 C [UART] Full-duplex double buffer Selection with or without parity supported Built-in dedicated baud rate generator External clock available as a serial clock Hardware Flow control : Automatically control the transmission by CTS/RTS (only ch.4) Various error detect functions available (parity errors, framing errors, and overrun errors) [CSIO] Full-duplex double buffer Built-in dedicated baud rate generator Overrun error detect function available Serial chip select function (ch.6 and ch.7 only) Supports high-speed SPI (ch.4 and ch.6 only) Data length 5 to 16-bit [LIN] LIN protocol Rev.2.1 supported Full-duplex double buffer Master/Slave mode supported LIN break field generation (can change to 13 to 16-bit length) LIN break delimiter generation (can change to 1 to 4-bit length) Various error detect functions available (parity errors, framing errors, and overrun errors) [I 2 C] Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps) supported Fast-mode Plus (Fm+) (Max 1000 kbps, only for ch.3=ch.a and ch.7=ch.b) supported DMA Controller (8 channels) DMA Controller has an independent bus for CPU, so CPU and DMA Controller can process simultaneously. 8 independently configured and operated channels Transfer can be started by software or request from the builtin peripherals Transfer address area: 32-bit (4 Gbytes) Transfer mode: Block transfer/burst transfer/demand transfer Transfer data type: bytes/half-word/word Transfer block count: 1 to 16 Number of transfers: 1 to DSTC (Descriptor System data Transfer Controller) (128 channels) The DSTC can transfer data at high-speed without going via the CPU. The DSTC adopts the Descriptor system and, following the specified contents of the Descriptor which has already been constructed on the memory, can access directly the memory /peripheral device and performs the data transfer operation. It supports the software activation, the hardware activation and the chain activation functions. A/D Converter (Max 24 channels) [12-bit A/D Converter] Successive Approximation type Built-in 3 units Conversion time: 5V Priority conversion available (priority at 2levels) Scanning conversion mode Built-in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion: 4steps) DA converter (Max 2 channels) R-2R type 12-bit resolution Document Number: Rev.*B Page 2 of 168

3 Base Timer (Max 8 channels) Operation mode is selectable from the followings for each channel. 16-bit PWM timer 16-bit PPG timer 16-/32-bit reload timer 16-/32-bit PWC timer General Purpose I/O Port This series can use its pins as general purpose I/O ports when they are not used for external bus or peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function can be allocated. Capable of pull-up control per pin Capable of reading pin level directly Built-in the port relocate function Up to 100 high-speed general-purpose I/O 120pin Package Some pin is 5V tolerant I/O. See Pin Description and I/O Circuit Type for the corresponding pins. Multi-function Timer (Max 2 units) The Multi-function timer is composed of the following blocks. Minimum resolution: 6.25 ns 16-bit free-run timer 3ch./unit Input capture 4ch./unit Output compare 6ch./unit A/D activation compare 6ch./unit Waveform generator 3ch./unit 16-bit PPG timer 3ch./unit The following function can be used to achieve the motor control. PWM signal output function DC chopper waveform output function Dead time function Input capture function A/D convertor activate function DTIF (Motor emergency stop) interrupt function Real-time clock (RTC) The Real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 00 to 99. Interrupt function with specifying date and time (Year/Month/Day/Hour/Minute) is available. This function is also available by specifying only Year, Month, Day, Hour or Minute. Timer interrupt function after set time or each set time. Capable of rewriting the time with continuing the time count. Leap year automatic count is available. Quadrature Position/Revolution Counter (QPRC) (Max 2 channels) The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position encoder. Moreover, it is possible to use up/down counter. The detection edge of the three external event input pins AIN, BIN and ZIN is configurable. 16-bit position counter 16-bit revolution counter Two 16-bit compare registers Dual Timer (32/16-bit Down Counter) The Dual Timer consists of two programmable 32/16-bit down counters. Operation mode is selectable from the followings for each channel. Free-running Periodic (=Reload) One-shot Watch Counter The Watch counter is used for wake up from the low-power consumption mode. It is possible to select the main clock, sub clock, built-in high-speed CR clock or built-in low-speed CR clock as the clock source. Interval timer: up to 64s Sub Clock : khz External Interrupt Controller Unit External interrupt input pin: Max 16 pins Include one non-maskable interrupt (NMI) Watchdog Timer (2 channels) A watchdog timer can generate interrupts or a reset when a time-out value is reached. This series consists of two different watchdogs, a "Hardware" watchdog and a "Software" watchdog. "Hardware" watchdog timer is clocked by low-speed internal CR oscillator. Therefore, "Hardware" watchdog is active in any power saving mode except STOP. Document Number: Rev.*B Page 3 of 168

4 CRC (Cyclic Redundancy Check) Accelerator The CRC accelerator helps a verify data transmission or storage integrity. CCITT CRC16 and IEEE CRC32 are supported. CCITT CRC16 Generator Polynomial: 0x1021 IEEE CRC32 Generator Polynomial: 0x04C11DB7 SD Card Interface It is possible to use the SD card that conforms to the following standards. Part 1 Physical Layer Specification version 3.01 Part E1 SDIO Specification version 3.00 Part A2 SD Host Controller Standard Specification version bit or 4-bit data bus Clock and Reset [Clocks] Five clock sources (2 external oscillators, 2 internal CR oscillator, and Main PLL) that are dynamically selectable. Main clock: Sub Clock : 4 MHz to 48 MHz khz High-speed internal CR Clock: 4 MHz Low-speed internal CR Clock: 100 khz Main PLL Clock [Resets] Reset requests from INITX pin Power on reset Software reset Watchdog timers reset Low voltage detector reset Clock supervisor reset Clock Super Visor (CSV) Clocks generated by internal CR oscillators are used to supervise abnormality of the external clocks. External OSC clock failure (clock stop) is detected, reset is asserted. External OSC frequency anomaly is detected, interrupt or reset is asserted. Low-Voltage Detector (LVD) This Series include 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the voltage has been set, Low-Voltage Detector generates an interrupt or reset. LVD1: error reporting via interrupt LVD2: auto-reset operation Low-power Consumption Mode Six low-power consumption modes are supported. SLEEP TIMER RTC STOP Deep standby RTC (selectable from with/without RAM retention) Deep standby stop (selectable from with/without RAM retention) VBAT The consumption power during the RTC operation can be reduced by supplying the power supply independent from the RTC (calendar circuit)/32 khz oscillation circuit. The following circuits can also be used. RTC 32 khz oscillation circuit Power-on circuit Back up register: 32 bytes Port circuit Debug Serial Wire JTAG Debug Port (SWJ-DP) Embedded Trace Macrocells (ETM) provide comprehensive debug and trace facilities. Unique ID Unique value of the device (41-bit) is set. Power Supply Three Power Supplies Wide range voltage: VCC = 2.7V to 5.5V Power supply for USB I/O: USBVCC = 3.0V to 3.6V (when USB is used) = 2.7V to 5.5V (when GPIO is used) Power supply for VBAT: VBAT = 2.7V to 5.5V Document Number: Rev.*B Page 4 of 168

5 Contents 1. Product Lineup Packages Pin Assignment Pin Description I/O Circuit Type Handling Precautions Precautions for Product Design Precautions for Package Mounting Precautions for Use Environment Handling Devices Block Diagram Memory Size Memory Map Pin Status in Each CPU State Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions DC Characteristics Current Rating Pin Characteristics AC Characteristics Main Clock Input Characteristics Sub Clock Input Characteristics Built-in CR Oscillation Characteristics Operating Conditions of Main PLL (In the case of using main clock for input clock of PLL) Operating Conditions of USB PLL (In the case of using main clock for input clock of PLL) Operating Conditions of Main PLL (In the case of using built-in high-speed CR clock for input clock of main PLL) Reset Input Characteristics Power-on Reset Timing GPIO Output Characteristics External Bus Timing Base Timer Input Timing CSIO/UART Timing External Input Timing Quadrature Position/Revolution Counter Timing I 2 C Timing SD Card Interface Timing ETM Timing JTAG Timing bit A/D Converter bit D/A Converter USB Characteristics Low-Voltage Detection Characteristics Low-Voltage Detection Reset Interrupt of Low-Voltage Detection MainFlash Memory Write/Erase Characteristics WorkFlash Memory Write/Erase Characteristics Document Number: Rev.*B Page 5 of 168

6 12.11 Standby Recovery Time Recovery cause: Interrupt/WKUP Recovery cause: Reset Ordering Information Package Dimensions Major Changes Document History Sales, Solutions, and Legal Information Document Number: Rev.*B Page 6 of 168

7 1. Product Lineup Memory size Product name MB9BF366M/N/R MB9BF367M/N/R MB9BF368M/N/R MainFlash memory 512 Kbytes 768 Kbytes 1024 Kbytes WorkFlash memory 32 Kbytes 32 Kbytes 32 Kbytes On-chip SRAM 64 Kbytes 96 Kbytes 128 Kbytes SRAM0 32 Kbytes 48 Kbytes 64 Kbytes SRAM1 16 Kbytes 24 Kbytes 32 Kbytes SRAM1 16 Kbytes 24 Kbytes 32 Kbytes Function Product name MB9BF366M MB9BF367M MB9BF368M MB9BF366N MB9BF367N MB9BF368N MB9BF366R MB9BF367R MB9BF368R Pin count / /144 CPU Cortex-M4F, MPU, NVIC 128ch. Freq. 160 MHz Power supply voltage range 2.7V to 5.5V USB2.0 (Device/Host) 1ch. DMAC 8ch. DSTC 128ch. External Bus Interface Addr:25-bit (Max), Addr:25-bit (Max), Addr:19-bit (Max), R/W data: 8/16-bit R/W data: 8/16-bit R/W data: 8-bit (Max), (Max), (Max), CS:9 (Max), CS:9 (Max), CS:5 (Max), SRAM, SRAM, SRAM, NOR Flash, NOR Flash, NOR Flash SDRAM NAND Flash, SDRAM Multi-function Serial Interface (UART/CSIO/LIN/I 2 C) 8ch. (Max) Base Timer (PWC/Reload timer/pwm/ppg) 8ch. (Max) A/D activation compare 6ch. Input capture 4ch. Free-run timer 3ch. Output compare 6ch. 2 units (Max) Waveform generator 3ch. PPG 3ch. SD Card Interface 1 unit QPRC 2ch. (Max) Dual Timer 1 unit Real-Time Clock 1 unit Watch Counter 1 unit CRC Accelerator Yes Watchdog Timer 1ch. (SW) + 1ch. (HW) External Interrupts 16pins (Max) + NMI 1 I/O Ports 63pins (Max) 80pins (Max) 100pins (Max) MF Timer 12-bit A/D Converter 16ch. (3 units) 24ch. (3 units) 12-bit D/A Converter CSV (Clock Super Visor) LVD (Low-Voltage Detector) High-speed Built-in CR Low-speed Debug Function Unique ID 2 units (Max) Yes 2ch. 4 MHz 100 khz SWJ-DP/ETM Yes Note: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use the port relocate function of the I/O port according to your function use. See 12. Electrical Characteristics AC Characteristics Built-in CR Oscillation Characteristics for accuracy of built-in CR. Document Number: Rev.*B Page 7 of 168

8 2. Packages Package Product name MB9BF366M MB9BF367M MB9BF368M MB9BF366N MB9BF367N MB9BF368N MB9BF366R MB9BF367R MB9BF368R LQFP: LQH080 (0.5mm pitch) - - LQFP: LQJ080 (0.65mm pitch) - - QFP: PQH100 (0.65mm pitch) - - LQFP: LQI100 (0.5mm pitch) - - LQFP: LQM120 (0.5mm pitch) - - BGA: LDC112 (0.5mm pitch) - - BGA: LDC144 (0.5mm pitch) - - : Supported Note: See "Package Dimensions" for detailed information on each package. Document Number: Rev.*B Page 8 of 168

9 3. Pin Assignment LQH080/LQJ080 (TOP VIEW) VSS P81/UDP0 P80/UDM0 USBVCC P60/TIOA2_2/SCK5_0/NMIX/WKUP0/MRDY_0 P61/UHCONX0/TIOB2_2/SOT5_0/RTCCO_0/SUBOUT_0 P62/ADTG_3/SIN5_0/INT04_1/S_WP_0/MOEX_0 P63/CROUT_1/INT03_0/S_CD_0/MWEX_0 P00/TRSTX/MCSX7_0 P01/TCK/SWCLK P02/TDI/MCSX6_0 P03/TMS/SWDIO P04/TDO/SWO P09/AN19/TIOA3_2/SOT1_0/S_DATA2_0/MCSX5_0 P0A/SIN1_0/FRCK1_0/INT12_2/S_DATA3_0/MCSX1_0 P0B/TIOB6_1/SIN6_1/IC10_0/INT00_1/S_DATA0_0/MCSX0_0 P0C/TIOA6_1/SOT6_1/IC11_0/S_DATA1_0/MALE_0 P0D/TIOA5_2/SCK6_1/IC12_0/S_CMD_0/MDQM0_0 P0E/TIOB5_2/SCS6_1/IC13_0/S_CLK_0/MDQM1_0 VCC VCC 1 60 VSS P50/CTS4_0/AIN0_2/RTO10_0/INT00_0/MADATA00_ P21/AN17/SIN0_0/INT06_1 P51/RTS4_0/BIN0_2/RTO11_0/INT01_0/MADATA01_ P22/CROUT_0/AN16/TIOB7_1/SOT0_0 P52/SCK4_0/ZIN0_2/RTO12_0/MADATA02_ P23/AN15/TIOA7_1/SCK0_0/RTO00_1 P53/TIOA1_2/SOT4_0/RTO13_0/MADATA03_ P1B/AN11/SCK4_1/IC02_1/MAD18_0 P54/TIOB1_2/SIN4_0/RTO14_0/INT02_0/MADATA04_ P1A/AN10/SOT4_1/IC01_1/MAD17_0 P55/ADTG_1/SIN6_0/RTO15_0/INT07_2/MADATA05_ P19/AN09/SIN4_1/IC00_1/INT05_1/MAD16_0 P56/SOT6_0/DTTI1X_0/INT08_2/MADATA06_ P18/AN08/SCK2_2/MAD15_0 P30/TIOB0_1/RTS4_2/INT15_2/WKUP1/MADATA07_ AVRH P31/TIOB1_1/SIN3_1/INT09_2/MADATA08_ AVRL LQFP - 80 P32/TIOB2_1/SOT3_1/INT10_1/MADATA09_ AVSS P33/ADTG_6/TIOB3_1/SCK3_1/INT04_0/MADATA10_ AVCC P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_ P17/AN07/SOT2_2/WKUP3/MAD14_0 P3A/TIOA0_1/AIN0_0/RTO00_ P16/AN06/SIN2_2/INT14_1/MAD13_0 P3B/TIOA1_1/BIN0_0/RTO01_ P15/AN05/SCK0_1/MAD12_0 P3C/TIOA2_1/ZIN0_0/RTO02_ P14/AN04/SOT0_1/IC03_2/MAD11_0 P3D/TIOA3_1/RTO03_0/MAD00_ P13/AN03/SIN0_1/IC02_2/INT03_1/MAD10_0 P3E/TIOA4_1/RTO04_0/MAD01_ P12/AN02/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1/MAD09_0 P3F/TIOA5_1/RTO05_0/MAD02_ P11/AN01/SOT1_1/IC00_2/MAD08_0 VSS P10/AN00/SIN1_1/FRCK0_2/INT02_1/MAD07_0 P44/TIOA4_0/RTO14_1/DA0 P45/TIOB0_0/RTO15_1/DA1 INITX P46/X0A P47/X1A P48/VREGCTL P49/VWAKEUP VBAT C VSS VCC P4B/TIOB1_0/SCS7_1/MAD03_0 P4C/TIOB2_0/SCK7_1/AIN1_2/MAD04_0 P4D/TIOB3_0/SOT7_1/BIN1_2/INT13_2/MAD05_0 P4E/TIOB4_0/SIN7_1/ZIN1_2/FRCK1_1/INT11_1/WKUP2/MAD06_0 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS Note: The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: Rev.*B Page 9 of 168

10 LQI100 (TOP VIEW) VSS P81/UDP0 P80/UDM0 USBVCC P60/TIOA2_2/SCK5_0/NMIX/WKUP0/MRDY_0 P61/UHCONX0/TIOB2_2/SOT5_0/RTCCO_0/SUBOUT_0 P62/ADTG_3/SIN5_0/INT04_1/S_WP_0/MOEX_0 P63/CROUT_1/INT03_0/S_CD_0/MWEX_0 VSS P00/TRSTX/MCSX7_0 P01/TCK/SWCLK P02/TDI/MCSX6_0 P03/TMS/SWDIO P04/TDO/SWO P05/AN23/ADTG_0/TRACECLK/SIN7_0/INT01_1/MCSX2_0 P06/AN22/TRACED3/TIOB0_2/SOT7_0/MCSX3_0 P07/AN21/TRACED2/TIOA0_2/SCK7_0/MCLKOUT_0 P08/AN20/TRACED1/TIOB3_2/SCK1_0/MCSX4_0 P09/AN19/TRACED0/TIOA3_2/SOT1_0/S_DATA2_0/MCSX5_0 P0A/SIN1_0/FRCK1_0/INT12_2/S_DATA3_0/MCSX1_0 P0B/TIOB6_1/SIN6_1/IC10_0/INT00_1/S_DATA0_0/MCSX0_0 P0C/TIOA6_1/SOT6_1/IC11_0/S_DATA1_0/MALE_0 P0D/TIOA5_2/SCK6_1/IC12_0/S_CMD_0/MDQM0_0 P0E/TIOB5_2/SCS6_1/IC13_0/S_CLK_0/MDQM1_0 VCC VCC 1 75 VSS P50/CTS4_0/AIN0_2/RTO10_0/INT00_0/MADATA00_ P20/AN18/AIN1_1/INT05_0/MAD24_0 P51/RTS4_0/BIN0_2/RTO11_0/INT01_0/MADATA01_ P21/AN17/SIN0_0/BIN1_1/INT06_1/MAD23_0 P52/SCK4_0/ZIN0_2/RTO12_0/MADATA02_ P22/CROUT_0/AN16/TIOB7_1/SOT0_0/ZIN1_1 P53/TIOA1_2/SOT4_0/RTO13_0/MADATA03_ P23/AN15/TIOA7_1/SCK0_0/RTO00_1/MAD22_0 P54/TIOB1_2/SIN4_0/RTO14_0/INT02_0/MADATA04_ P1E/AN14/ADTG_5/FRCK0_1/MAD21_0 P55/ADTG_1/SIN6_0/RTO15_0/INT07_2/MADATA05_ P1D/AN13/RTS4_1/DTTI0X_1/MAD20_0 P56/SOT6_0/DTTI1X_0/INT08_2/MADATA06_ P1C/AN12/CTS4_1/IC03_1/MAD19_0 P30/TIOB0_1/RTS4_2/INT15_2/WKUP1/MADATA07_ P1B/AN11/SCK4_1/IC02_1/MAD18_0 P31/TIOB1_1/SIN3_1/INT09_2/MADATA08_ P1A/AN10/SOT4_1/IC01_1/MAD17_0 P32/TIOB2_1/SOT3_1/INT10_1/MADATA09_ P19/AN09/SIN4_1/IC00_1/INT05_1/MAD16_0 LQFP P33/ADTG_6/TIOB3_1/SCK3_1/INT04_0/MADATA10_ P18/AN08/SCK2_2/MAD15_0 P34/TIOB4_1/FRCK0_0/MADATA11_ AVRH P35/TIOB5_1/IC03_0/INT08_1/MADATA12_ AVRL P36/SIN5_2/IC02_0/INT09_1/MADATA13_ AVSS P37/SOT5_2/IC01_0/INT05_2/MADATA14_ AVCC P38/SCK5_2/IC00_0/INT06_2/MADATA15_ P17/AN07/SOT2_2/WKUP3/MAD14_0 P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2/MSDCLK_ P16/AN06/SIN2_2/INT14_1/MAD13_0 P3A/TIOA0_1/AIN0_0/RTO00_0/MSDCKE_ P15/AN05/SCK0_1/MAD12_0 P3B/TIOA1_1/BIN0_0/RTO01_0/MRASX_ P14/AN04/SOT0_1/IC03_2/MAD11_0 P3C/TIOA2_1/ZIN0_0/RTO02_0/MCASX_ P13/AN03/SIN0_1/IC02_2/INT03_1/MAD10_0 P3D/TIOA3_1/RTO03_0/MAD00_ P12/AN02/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1/MAD09_0 P3E/TIOA4_1/RTO04_0/MAD01_ P11/AN01/SOT1_1/IC00_2/MAD08_0 P3F/TIOA5_1/RTO05_0/MAD02_ P10/AN00/SIN1_1/FRCK0_2/INT02_1/MAD07_0 VSS VCC VCC P40/TIOA0_0/RTO10_1/INT12_1 P41/TIOA1_0/RTO11_1/INT13_1 P42/TIOA2_0/RTO12_1/MSDWEX_0 P43/ADTG_7/TIOA3_0/RTO13_1/MCSX8_0 P44/TIOA4_0/RTO14_1/DA0 P45/TIOB0_0/RTO15_1/DA1 INITX P46/X0A P47/X1A P48/VREGCTL P49/VWAKEUP VBAT C VSS VCC P4B/TIOB1_0/SCS7_1/MAD03_0 P4C/TIOB2_0/SCK7_1/AIN1_2/MAD04_0 P4D/TIOB3_0/SOT7_1/BIN1_2/INT13_2/MAD05_0 P4E/TIOB4_0/SIN7_1/ZIN1_2/FRCK1_1/INT11_1/WKUP2/MAD06_0 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS Note: The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: Rev.*B Page 10 of 168

11 LQM120 (TOP VIEW) VSS P81/UDP0 P80/UDM0 USBVCC P60/TIOA2_2/SCK5_0/NMIX/WKUP0/MRDY_0 P61/UHCONX0/TIOB2_2/SOT5_0/RTCCO_0/SUBOUT_0 P62/ADTG_3/SIN5_0/INT04_1/S_WP_0/MOEX_0 P63/CROUT_1/SIN5_1/INT03_0/S_CD_0/MWEX_0 P64/TIOA7_0/SOT5_1/INT10_2 P65/TIOB7_0/SCK5_1 P66/ADTG_8/SIN3_0/INT11_2 P67/TIOA7_2/SOT3_0 P68/TIOB7_2/SCK3_0/INT00_2 VSS P00/TRSTX/MCSX7_0 P01/TCK/SWCLK P02/TDI/MCSX6_0 P03/TMS/SWDIO P04/TDO/SWO P05/AN23/ADTG_0/TRACECLK/SIN7_0/INT01_1/MCSX2_0 P06/AN22/TRACED3/TIOB0_2/SOT7_0/MCSX3_0 P07/AN21/TRACED2/TIOA0_2/SCK7_0/MCLKOUT_0 P08/AN20/TRACED1/TIOB3_2/SCK1_0/MCSX4_0 P09/AN19/TRACED0/TIOA3_2/SOT1_0/S_DATA2_0/MCSX5_0 P0A/SIN1_0/FRCK1_0/INT12_2/S_DATA3_0/MCSX1_0 P0B/TIOB6_1/SIN6_1/IC10_0/INT00_1/S_DATA0_0/MCSX0_0 P0C/TIOA6_1/SOT6_1/IC11_0/S_DATA1_0/MALE_0 P0D/TIOA5_2/SCK6_1/IC12_0/S_CMD_0/MDQM0_0 P0E/TIOB5_2/SCS6_1/IC13_0/S_CLK_0/MDQM1_0 VCC VCC 1 90 VSS P50/CTS4_0/AIN0_2/RTO10_0/INT00_0/MADATA00_ P20/AN18/AIN1_1/INT05_0/MAD24_0 P51/RTS4_0/BIN0_2/RTO11_0/INT01_0/MADATA01_ P21/AN17/SIN0_0/BIN1_1/INT06_1/MAD23_0 P52/SCK4_0/ZIN0_2/RTO12_0/MADATA02_ P22/CROUT_0/AN16/TIOB7_1/SOT0_0/ZIN1_1 P53/TIOA1_2/SOT4_0/RTO13_0/MADATA03_ P23/AN15/TIOA7_1/SCK0_0/RTO00_1/MAD22_0 P54/TIOB1_2/SIN4_0/RTO14_0/INT02_0/MADATA04_ P24/SIN2_1/RTO01_1/INT01_2 P55/ADTG_1/SIN6_0/RTO15_0/INT07_2/MADATA05_ P25/TIOA5_0/SOT2_1/RTO02_1 P56/SOT6_0/DTTI1X_0/INT08_2/MADATA06_ P26/TIOB5_0/SCK2_1/RTO03_1 P57/SCK6_0/MADATA07_ P27/TIOA6_2/RTO04_1/INT02_2 P58/SIN4_2/AIN1_0/INT04_2/MADATA08_ P1F/ADTG_4/TIOB6_2/RTO05_1 P59/SOT4_2/BIN1_0/INT07_1/MADATA09_ P1E/AN14/ADTG_5/FRCK0_1/MAD21_0 P5A/SCK4_2/ZIN1_0/MADATA10_ P1D/AN13/RTS4_1/DTTI0X_1/MAD20_0 LQFP P5B/CTS4_2/MADATA11_ P1C/AN12/CTS4_1/IC03_1/MAD19_0 P30/TIOB0_1/RTS4_2/INT15_2/WKUP1/MADATA12_ P1B/AN11/SCK4_1/IC02_1/MAD18_0 P31/TIOB1_1/SIN3_1/INT09_2/MADATA13_ P1A/AN10/SOT4_1/IC01_1/MAD17_0 P32/TIOB2_1/SOT3_1/INT10_1/MADATA14_ P19/AN09/SIN4_1/IC00_1/INT05_1/MAD16_0 P33/ADTG_6/TIOB3_1/SCK3_1/INT04_0/MADATA15_ P18/AN08/SCK2_2/MAD15_0 P34/TIOB4_1/FRCK0_0/MNALE_ AVRH P35/TIOB5_1/IC03_0/INT08_1/MNCLE_ AVRL P36/SIN5_2/IC02_0/INT09_1/MNWEX_ AVSS P37/SOT5_2/IC01_0/INT05_2/MNREX_ AVCC P38/SCK5_2/IC00_0/INT06_ P17/AN07/SOT2_2/WKUP3/MAD14_0 P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2/MSDCLK_ P16/AN06/SIN2_2/INT14_1/MAD13_0 P3A/TIOA0_1/AIN0_0/RTO00_0/MSDCKE_ P15/AN05/SCK0_1/MAD12_0 P3B/TIOA1_1/BIN0_0/RTO01_0/MRASX_ P14/AN04/SOT0_1/IC03_2/MAD11_0 P3C/TIOA2_1/ZIN0_0/RTO02_0/MCASX_ P13/AN03/SIN0_1/IC02_2/INT03_1/MAD10_0 P3D/TIOA3_1/RTO03_0/MAD00_ P12/AN02/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1/MAD09_0 P3E/TIOA4_1/RTO04_0/MAD01_ P11/AN01/SOT1_1/IC00_2/MAD08_0 P3F/TIOA5_1/RTO05_0/MAD02_ P10/AN00/SIN1_1/FRCK0_2/INT02_1/MAD07_0 VSS VCC VCC P40/TIOA0_0/RTO10_1/INT12_1 P41/TIOA1_0/RTO11_1/INT13_1 P42/TIOA2_0/RTO12_1/MSDWEX_0 P43/ADTG_7/TIOA3_0/RTO13_1/MCSX8_0 P44/TIOA4_0/RTO14_1/DA0 P45/TIOB0_0/RTO15_1/DA1 INITX P46/X0A P47/X1A P48/VREGCTL P49/VWAKEUP VBAT C VSS VCC P4B/TIOB1_0/SCS7_1/MAD03_0 P4C/TIOB2_0/SCK7_1/AIN1_2/MAD04_0 P4D/TIOB3_0/SOT7_1/BIN1_2/INT13_2/MAD05_0 P4E/TIOB4_0/SIN7_1/ZIN1_2/FRCK1_1/INT11_1/WKUP2/MAD06_0 P70/TIOA4_2/AIN0_1/IC13_1 P71/TIOB4_2/BIN0_1/IC12_1/INT15_1 P72/TIOA6_0/SIN2_0/ZIN0_1/IC11_1/INT14_2 P73/TIOB6_0/SOT2_0/IC10_1/INT03_2 P74/SCK2_0/DTTI1X_1 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS Note: The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: Rev.*B Page 11 of 168

12 PQH100 (TOP VIEW) P50/CTS4_0/AIN0_2/RTO10_0/INT00_0/MADATA00_0 VCC VSS P81/UDP0 P80/UDM0 USBVCC P60/TIOA2_2/SCK5_0/NMIX/WKUP0/MRDY_0 P61/UHCONX0/TIOB2_2/SOT5_0/RTCCO_0/SUBOUT_0 P62/ADTG_3/SIN5_0/INT04_1/S_WP_0/MOEX_0 P63/CROUT_1/INT03_0/S_CD_0/MWEX_0 VSS P00/TRSTX/MCSX7_0 P01/TCK/SWCLK P02/TDI/MCSX6_0 P03/TMS/SWDIO P04/TDO/SWO P05/AN23/ADTG_0/TRACECLK/SIN7_0/INT01_1/MCSX2_0 P06/AN22/TRACED3/TIOB0_2/SOT7_0/MCSX3_0 P07/AN21/TRACED2/TIOA0_2/SCK7_0/MCLKOUT_0 P08/AN20/TRACED1/TIOB3_2/SCK1_0/MCSX4_0 P09/AN19/TRACED0/TIOA3_2/SOT1_0/S_DATA2_0/MCSX5_0 P0A/SIN1_0/FRCK1_0/INT12_2/S_DATA3_0/MCSX1_0 P0B/TIOB6_1/SIN6_1/IC10_0/INT00_1/S_DATA0_0/MCSX0_0 P0C/TIOA6_1/SOT6_1/IC11_0/S_DATA1_0/MALE_0 P0D/TIOA5_2/SCK6_1/IC12_0/S_CMD_0/MDQM0_0 P0E/TIOB5_2/SCS6_1/IC13_0/S_CLK_0/MDQM1_0 VCC VSS P20/AN18/AIN1_1/INT05_0/MAD24_0 P21/AN17/SIN0_0/BIN1_1/INT06_1/MAD23_ P51/RTS4_0/BIN0_2/RTO11_0/INT01_0/MADATA01_ P22/CROUT_0/AN16/TIOB7_1/SOT0_0/ZIN1_1 P52/SCK4_0/ZIN0_2/RTO12_0/MADATA02_ P23/AN15/TIOA7_1/SCK0_0/RTO00_1/MAD22_0 P53/TIOA1_2/SOT4_0/RTO13_0/MADATA03_ P1E/AN14/ADTG_5/FRCK0_1/MAD21_0 P54/TIOB1_2/SIN4_0/RTO14_0/INT02_0/MADATA04_ P1D/AN13/RTS4_1/DTTI0X_1/MAD20_0 P55/ADTG_1/SIN6_0/RTO15_0/INT07_2/MADATA05_ P1C/AN12/CTS4_1/IC03_1/MAD19_0 P56/SOT6_0/DTTI1X_0/INT08_2/MADATA06_ P1B/AN11/SCK4_1/IC02_1/MAD18_0 P30/TIOB0_1/RTS4_2/INT15_2/WKUP1/MADATA07_ P1A/AN10/SOT4_1/IC01_1/MAD17_0 P31/TIOB1_1/SIN3_1/INT09_2/MADATA08_ P19/AN09/SIN4_1/IC00_1/INT05_1/MAD16_0 P32/TIOB2_1/SOT3_1/INT10_1/MADATA09_ P18/AN08/SCK2_2/MAD15_0 QFP P33/ADTG_6/TIOB3_1/SCK3_1/INT04_0/MADATA10_ AVRH P34/TIOB4_1/FRCK0_0/MADATA11_ AVRL P35/TIOB5_1/IC03_0/INT08_1/MADATA12_ AVSS P36/SIN5_2/IC02_0/INT09_1/MADATA13_ AVCC P37/SOT5_2/IC01_0/INT05_2/MADATA14_ P17/AN07/SOT2_2/WKUP3/MAD14_0 P38/SCK5_2/IC00_0/INT06_2/MADATA15_ P16/AN06/SIN2_2/INT14_1/MAD13_0 P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2/MSDCLK_ P15/AN05/SCK0_1/MAD12_0 P3A/TIOA0_1/AIN0_0/RTO00_0/MSDCKE_ P14/AN04/SOT0_1/IC03_2/MAD11_0 P3B/TIOA1_1/BIN0_0/RTO01_0/MRASX_ P13/AN03/SIN0_1/IC02_2/INT03_1/MAD10_0 P3C/TIOA2_1/ZIN0_0/RTO02_0/MCASX_ P12/AN02/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1/MAD09_0 P3D/TIOA3_1/RTO03_0/MAD00_ P11/AN01/SOT1_1/IC00_2/MAD08_0 P3E/TIOA4_1/RTO04_0/MAD01_0 P3F/TIOA5_1/RTO05_0/MAD02_0 VSS VCC P40/TIOA0_0/RTO10_1/INT12_1 P41/TIOA1_0/RTO11_1/INT13_1 P42/TIOA2_0/RTO12_1/MSDWEX_0 P43/ADTG_7/TIOA3_0/RTO13_1/MCSX8_0 P44/TIOA4_0/RTO14_1/DA0 P45/TIOB0_0/RTO15_1/DA1 INITX P46/X0A P47/X1A P48/VREGCTL P49/VWAKEUP VBAT C VSS VCC P4B/TIOB1_0/SCS7_1/MAD03_0 P4C/TIOB2_0/SCK7_1/AIN1_2/MAD04_0 P4D/TIOB3_0/SOT7_1/BIN1_2/INT13_2/MAD05_0 P4E/TIOB4_0/SIN7_1/ZIN1_2/FRCK1_1/INT11_1/WKUP2/MAD06_0 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS VCC P10/AN00/SIN1_1/FRCK0_2/INT02_1/MAD07_ Note: The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: Rev.*B Page 12 of 168

13 LDC112 (TOP VIEW) A VSS TCK/ UDP0 UDM0 USBVCC VSS VSS AN21 P0A SWCLK P0B VSS P0E VSS B VCC VSS P60 P61 P62 TRSTX TMS/ SWDIO AN22 AN19 P0C P0D VSS VCC C P50 P51 P52 P63 TDI TDO/ SWO AN23 AN20 VSS AN18 AN17 D P53 P54 index AN16 AN15 E P55 P56 P30 AN14 AN13 AVRH F P31 P32 P33 AN12 AN11 AVRL G P34 P35 P36 AN10 AN09 AVSS H VSS P37 P38 AN08 AN07 AVCC J P39 P3A P3B AN06 AN05 AN04 K P3C P3D AN03 AN02 L P3E P3F P43 P45 P48 P4B P4C P4E VSS AN01 AN00 M VCC VSS P42 P44 VSS INITX P49 VCC P4D MD1 MD0 VSS VCC N VSS P40 P41 VSS X0A X1A VSS VBAT C VSS X0 X1 VSS Note: The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: Rev.*B Page 13 of 168

14 LDC144 (TOP VIEW) A VSS UDP0 UDM0 USBVCC VSS P66 VSS VSS AN21 VSS P0C VCC VSS B VCC VSS P60 P61 P63 P67 TCK/ SWCLK TDO/ SWO AN20 P0B VSS VSS P0E C P50 P51 VSS P62 P64 P68 TDI AN23 AN19 P0D VSS AN18 VSS D P52 P53 P54 VSS P65 TRSTX TMS/ SWDIO AN22 P0A VSS AN17 AN16 AN15 E P55 P56 P57 P58 index P24 P25 P26 P27 F P59 P5A P5B P30 P1F AN14 AN13 AN12 G P31 P32 P33 P34 AN11 AN10 AN09 AVRH H P35 P36 P37 P38 AN08 AN07 AN06 AVRL J P39 P3A P3B P3C AN05 AN04 AN03 AVSS K VSS P3D P3E VSS P45 P49 P4C P70 P72 VSS AN02 AN01 AVCC L P3F P41 VSS P44 VSS P48 P4B P4E P71 P74 VSS AN00 VSS M VCC VSS P43 VSS X1A VSS VSS P4D VCC P73 MD0 VSS VCC N VSS P40 P42 INITX X0A VSS VBAT C VSS MD1 X0 X1 VSS Note: The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: Rev.*B Page 14 of 168

15 4. Pin Description List of pin numbers The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin Pin No LQFP120 LQFP100 LQFP80 QFP100 BGA112 BGA144 Pin Name I/O circuit type B1 B1 VCC C1 C C2 C C3 D D1 D D2 D E1 E1 Pin type Document Number: Rev.*B Page 15 of 168 P50 CTS4_0 AIN0_2 RTO10_0 (PPG10_0) INT00_0 MADATA00_0 P51 RTS4_0 BIN0_2 RTO11_0 (PPG10_0) INT01_0 MADATA01_0 P52 SCK4_0 (SCL4_0) ZIN0_2 RTO12_0 (PPG12_0) MADATA02_0 P53 TIOA1_2 SOT4_0 (SDA4_0) RTO13_0 (PPG12_0) MADATA03_0 P54 TIOB1_2 SIN4_0 RTO14_0 (PPG14_0) INT02_0 MADATA04_0 P55 ADTG_1 SIN6_0 RTO15_0 (PPG14_0) INT07_2 MADATA05_0 E E E E E E K K I I K K

16 Pin No LQFP120 LQFP100 LQFP80 QFP100 BGA112 BGA144 Pin Name I/O circuit type Pin type P E2 E2 SOT6_0 (SDA6_0) DTTI1X_0 E K INT08_2 MADATA06_0 P E3 SCK6_0 (SCL6_0) E I MADATA07_0 P58 SIN4_ E4 AIN1_0 E K INT04_2 MADATA08_0 P F1 SOT4_2 (SDA4_2) BIN1_0 E K INT07_1 MADATA09_0 P5A F F E3 F4 SCK4_2 (SCL4_2) ZIN1_0 MADATA10_0 P5B CTS4_2 MADATA11_0 P30 TIOB0_1 RTS4_2 INT15_2 WKUP1 - - MADATA07_ F4 MADATA12_0 P F1 G1 TIOB1_1 SIN3_1 INT09_2 - - MADATA08_ G1 MADATA13_0 E E E I I I Q K Document Number: Rev.*B Page 16 of 168

17 Pin No LQFP120 LQFP100 LQFP80 QFP100 BGA112 BGA F2 G2 P32 Pin Name TIOB2_1 SOT3_1 (SDA3_1) INT10_1 - - MADATA09_ G2 MADATA14_0 P F3 G3 ADTG_6 TIOB3_1 SCK3_1 (SCL3_1) INT04_0 - - MADATA10_ G3 MADATA15_0 P34 18 G4 TIOB4_ G1 FRCK0_0 - - MADATA11_ G4 MNALE_0 P G2 H1 TIOB5_1 IC03_0 INT08_1 - - MADATA12_ H1 MNCLE_0 I/O circuit type N N E E K K I K Pin type Document Number: Rev.*B Page 17 of 168

18 Pin No LQFP120 LQFP100 LQFP80 QFP100 BGA112 BGA G3 H2 P36 SIN5_2 IC02_0 Pin Name INT09_1 - - MADATA13_ H2 MNWEX_0 P H2 H3 SOT5_2 (SDA5_2) IC01_0 INT05_2 - - MADATA14_ H3 MNREX_0 P H3 H4 SCK5_2 (SCL5_2) IC00_0 INT06_2 - - MADATA15_0 P J1 J1 ADTG_2 DTTI0X_0 RTCCO_2 SUBOUT_2 - MSDCLK_ J2 J2 P3A TIOA0_1 AIN0_0 RTO00_0 (PPG00_0) E E E L G I/O circuit type K K K I I Pin type - MSDCKE_0 P3B TIOA1_ J3 J3 BIN0_0 RTO01_0 (PPG00_0) G I - MRASX_0 Document Number: Rev.*B Page 18 of 168

19 Pin No LQFP120 LQFP100 LQFP80 QFP100 BGA112 BGA144 Pin Name I/O circuit type Pin type P3C TIOA2_ K1 J4 ZIN0_0 RTO02_0 (PPG02_0) G I - MCASX_ K2 K2 P3D TIOA3_1 RTO03_0 (PPG02_0) G I MAD00_0 P3E TIOA4_ L1 K3 RTO04_0 (PPG04_0) G I MAD01_0 P3F TIOA5_ L2 L1 RTO05_0 (PPG04_0) G I MAD02_ N1 N1 VSS M1 M1 VCC N2 N2 P40 TIOA0_0 RTO10_1 (PPG10_1) G K INT12_1 P41 TIOA1_ N3 L2 RTO11_1 (PPG10_1) G K INT13_1 P42 TIOA2_ M3 N3 RTO12_1 (PPG12_1) G I MSDWEX_0 P43 ADTG_ L3 M3 TIOA3_0 RTO13_1 (PPG12_1) G I MCSX8_0 Document Number: Rev.*B Page 19 of 168

20 Pin No LQFP120 LQFP100 LQFP80 QFP100 BGA112 BGA144 Pin Name I/O circuit type Pin type P44 TIOA4_ M4 L4 RTO14_1 (PPG14_1) R J DA0 P45 TIOB0_ L5 K5 RTO15_1 (PPG14_1) R J DA M6 N4 INITX B C N5 N5 P46 X0A P S N6 M5 P47 X1A Q T L6 L6 P48 VREGCTL O U M7 K6 P49 VWAKEUP O U N8 N7 VBAT N9 N8 C N10 N9 VSS M8 M9 VCC - - P4B L7 L7 TIOB1_0 SCS7_1 MAD03_0 E I P4C TIOB2_ L8 K7 SCK7_1 (SCL7_1) N I AIN1_2 MAD04_0 P4D TIOB3_ M9 M8 SOT7_1 (SDA7_1) N K BIN1_2 INT13_2 MAD05_0 P4E TIOB4_0 SIN7_ L9 L8 ZIN1_2 FRCK1_1 I Q INT11_1 WKUP2 MAD06_0 Document Number: Rev.*B Page 20 of 168

21 Pin No LQFP120 LQFP100 LQFP80 QFP100 BGA112 BGA144 Pin Name I/O circuit type Pin type P K8 TIOA4_2 AIN0_1 E I IC13_1 P71 TIOB4_ L9 BIN0_1 E K IC12_1 INT15_1 P72 TIOA6_ K9 SIN2_0 ZIN0_1 E K IC11_1 INT14_2 P73 TIOB6_ M10 SOT2_0 (SDA2_0) E K IC10_1 INT03_2 P L10 SCK2_0 (SCL2_0) E I DTTI1X_ M10 N10 PE0 MD1 C E M11 M11 MD0 J D N11 N11 PE2 X0 A A N12 N12 PE3 X1 A B N13 N13 VSS M13 M13 VCC - - P L13 L12 AN00 SIN1_1 FRCK0_2 INT02_1 MAD07_0 F M P11 AN L12 K12 SOT1_1 (SDA1_1) F L IC00_2 MAD08_0 Document Number: Rev.*B Page 21 of 168

22 Pin No LQFP120 LQFP100 LQFP80 QFP100 BGA112 BGA144 Pin Name I/O circuit type Pin type P12 AN K13 K11 SCK1_1 (SCL1_1) IC01_2 F L RTCCO_1 SUBOUT_1 MAD09_0 P13 AN K12 J12 SIN0_1 IC02_2 F M INT03_1 MAD10_0 P14 AN J13 J11 SOT0_1 (SDA0_1) F L IC03_2 MAD11_0 P15 AN J12 J10 SCK0_1 (SCL0_1) F L MAD12_0 P16 AN J11 H12 SIN2_2 F M INT14_1 MAD13_0 P17 AN H12 H11 SOT2_2 (SDA2_2) F P WKUP3 MAD14_ H13 K13 AVCC G13 J13 AVSS F13 H13 AVRL E13 G13 AVRH H11 H10 P18 AN08 SCK2_2 (SCL2_2) MAD15_0 F L Document Number: Rev.*B Page 22 of 168

23 Pin No LQFP120 LQFP100 LQFP80 QFP100 BGA112 BGA144 Pin Name I/O circuit type Pin type P19 AN G12 G12 SIN4_1 IC00_1 F M INT05_1 MAD16_0 P1A AN G11 G11 SOT4_1 (SDA4_1) M L IC01_1 MAD17_0 P1B AN F12 G10 SCK4_1 (SCL4_1) M L IC02_1 MAD18_0 P1C AN F11 F13 CTS4_1 F L IC03_1 MAD19_0 P1D AN E12 F12 RTS4_1 F L DTTI0X_1 MAD20_0 P1E AN E11 F11 ADTG_5 F L FRCK0_1 MAD21_0 P1F ADTG_ F10 TIOB6_2 E I RTO05_1 (PPG04_1) P27 TIOA6_ E13 RTO04_1 (PPG04_1) E K INT02_2 Document Number: Rev.*B Page 23 of 168

24 Pin No LQFP120 LQFP100 LQFP80 QFP100 BGA112 BGA E E E D13 D13 P26 TIOB5_0 SCK2_1 (SCL2_1) Pin Name RTO03_1 (PPG02_1) P25 TIOA5_0 SOT2_1 (SDA2_1) RTO02_1 (PPG02_1) P24 SIN2_1 RTO01_1 (PPG00_1) INT01_2 P23 AN15 TIOA7_1 SCK0_0 (SCL0_0) RTO00_1 (PPG00_1) - MAD22_ D12 D12 P22 CROUT_0 AN16 TIOB7_1 SOT0_0 (SDA0_0) - ZIN1_1 59 P21 AN17 SIN0_0 51 C13 D11 - BIN1_1 59 INT06_1 - MAD23_ C12 C12 P20 AN18 AIN1_1 INT05_0 MAD24_0 E E E F F F I/O circuit type A13 A13 VSS B13 A12 VCC - - F I I K L L M M Pin type Document Number: Rev.*B Page 24 of 168

25 Pin No LQFP120 LQFP100 LQFP80 QFP100 BGA112 BGA144 Pin Name I/O circuit type Pin type P0E TIOB5_ A12 B13 SCS6_1 IC13_0 L I S_CLK_0 MDQM1_0 P0D TIOA5_ B11 C10 SCK6_1 (SCL6_1) L I IC12_0 S_CMD_0 MDQM0_0 P0C TIOA6_ B10 A A10 B A9 D B9 C9 SOT6_1 (SDA6_1) IC11_0 S_DATA1_0 MALE_0 P0B TIOB6_1 SIN6_1 IC10_0 INT00_1 S_DATA0_0 MCSX0_0 P0A SIN1_0 FRCK1_0 INT12_2 S_DATA3_0 MCSX1_0 P09 AN19 - TRACED C9 B9 TIOA3_2 SOT1_0 (SDA1_0) S_DATA2_0 MCSX5_0 P08 AN20 TRACED1 TIOB3_2 SCK1_0 (SCL1_0) MCSX4_0 L L L M F I K K N N Document Number: Rev.*B Page 25 of 168

26 Pin No LQFP120 LQFP100 LQFP80 QFP100 BGA112 BGA144 Pin Name I/O circuit type Pin type P07 AN21 TRACED A8 A9 TIOA0_2 F N SCK7_0 (SCL7_0) MCLKOUT_0 P06 AN22 TRACED B8 D8 TIOB0_2 F N SOT7_0 (SDA7_0) C8 C C7 B B7 D C6 C A6 B B6 D6 MCSX3_0 P05 AN23 ADTG_0 TRACECLK SIN7_0 INT01_1 MCSX2_0 P04 TDO SWO P03 TMS SWDIO P02 TDI MCSX6_0 P01 TCK SWCLK P00 TRSTX MCSX7_ A5 A7 VSS C6 P68 TIOB7_2 SCK3_0 (SCL3_0) F E E E E E E O G G H G H K INT00_2 P B6 TIOA7_2 SOT3_0 (SDA3_0) E I Document Number: Rev.*B Page 26 of 168

27 Pin No LQFP120 LQFP100 LQFP80 QFP100 BGA112 BGA A D C C5 P66 ADTG_8 SIN3_0 INT11_2 P65 TIOB7_0 SCK5_1 (SCL5_1) P64 TIOA7_0 Pin Name SOT5_1 (SDA5_1) INT10_ SIN5_1 B5 INT03_ C B5 C B4 B B3 B3 P63 CROUT_1 S_CD_0 MWEX_0 P62 ADTG_3 SIN5_0 INT04_1 S_WP_0 MOEX_0 P61 UHCONX0 TIOB2_2 SOT5_0 (SDA5_0) RTCCO_0 SUBOUT_0 P60 TIOA2_2 SCK5_0 (SCL5_0) NMIX WKUP0 MRDY_0 E E E E I E I/O circuit type A4 A4 USBVCC A3 A A2 A2 P80 UDM0 P81 UDP0 I H H K I K K K I F R R Pin type Document Number: Rev.*B Page 27 of 168

28 Pin No LQFP120 LQFP100 LQFP80 QFP100 BGA112 BGA A1 A1 Pin Name I/O circuit type A7 A B2 A B12 A C11 B H1 B N4 B M5 C N7 C L11 C A11 D M12 D M2 K1 VSS K K L L L L M M M M M N6 - - Pin type Document Number: Rev.*B Page 28 of 168

29 List of pin functions The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin function ADC Base Timer 0 Base Timer 1 Base Timer 2 Pin No Pin name Function description LQFP LQFP LQFP QFP BGA BGA ADTG_ C8 C8 ADTG_ E1 E1 ADTG_ J1 J1 ADTG_ B5 C4 ADTG_4 A/D converter external trigger input pin F10 ADTG_ E11 F11 ADTG_ F3 G3 ADTG_ L3 M3 ADTG_ A6 AN L13 L12 AN L12 K12 AN K13 K11 AN K12 J12 AN J13 J11 AN J12 J10 AN J11 H12 AN H12 H11 AN H11 H10 AN G12 G12 AN G11 G11 AN11 A/D converter analog input pin F12 G10 AN12 ANxx describes ADC ch.xx F11 F13 AN E12 F12 AN E11 F11 AN D13 D13 AN D12 D12 AN C13 D11 AN C12 C12 AN B9 C9 AN C9 B9 AN A8 A9 AN B8 D8 AN C8 C8 TIOA0_ N2 N2 TIOA0_1 Base timer ch.0 TIOA pin J2 J2 TIOA0_ A8 A9 TIOB0_ L5 K5 TIOB0_1 Base timer ch.0 TIOB pin E3 F4 TIOB0_ B8 D8 TIOA1_ N3 L2 TIOA1_1 Base timer ch.1 TIOA pin J3 J3 TIOA1_ D1 D2 TIOB1_ L7 L7 TIOB1_1 Base timer ch.1 TIOB pin F1 G1 TIOB1_ D2 D3 TIOA2_ M3 N3 TIOA2_1 Base timer ch.2 TIOA pin K1 J4 TIOA2_ B3 B3 TIOB2_ L8 K7 TIOB2_1 Base timer ch.2 TIOB pin F2 G2 TIOB2_ B4 B4 Document Number: Rev.*B Page 29 of 168

30 Pin function Base Timer 3 Base Timer 4 Base Timer 5 Base Timer 6 Base Timer 7 Debugger Pin No Pin name Function description LQFP LQFP LQFP QFP BGA BGA TIOA3_ L3 M3 TIOA3_1 Base timer ch.3 TIOA pin K2 K2 TIOA3_ B9 C9 TIOB3_ M9 M8 TIOB3_1 Base timer ch.3 TIOB pin F3 G3 TIOB3_ C9 B9 TIOA4_ M4 L4 TIOA4_1 Base timer ch.4 TIOA pin L1 K3 TIOA4_ K8 TIOB4_ L9 L8 TIOB4_1 Base timer ch.4 TIOB pin G1 G4 TIOB4_ L9 TIOA5_ E11 TIOA5_1 Base timer ch.5 TIOA pin L2 L1 TIOA5_ B11 C10 TIOB5_ E12 TIOB5_1 Base timer ch.5 TIOB pin G2 H1 TIOB5_ A12 B13 TIOA6_ K9 TIOA6_1 Base timer ch.6 TIOA pin B10 A11 TIOA6_ E13 TIOB6_ M10 TIOB6_1 Base timer ch.6 TIOB pin A10 B10 TIOB6_ F10 TIOA7_ C5 TIOA7_1 Base timer ch.7 TIOA pin D13 D13 TIOA7_ B6 TIOB7_ D5 TIOB7_1 Base timer ch.7 TIOB pin D12 D12 TIOB7_ C6 SWCLK Serial wire debug interface clock input pin A6 B7 SWDIO Serial wire debug interface data input / output pin B7 D7 SWO Serial wire viewer output pin C7 B8 TCK JTAG test clock input pin A6 B7 TDI JTAG test data input pin C6 C7 TDO JTAG debug data output pin C7 B8 TMS JTAG test mode input/output pin B7 D7 TRACECLK Trace CLK output pin of ETM C8 C8 TRACED B9 C9 TRACED C9 B9 Trace data output pin of ETM TRACED A8 A9 TRACED B8 D8 TRSTX JTAG test reset Input pin B6 D6 Document Number: Rev.*B Page 30 of 168

31 Pin function External Bus Pin No Pin name Function description LQFP LQFP LQFP QFP BGA BGA MAD00_ K2 K2 MAD01_ L1 K3 MAD02_ L2 L1 MAD03_ L7 L7 MAD04_ L8 K7 MAD05_ M9 M8 MAD06_ L9 L8 MAD07_ L13 L12 MAD08_ L12 K12 MAD09_ K13 K11 MAD10_ K12 J12 MAD11_ J13 J11 MAD12_0 External bus interface address bus J12 J10 MAD13_ J11 H12 MAD14_ H12 H11 MAD15_ H11 H10 MAD16_ G12 G12 MAD17_ G11 G11 MAD18_ F12 G10 MAD19_ F11 F13 MAD20_ E12 F12 MAD21_ E11 F11 MAD22_ D13 D13 MAD23_ C13 D11 MAD24_ C12 C12 Document Number: Rev.*B Page 31 of 168

32 Pin function External Bus External Bus Pin No Pin name Function description LQFP LQFP LQFP QFP BGA BGA MCSX0_ A10 B10 MCSX1_ A9 D9 MCSX2_ C8 C8 MCSX3_ B8 D8 MCSX4_0 External bus interface chip select output pin C9 B9 MCSX5_ B9 C9 MCSX6_ C6 C7 MCSX7_ B6 D6 MCSX8_ L3 M3 MADATA00_ C1 C1 MADATA01_ C2 C2 MADATA02_ C3 D1 MADATA03_ D1 D2 MADATA04_ D2 D3 MADATA05_ E1 E1 MADATA06_ E2 E2 MADATA07_0 External bus interface data bus E3 E3 MADATA08_0 (Address / data multiplex bus) F1 E4 MADATA09_ F2 F1 MADATA10_ F3 F2 MADATA11_ G1 F3 MADATA12_ G2 F4 MADATA13_ G3 G1 MADATA14_ H2 G2 MADATA15_ H3 G3 MDQM0_0 External bus interface byte mask signal output B11 C10 MDQM1_0 pin A12 B13 MALE_0 External bus interface Address Latch enable output signal for multiplex B10 A11 MRDY_0 External bus interface external RDY input signal B3 B3 MCLKOUT_0 External bus interface external clock output pin A8 A9 MNALE_0 External bus interface ALE signal to control NAND Flash output pin G4 MNCLE_0 External bus interface CLE signal to control NAND Flash output pin H1 MNREX_0 External bus interface read enable signal to control NAND Flash H3 MNWEX_0 External bus interface write enable signal to control NAND Flash H2 MOEX_0 External bus interface read enable signal for SRAM B5 C4 MWEX_0 External bus interface write enable signal for SRAM C5 B5 MSDCLK_0 SDRAM interface SDRAM clock output pin J1 J1 MSDCKE_0 SDRAM interface SDRAM clock enable pin J2 J2 MRASX_0 SDRAM interface SDRAM row address strobe pin J3 J3 MCASX_0 SDRAM interface SDRAM column address strobe pin K1 J4 MSDWEX_0 SDRAM interface SDRAM write enable pin M3 N3 Document Number: Rev.*B Page 32 of 168

33 Pin function External Interrupt Pin No Pin name Function description LQFP LQFP LQFP QFP BGA BGA INT00_ C1 C1 INT00_1 External interrupt request 00 input pin A10 B10 INT00_ C6 INT01_ C2 C2 INT01_1 External interrupt request 01 input pin C8 C8 INT01_ E10 INT02_ D2 D3 INT02_1 External interrupt request 02 input pin L13 L12 INT02_ E13 INT03_ C5 B5 INT03_1 External interrupt request 03 input pin K12 J12 INT03_ M10 INT04_ F3 G3 INT04_1 External interrupt request 04 input pin B5 C4 INT04_ E4 INT05_ C12 C12 INT05_1 External interrupt request 05 input pin G12 G12 INT05_ H2 H3 INT06_ C13 D11 External interrupt request 06 input pin INT06_ H3 H4 INT07_ F1 External interrupt request 07 input pin INT07_ E1 E1 INT08_ G2 H1 External interrupt request 08 input pin INT08_ E2 E2 INT09_ G3 H2 External interrupt request 09 input pin INT09_ F1 G1 INT10_ F2 G2 External interrupt request 10 input pin INT10_ C5 INT11_ L9 L8 External interrupt request 11 input pin INT11_ A6 INT12_ N2 N2 External interrupt request 12 input pin INT12_ A9 D9 INT13_ N3 L2 External interrupt request 13 input pin INT13_ M9 M8 INT14_ J11 H12 External interrupt request 14 input pin INT14_ K9 INT15_ L9 External interrupt request 15 input pin INT15_ E3 F4 NMIX Non-Maskable Interrupt input pin B3 B3 Document Number: Rev.*B Page 33 of 168

34 Pin function GPIO Pin No Pin name Function description LQFP LQFP LQFP QFP BGA BGA P B6 D6 P A6 B7 P C6 C7 P B7 D7 P C7 B8 P C8 C8 P B8 D8 P07 General-purpose I/O port A8 A9 P C9 B9 P B9 C9 P0A A9 D9 P0B A10 B10 P0C B10 A11 P0D B11 C10 P0E A12 B13 P L13 L12 P L12 K12 P K13 K11 P K12 J12 P J13 J11 P J12 J10 P J11 H12 P H12 H11 General-purpose I/O port 1 P H11 H10 P G12 G12 P1A G11 G11 P1B F12 G10 P1C F11 F13 P1D E12 F12 P1E E11 F11 P1F F10 P C12 C12 P C13 D11 P D12 D12 P D13 D13 General-purpose I/O port 2 P E10 P E11 P E12 P E13 Document Number: Rev.*B Page 34 of 168

35 Pin function GPIO Pin No Pin name Function description LQFP LQFP LQFP QFP BGA BGA P E3 F4 P F1 G1 P F2 G2 P F3 G3 P G1 G4 P G2 H1 P G3 H2 P H2 H3 General-purpose I/O port 3 P H3 H4 P J1 J1 P3A J2 J2 P3B J3 J3 P3C K1 J4 P3D K2 K2 P3E L1 K3 P3F L2 L1 P N2 N2 P N3 L2 P M3 N3 P L3 M3 P M4 L4 P L5 K5 P N5 N5 General-purpose I/O port 4 P N6 M5 P L6 L6 P M7 K6 P4B L7 L7 P4C L8 K7 P4D M9 M8 P4E L9 L8 P C1 C1 P C2 C2 P C3 D1 P D1 D2 P D2 D3 P E1 E1 General-purpose I/O port 5 P E2 E2 P E3 P E4 P F1 P5A F2 P5B F3 Document Number: Rev.*B Page 35 of 168

36 Pin function GPIO Pin No Pin name Function description LQFP LQFP LQFP QFP BGA BGA P B3 B3 P B4 B4 P B5 C4 P C5 B5 P64 General-purpose I/O port C5 P D5 P A6 P B6 P C6 P K8 P L9 P72 General-purpose I/O port K9 P M10 P L10 P A3 A3 General-purpose I/O port 8 P A2 A2 PE M10 N10 PE2 General-purpose I/O port E N11 N11 PE N12 N12 SIN0_ C13 D11 Multi-function serial interface ch.0 input pin SIN0_ K12 J12 Multi- function Serial 0 SOT0_0 (SDA0_0) SOT0_1 (SDA0_1) Multi-function serial interface ch.0 output pin. This pin operates as SOT0 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA0 when it is used in an I 2 C (operation mode 4) D12 D J13 J11 SCK0_0 (SCL0_0) SCK0_1 (SCL0_1) Multi-function serial interface ch.0 clock I/O pin. This pin operates as SCK0 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SCL0 when it is used in an I 2 C (operation mode 4) D13 D J12 J10 SIN1_ A9 D9 Multi-function serial interface ch.1 input pin SIN1_ L13 L12 Multi- function Serial 1 SOT1_0 (SDA1_0) SOT1_1 (SDA1_1) Multi-function serial interface ch.1 output pin. This pin operates as SOT1 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA1 when it is used in an I 2 C (operation mode 4) B9 C L12 K12 SCK1_0 (SCL1_0) SCK1_1 (SCL1_1) Multi-function serial interface ch.1 clock I/O pin. This pin operates as SCK1 when it is used in a CSIO (operation modes 4) and as SCL1 when it is used in an I 2 C (operation mode 4) C9 B K13 K11 Document Number: Rev.*B Page 36 of 168

37 Pin function Multi- function Serial 2 Pin No Pin name Function description LQFP LQFP LQFP QFP BGA BGA SIN2_ K9 SIN2_1 Multi-function serial interface ch.2 input pin E10 SIN2_ J11 H12 SOT2_0 Multi-function serial interface ch.2 output pin M10 (SDA2_0) This pin operates as SOT2 when it is used in a SOT2_1 UART/CSIO/LIN (operation modes 0 to 3) and as E11 (SDA2_1) SDA2 when it is used in an I 2 C (operation mode SOT2_2 4) H12 H11 (SDA2_2) SCK2_0 (SCL2_0) Multi-function serial interface ch.2 clock I/O pin L10 SCK2_1 This pin operates as SCK2 when it is used in a (SCL2_1) CSIO (operation modes 2) and as SCL2 when it E12 SCK2_2 is used in an I 2 C (operation mode 4). (SCL2_2) H11 H10 SIN3_ A6 Multi-function serial interface ch.3 input pin SIN3_ F1 G1 Multi- function Serial 3 SOT3_0 (SDA3_0) SOT3_1 (SDA3_1) Multi-function serial interface ch.3 output pin. This pin operates as SOT3 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA3 when it is used in an I 2 C (operation mode 4) B F2 G2 SCK3_0 (SCL3_0) SCK3_1 (SCL3_1) Multi-function serial interface ch.3 clock I/O pin. This pin operates as SCK3 when it is used in a CSIO (operation modes 2) and as SCL3 when it is used in an I 2 C (operation mode 4) C F3 G3 Multi- function Serial 4 SIN4_ D2 D3 SIN4_1 Multi-function serial interface ch.4 input pin G12 G12 SIN4_ E4 SOT4_0 Multi-function serial interface ch.4 output pin D1 D2 (SDA4_0) This pin operates as SOT4 when it is used in a SOT4_1 UART/CSIO/LIN (operation modes 0 to 3) and as G11 G11 (SDA4_1) SDA4 when it is used in an I 2 C (operation mode SOT4_2 4) F1 (SDA4_2) SCK4_0 (SCL4_0) Multi-function serial interface ch.4 clock I/O pin C3 D1 SCK4_1 This pin operates as SCK4 when it is used in a (SCL4_1) CSIO (operation modes 2) and as SCL4 when it F12 G10 SCK4_2 is used in an I 2 C (operation mode 4). (SCL4_2) F2 CTS4_ C1 C1 CTS4_1 Multi-function serial interface ch.4 CTS input pin F11 F13 CTS4_ F3 RTS4_ C2 C2 RTS4_1 Multi-function serial interface ch.4 RTS output pin E12 F12 RTS4_ E3 F4 Document Number: Rev.*B Page 37 of 168

38 Pin function Multi- function Serial 5 Pin No Pin name Function description LQFP LQFP LQFP QFP BGA BGA SIN5_ B5 C4 SIN5_1 Multi-function serial interface ch.5 input pin B5 SIN5_ G3 H2 SOT5_0 Multi-function serial interface ch.5 output pin B4 B4 (SDA5_0) This pin operates as SOT5 when it is used in a SOT5_1 UART/CSIO/LIN (operation modes 0 to 3) and as C5 (SDA5_1) SDA5 when it is used in an I 2 C (operation mode SOT5_2 4) H2 H3 (SDA5_2) SCK5_0 (SCL5_0) Multi-function serial interface ch.5 clock I/O pin B3 B3 SCK5_1 This pin operates as SCK5 when it is used in a (SCL5_1) CSIO (operation modes 2) and as SCL5 when it D5 SCK5_2 is used in an I 2 C (operation mode 4). (SCL5_2) H3 H4 SIN6_ E1 E1 Multi-function serial interface ch.6 input pin SIN6_ A10 B10 Multi- function Serial 6 SOT6_0 (SDA6_0) SOT6_1 (SDA6_1) SCK6_0 (SCL6_0) SCK6_1 (SCL6_1) Multi-function serial interface ch.6 output pin. This pin operates as SOT6 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA6 when it is used in an I 2 C (operation mode 4). Multi-function serial interface ch.6 clock I/O pin. This pin operates as SCK6 when it is used in a CSIO (operation modes 2) and as SCL6 when it is used in an I 2 C (operation mode 4) E2 E B10 A E B11 C10 SCS6_1 Multi-function serial interface ch.6 serial chip select pin A12 B13 SIN7_ C8 C8 Multi-function serial interface ch.7 input pin SIN7_ L9 L8 Multi- function Serial 7 SOT7_0 (SDA7_0) SOT7_1 (SDA7_1) SCK7_0 (SCL7_0) SCK7_1 (SCL7_1) Multi-function serial interface ch.7 output pin. This pin operates as SOT7 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA7 when it is used in an I 2 C (operation mode 4). Multi-function serial interface ch.7 clock I/O pin. This pin operates as SCK7 when it is used in a CSIO (operation modes 2) and as SCL7 when it is used in an I 2 C (operation mode 4) B8 D M9 M A8 A L8 K7 SCS7_1 Multi-function serial interface ch.7 serial chip select pin L7 L7 Document Number: Rev.*B Page 38 of 168

39 Pin function Multifunction Timer 0 Pin name Function description LQFP 120 LQFP 100 Pin No LQFP QFP DTTI0X_0 Input signal controlling wave form generator J1 J1 outputs RTO00 to RTO05 of Multi-function timer DTTI0X_ E12 F12 FRCK0_ G1 G4 FRCK0_1 16-bit free-run timer ch.0 external clock input pin E11 F11 FRCK0_ L13 L12 IC00_ H3 H4 IC00_ G12 G12 IC00_ L12 K12 IC01_ H2 H3 IC01_ G11 G11 16-bit input capture ch.0 input pin of Multifunction timer 0. IC01_ K13 K11 IC02_ G3 H2 ICxx describes channel number. IC02_ F12 G10 IC02_ K12 J12 IC03_ G2 H1 IC03_ F11 F13 IC03_ J13 J11 RTO00_0 Wave form generator output pin of Multi-function (PPG00_0) timer J2 J2 RTO00_1 This pin operates as PPG00 when it is used in (PPG00_1) PPG0 output modes D13 D13 RTO01_0 Wave form generator output pin of Multi-function (PPG00_0) timer J3 J3 RTO01_1 This pin operates as PPG00 when it is used in (PPG00_1) PPG0 output modes E10 RTO02_0 Wave form generator output pin of Multi-function (PPG02_0) timer K1 J4 RTO02_1 This pin operates as PPG02 when it is used in (PPG02_1) PPG0 output modes E11 RTO03_0 Wave form generator output pin of Multi-function (PPG02_0) timer K2 K2 RTO03_1 This pin operates as PPG02 when it is used in (PPG02_1) PPG0 output modes E12 RTO04_0 Wave form generator output pin of Multi-function (PPG04_0) timer L1 K3 RTO04_1 This pin operates as PPG04 when it is used in (PPG04_1) PPG0 output modes E13 RTO05_0 Wave form generator output pin of Multi-function (PPG04_0) timer L2 L1 RTO05_1 This pin operates as PPG04 when it is used in (PPG04_1) PPG0 output modes F10 BGA 112 BGA 144 Document Number: Rev.*B Page 39 of 168

40 Pin function Multifunction Timer 1 Quadrature Position/ Revolution Counter 0 Quadrature Position/ Revolution Counter 1 Pin name Function description LQFP 120 LQFP 100 Pin No LQFP QFP DTTI1X_0 Input signal controlling wave form generator E2 E2 outputs RTO10 to RTO15 of Multi-function timer DTTI1X_ L10 FRCK1_ A9 D9 16-bit free-run timer ch.1 external clock input pin FRCK1_ L9 L8 IC10_ A10 B10 IC10_ M10 IC11_ B10 A11 16-bit input capture ch.1 input pin of Multifunction timer 1. IC11_ K9 IC12_ B11 C10 ICxx describes channel number. IC12_ L9 IC13_ A12 B13 IC13_ K8 RTO10_0 Wave form generator output pin of Multi-function (PPG10_0) timer C1 C1 RTO10_1 This pin operates as PPG10 when it is used in (PPG10_1) PPG1 output modes N2 N2 RTO11_0 Wave form generator output pin of Multi-function (PPG10_0) timer C2 C2 RTO11_1 This pin operates as PPG10 when it is used in (PPG10_1) PPG1 output modes N3 L2 RTO12_0 Wave form generator output pin of Multi-function (PPG12_0) timer C3 D1 RTO12_1 This pin operates as PPG12 when it is used in (PPG12_1) PPG1 output modes M3 N3 RTO13_0 Wave form generator output pin of Multi-function (PPG12_0) timer D1 D2 RTO13_1 This pin operates as PPG12 when it is used in (PPG12_1) PPG1 output modes L3 M3 RTO14_0 Wave form generator output pin of Multi-function (PPG14_0) timer D2 D3 RTO14_1 This pin operates as PPG14 when it is used in (PPG14_1) PPG1 output modes M4 L4 RTO15_0 Wave form generator output pin of Multi-function (PPG14_0) timer E1 E1 RTO15_1 This pin operates as PPG14 when it is used in (PPG14_1) PPG1 output modes L5 K5 AIN0_ J2 J2 AIN0_1 QPRC ch.0 AIN input pin K8 AIN0_ C1 C1 BIN0_ J3 J3 BIN0_1 QPRC ch.0 BIN input pin L9 BIN0_ C2 C2 ZIN0_ K1 J4 ZIN0_1 QPRC ch.0 ZIN input pin K9 ZIN0_ C3 D1 AIN1_ E4 AIN1_1 QPRC ch.1 AIN input pin C12 C12 AIN1_ L8 K7 BIN1_ F1 BIN1_1 QPRC ch.1 BIN input pin C13 D11 BIN1_ M9 M8 ZIN1_ F2 ZIN1_1 QPRC ch.1 ZIN input pin D12 D12 ZIN1_ L9 L8 BGA 112 BGA 144 Document Number: Rev.*B Page 40 of 168

41 Pin function Real-time clock USB Low-Power Consumption Mode DAC VBAT SD I/F Reset Mode Power Pin No Pin name Function description LQFP LQFP LQFP QFP BGA BGA RTCCO_ B4 B4 RTCCO_1 0.5 seconds pulse output pin of Real-time clock K13 K11 RTCCO_ J1 J1 SUBOUT_ B4 B4 SUBOUT_1 Sub clock output pin K13 K11 SUBOUT_ J1 J1 UDM0 USB device/host D pin A3 A3 UDP0 USB device/host D + pin A2 A2 UHCONX0 USB external pull-up control pin B4 B4 WKUP0 Deep standby mode return signal input pin B3 B3 WKUP1 Deep standby mode return signal input pin E3 F4 WKUP2 Deep standby mode return signal input pin L9 L8 WKUP3 Deep standby mode return signal input pin H12 H11 DA0 D/A converter ch.0 analog output pin M4 L4 DA1 D/A converter ch.1 analog output pin L5 K5 VREGCTL On-board regulator control pin L6 L6 VWAKEUP The return signal input pin from a hibernation M7 K6 S_CLK_0 SD memory card interface SD memory card clock output pin A12 B13 S_CMD_0 SD memory card interface SD memory card command output B11 C10 S_DATA1_ B10 A11 S_DATA0_0 SD memory card interface A10 B10 S_DATA3_0 SD memory card data bus A9 D9 S_DATA2_ B9 C9 S_CD_0 SD memory card interface SD memory card detection pin C5 B5 S_WP_0 SD memory card interface SD memory card write protection B5 C4 INITX External Reset Input pin. A reset is valid when INITX="L" M6 N4 Mode 1 pin. MD1 During serial programming to Flash memory, M10 N10 MD1="L" must be input. Mode 0 pin. MD0 During normal operation, MD0="L" must be input. During serial programming to Flash memory, M11 M11 MD0="H" must be input B1 B M1 M1 VCC Power supply Pin M8 M M13 M B13 A12 USBVCC 3.3V Power supply port for USB I/O A4 A4 Document Number: Rev.*B Page 41 of 168

42 Pin No Pin Pin name Function description function LQFP LQFP LQFP QFP BGA BGA A5 A N1 N N10 N N13 N A13 A A1 A A7 A B2 A B12 A C11 B H1 B N4 B12 GND VSS GND Pin M5 C N7 C L11 C A11 D M12 D M2 K K K L L L L M M M6 GND VSS GND Pin M M N6 X0 Main clock (oscillation) input pin N11 N11 X1 Main clock (oscillation) I/O pin N12 N12 Clock X0A Sub clock (oscillation) input pin N5 N5 X1A Sub clock (oscillation) I/O pin N6 M5 CROUT_ D12 D12 Built-in high-speed CR-osc clock output port CROUT_ C5 B5 A/D converter and D/A converter AVCC ADC analog power supply pin H13 K13 Power AVRL A/D converter analog reference voltage input pin F13 H13 AVRH A/D converter analog reference voltage input pin E13 G13 VBAT power supply pin. VBAT VBAT Backup power supply (battery etc.) and system Power power supply N8 N7 ADC A/D converter and D/A converter AVSS GND GND pin G13 J13 C pin C Power supply stabilization capacity pin N9 N8 Note: While this device contains a Test Access Port (TAP) based on the IEEE JTAG standard, it is not fully compliant to all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP controller. Document Number: Rev.*B Page 42 of 168

43 5. I/O Circuit Type Type Circuit Remarks A It is possible to select the main oscillation / GPIO function Pull-up X1 P-ch resistor P-ch Digital output When the main oscillation is selected. Oscillation feedback resistor : Approximately 1MΩ With Standby mode control When the GPIO is selected. R N-ch Digital output Pull-up resistor control Digital input CMOS level output. CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50kΩ IOH = -4mA, IOL = 4mA Standby mode control Feedback resistor Clock input Standby mode control Digital input R Pull-up resistor Standby mode control X0 P-ch P-ch Digital output N-ch Digital output Pull-up resistor control B Pull-up resistor CMOS level hysteresis input Pull-up resistor : Approximately 50kΩ Digital input Document Number: Rev.*B Page 43 of 168

44 Type Circuit Remarks C Open drain output Digital input CMOS level hysteresis input N-ch Digital output E P-ch P-ch Digital output CMOS level output CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50kΩ IOH = -4mA, IOL = 4mA R N-ch Digital output Pull-up resistor control Digital input Standby mode control F P-ch P-ch Digital output CMOS level output CMOS level hysteresis input With input control Analog input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50kΩ IOH = -4mA, IOL = 4mA N-ch Digital output R Pull-up resistor control Digital input Standby mode control Analog input Input control Document Number: Rev.*B Page 44 of 168

45 Type Circuit Remarks G CMOS level output CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50kΩ P-ch P-ch Digital output IOH = -12mA, IOL = 12mA R N-ch Digital output Pull-up resistor control Digital input Standby mode control H It is possible to select the USB I/O / GPIO function. UDP/Pxx GPIO Digital output GPIO Digital input/output direction GPIO Digital input GPIO Digital input circuit control UDP output USB Full-speed/Low-speed control UDP input When the USB I/O is selected. Full-speed, Low-speed control When the GPIO is selected. CMOS level output CMOS level hysteresis input With standby mode control IOH = -20.5mA, IOL = 18.5mA UDM/Pxx Differential Differential input USB/GPIO select UDM input UDM output USB Digital input/output direction GPIO Digital output GPIO Digital input/output direction GPIO Digital input GPIO Digital input circuit control Document Number: Rev.*B Page 45 of 168

46 Type Circuit Remarks I CMOS level output CMOS level hysteresis input 5V tolerant With standby mode control Pull-up resistor P-ch P-ch Digital output : Approximately 50kΩ IOH = -4mA, IOL = 4mA Available to control of PZR registers. R N-ch Digital output Pull-up resistor control Digital input Standby mode control J CMOS level hysteresis input Mode input L P-ch P-ch Digital output CMOS level output CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50kΩ IOH = -8mA, IOL = 8mA N-ch Digital output R Pull-up resistor control Digital input Standby mode control Document Number: Rev.*B Page 46 of 168

47 Type Circuit Remarks M CMOS level output CMOS level hysteresis input With input control Analog input With pull-up resistor control With standby mode control P-ch P-ch Digital output Pull-up resistor : Approximately 50kΩ IOH = -8mA, IOL = 8mA N-ch Digital output R Pull-up resistor control Digital input Standby mode control Analog input Input control N P-ch R N-ch P-ch N-ch Pull-up resistor control Digital output Digital output Fast mode control CMOS level output CMOS level hysteresis input 5V tolerant Pull-up resistor control Standby mode control Pull-up resistor: approximately 50 kω IOH = -4 ma, IOL = 4 ma (GPIO) IOL = 20mA (Fast mode Plus) Available to control of PZR register (pseudo-open drain control) For PZR registers, refer to GPIO in the FM4 Family Peripheral Manual Main Part ( ). When this pin is used as an I 2 C pin, the digital output P-ch transistor is always off. Digital input Standby mode control Document Number: Rev.*B Page 47 of 168

48 Type Circuit Remarks O CMOS level output CMOS level hysteresis input 5 V tolerant P-ch R P-ch N-ch Pull-up resistor control Digital output Digital output Digital input Pull-up resistor control Pull-up resistor: approximately 50 kω IOH = -4 ma, IOL = 4 ma Available to control of PZR register (pseudo-open drain control) For PZR registers, refer to GPIO in the FM4 Family Peripheral Manual Main Part (MN ). For I/O setting, refer to VBAT Domain in the FM4 Family Peripheral Manual Main Part ( ). P X0A P-ch P-ch Pull-up resistor control Digital output CMOS level output CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50kΩ IOH = -4mA, IOL = 4mA For I/O setting, refer to VBAT Domain in the Peripheral Manual N-ch Digital output R Digital input Standby mode control OSC Document Number: Rev.*B Page 48 of 168

49 Type Circuit Remarks Q It is possible to select the sub oscillation / GPIO function X1A P-ch P-ch Pull-up resistor control Digital output When the sub oscillation is selected. Oscillation feedback resistor : Approximately 10MΩ With Standby mode control R N-ch Digital output Digital input Standby mode control OSC When the GPIO is selected. CMOS level output. CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50kΩ IOH = -4mA, IOL = 4mA For I/O setting, refer to VBAT Domain in the Peripheral Manual RX Standby mode control Clock input R P-ch P-ch N-ch Pull-up resistor control Digital output Digital output CMOS level output CMOS level hysteresis input Analog output With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50kΩ IOH = -12mA, IOL = 12mA (4.5V to 5.5V) IOH = -8mA, IOL = 8mA (2.7V to 4.5V) R Digital input Standby mode control Analog output Document Number: Rev.*B Page 49 of 168

50 6. Handling Precautions Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices. 6.1 Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices. Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. 1. Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. 2. Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. 3. Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin. Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred ma to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: 1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. 2. Be sure that abnormal current flows do not occur during the power-on sequence. Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Document Number: Rev.*B Page 50 of 168

51 Precautions Related to Usage of Devices Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 6.2 Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Cypress's recommended conditions. For detailed information about mount conditions, contact your sales representative. Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended conditions. Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: 1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. 2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5 C and 30 C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. 3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. 4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust. Document Number: Rev.*B Page 51 of 168

52 Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended conditions for baking. Condition: 125 C/24 h Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: 1. relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. 2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. 3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. 4. Ground all fixtures and instruments, or protect with anti-static measures. 5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies. 6.3 Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: 1. Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. 2. Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. 3. Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. 4. Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. 5. Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Cypress products in other special environmental conditions should consult with sales representatives. Document Number: Rev.*B Page 52 of 168

53 7. Handling Devices Power supply pins In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with each POWER pins and GND pins of this device at low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µf be connected as a bypass capacitor between VCC and VSS near this device. Power supply pins A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed operating range of the VCC power supply voltage. As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient fluctuation rate does not exceed 0.1 V/μs at a momentary fluctuation such as switching the power supply. Crystal oscillator circuit Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1, X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by ground plane as this is expected to produce stable operation. Evaluate oscillation of your using crystal oscillator by your mount board. Sub crystal oscillator This series sub oscillator circuit is low gain to keep the low current consumption. The crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation. Surface mount type Size: Load capacitance: Lead type Load capacitance: More than 3.2 mm 1.5 mm Approximately 6 pf to 7 pf Approximately 6 pf to 7 pf Using an external clock When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1(PE3) can be used as a general-purpose I/O port. Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input, and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port. Example of Using an External Clock Device Can be used as general-purpose I/O ports. X0(X0A) X1(PE3), X1A (P47) Set as External clock input Document Number: Rev.*B Page 53 of 168

54 Handling when using Multi-function serial pin as I 2 C pin If it is using the multi-function serial pin as I 2 C pins, P-ch transistor of digital output is always disabled. However, I 2 C pins need to keep the electrical characteristic like other pins and not to connect to the external I 2 C bus system with power OFF. C Pin This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. A smoothing capacitor of about 4.7 μf would be recommended for this series. Device C VSS CS GND Mode pins (MD0) Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is because of preventing the device erroneously switching to test mode due to noise. Notes on power-on Turn power on/off in the following order or at the same time. The device operates normally after all power on. VBAT only Power-on is possible when VBAT and VCC turns Power-on and Hibernation control is setting and then VCC turns Power-off. About Hibernation control, see Chapter 7-2: VBAT Domain(A) in FM4 Family Peripheral Manual Main Part( ). If not using the A/D converter and D/A converter, connect AVCC = VCC and AVSS = VSS. Turning on : VBAT VCC USBVCC VCC AVCC AVRH Turning off : AVRH AVCC VCC USBVCC VCC VBAT Serial Communication There is a possibility to receive wrong data due to the noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. If an error is detected, retransmit the data. Differences in features among the products with different memory sizes and between Flash products and MASK products The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between Flash products and MASK products are different because chip layout and memory structures are different. If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics. Document Number: Rev.*B Page 54 of 168

55 Pull-Up function of 5V tolerant I/O Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5V tolerant I/O. Adjoining wiring on circuit board If wiring of the crystal oscillation circuit X1A adjoins and also runs in parallel with the wiring of P48/VREGCTL, there is a possibility that the oscillation erroneously counts because X1A has noise with the change of P48/VREGCTL. Keep as much distance as possible between both wirings and insert the ground pattern between them in order to avoid this possibility. P46/ X0A P47/ X1A Device P48/ VREGCTL P49/ VWAKEUP Not allowed to run both wirings in parallel Ground Insert the ground pattern Handling when using debug pins When debug pins(tdo/tms/tdi/tck/trstx or SWO/SWDIO/SWCLK) are set to GPIO or other peripheral functions, only set them as output, do not set them as input. Document Number: Rev.*B Page 55 of 168

56 AHB-APB Bridge : APB1 (Max 160 MHz) AHB-APB Bridge : APB2 (Max 80 MHz) AHB-AHB Bridge AHB-APB Bridge: APB0(Max 80 MHz) Multi-layer AHB (Max 160 MHz) MB9B360R Series 8. Block Diagram MB9BF366M/N/R, F367M/N/R, F368M/N/R TRSTX,TCK, TDI,TMS TDO TRACEDx, TRACECLK INITX SWJ-DP TPIU* Cortex-M4 MHz(Max) FPU MPU Dual-Timer NVIC Watchdog Timer (Software) Clock Reset Generator Watchdog Timer (Hardware) ETM* ROM Table I D Sys MainFlash I/F Trace Buffer (16 Kbytes) Security WorkFlash I/F SRAM0 32/48/64 Kbytes SRAM1 16/24/32 Kbytes SRAM2 16/24/32 Kbytes MainFlash 1 Mbytes/ 768 Kbytes/ 512 Kbytes WorkFlash 32 Kbytes USB2.0 (Host/ Func) PHY USBVCC UDP0,UDM0 UHCONX0 CLK CSV DMAC 8ch. DSTC SD-CARD I/F S_CLK,S_CMD S_DATAx S_CD,S_WP Source Clock X0 X1 X0A X1A CROUT Main Osc VBAT Domain Sub Osc PLL CR 100 khz CR 4 MHz GPIO PIN-Function-Ctrl P0x, P1x,... PEx MADx AVCC, AVSS, AVRH ANxx ADTGx 12-bit A/D Converter Unit 0 Unit 1 Unit 2 External Bus I/F USB Clock Ctrl LVD Ctrl PLL Power-On Reset LVD MADATAx MCSXx,MDQMx, MOEX,MWEX, MALE,MRDY, MNALE,MNCLE, MNWEX,MNREX, MCLKOUT,MSDWEX, MSDCLK,MSDCKE, MRASX,MCASX TIOAx TIOBx Base Timer 16-bit 16ch./ 32-bit 8ch. IRQ-Monitor CRC Accelerator Regulator C AINx BINx ZINx QPRC 2ch. Watch Counter Deep Standby Ctrl WKUPx IC0x A/D Activation Compare 6ch. 16-bit Input Capture 4ch. Peripheral Clock Gating Low-speed CR Prescaler VBAT Domain Real-Time Clock Port Ctrl. VWAKEUP VREGCTL RTCCO, SUBOUT FRCK0 DTTI0X RTO0x 16-bit Free-run Timer 3ch. 16-bit Output Compare 6ch. Waveform Generator 3ch. 16-bit PPG 3ch. Multi-function Timer 2 External Interrupt Controller 16pin + NMI MODE-Ctrl Multi-function Serial I/F 8ch. HW flow control(ch.4) 12-bit D/A Converter 2units INTx NMIX MD0, MD1 SCKx SINx SOTx CTS4 RTS4 DAx *: For the MB9BF366M, MB9BF367M and MB9BF368M, ETM is not available. Document Number: Rev.*B Page 56 of 168

57 9. Memory Size See "Memory size" in "Product Lineup" to confirm the memory size. 10. Memory Map Memory Map (1) 0x41FF_FFFF 0x4007_0000 0x4006_F000 0x4006_E000 Peripherals Area Reserved GPIO SD-Card I/F See " Memory Map (2)" for the memory size details. 0xFFFF_FFFF Reserved Reserved 0x4006_2000 0xE010_0000 0x4006_1000 DSTC Cortex-M4 Private 0x4006_0000 DMAC 0xE000_0000 Peripherals 0x4005_0000 0x4004_0000 Reserved USB ch.0 0x4003_F000 EXT-bus I/F External Device Area 0x4003_C800 0x4003_C100 Reserved Peripheral Clock Gating 0x4003_C000 Low Speed CR Prescaler 0x6000_0000 0x4003_B000 RTC/Port Ctrl 0x4003_A000 Watch Counter Reserved 0x4003_9000 CRC 0x4400_0000 0x4003_8000 MFS 32 Mbytes 0x4003_7000 Reserved 0x4200_0000 Bit band alias 0x4003_6000 USB Clock ctrl 0x4003_5000 LVD/DS mode Peripherals 0x4003_4000 Reserved 0x4000_0000 0x4003_3000 D/AC 0x4003_2000 Reserved Reserved 0x4003_1000 Int-Req.Read 0x2400_0000 0x4003_0000 EXTI 32 Mbytes 0x4002_F000 Reserved 0x2200_0000 Bit band alias 0x4002_E000 CR Trim Reserved 0x4002_8000 Reserved 0x2010_0000 0x4002_7000 A/DC 0x200E_0000 WorkFlash I/F 0x4002_6000 QPRC 0x200C_0000 WorkFlash 0x4002_5000 Base Timer 0x4002_4000 PPG Reserved 0x2004_8000 Reserved 0x2004_0000 SRAM2 0x4002_2000 0x2003_8000 SRAM1 0x4002_1000 MFT Unit1 0x2000_0000 Reserved 0x4002_0000 MFT Unit0 0x1FFF_0000 SRAM0 0x0050_0000 Reserved 0x4001_6000 Reserved 0x0040_0000 Security/CR Trim 0x4001_5000 Dual Timer MainFlash 0x4001_3000 Reserved 0x4001_2000 SW WDT 0x0000_0000 0x4001_1000 HW WDT 0x4001_0000 Clock/Reset 0x4000_1000 0x4000_0000 Reserved MainFlash I/F Document Number: Rev.*B Page 57 of 168

58 Memory Map (2) MB9BF368M/N/R MB9BF367M/N/R MB9BF366M/N/R 0x2008_0000 0x2008_0000 0x2008_0000 Reserved Reserved 0x200C_8000 0x200C_8000 0x200C_8000 WorkFlash WorkFlash 0x200C_ Kbytes 0x200C_ Kbytes 0x200C_0000 0x2004_8000 0x2004_6000 SRAM2 0x2004_4000 SRAM2 32 Kbytes 24 Kbytes 0x2004_0000 0x2004_0000 0x2004_0000 0x2003_8000 0x2003_A000 0x2003_C000 0x2000_0000 0x2000_0000 0x2000_0000 0x1FFF_0000 Reserved SRAM1 32 Kbytes Reserved SRAM0 64 Kbytes Reserved 0x1FFF_4000 Reserved SRAM1 24 Kbytes Reserved SRAM0 48 Kbytes Reserved 0x1FFF_8000 Reserved WorkFlash 32 Kbytes Reserved SRAM2 16 Kbytes SRAM1 16 Kbytes Reserved SRAM0 32 Kbytes Reserved 0x0050_0000 0x0050_0000 0x0050_0000 0x0040_2000 CR trimming 0x0040_2000 CR trimming 0x0040_2000 CR trimming 0x0040_0000 Security 0x0040_0000 Security 0x0040_0000 Security Reserved 0x0010_0000 Reserved Reserved 0x000C_0000 MainFlash 1 Mbytes MainFlash 768 Kbytes 0x0008_0000 MainFlash 512 Kbytes 0x0000_0000 0x0000_0000 0x0000_0000 Document Number: Rev.*B Page 58 of 168

59 Peripheral Address Map Start address End address Bus Peripherals 0x4000_0000 0x4000_0FFF MainFlash I/F register AHB 0x4000_1000 0x4000_FFFF Reserved 0x4001_0000 0x4001_0FFF Clock/Reset Control 0x4001_1000 0x4001_1FFF Hardware Watchdog timer 0x4001_2000 0x4001_2FFF Software Watchdog timer APB0 0x4001_3000 0x4001_4FFF Reserved 0x4001_5000 0x4001_5FFF Dual-Timer 0x4001_6000 0x4001_FFFF Reserved 0x4002_0000 0x4002_0FFF Multi-function timer unit0 0x4002_1000 0x4002_1FFF Multi-function timer unit1 0x4002_2000 0x4003_FFFF Reserved 0x4002_4000 0x4002_4FFF PPG 0x4002_5000 0x4002_5FFF Base Timer APB1 0x4002_6000 0x4002_6FFF Quadrature Position/Revolution Counter 0x4002_7000 0x4002_7FFF A/D Converter 0x4002_8000 0x4002_DFFF Reserved 0x4002_E000 0x4002_EFFF CR trimming 0x4002_F000 0x4002_FFFF Reserved 0x4003_0000 0x4003_0FFF External Interrupt Controller 0x4003_1000 0x4003_1FFF Interrupt Request Batch-Read Function 0x4003_2000 0x4003_4FFF Reserved 0x4003_3000 0x4003_3FFF D/A Converter 0x4003_4000 0x4003_4FFF Reserved 0x4003_5000 0x4003_57FF Low Voltage Detector 0x4003_5800 0x4003_5FFF Deep standby mode Controller 0x4003_6000 0x4003_6FFF USB clock generator 0x4003_7000 0x4003_7FFF APB2 Reserved 0x4003_8000 0x4003_8FFF Multi-function serial Interface 0x4003_9000 0x4003_9FFF CRC 0x4003_A000 0x4003_AFFF Watch Counter 0x4003_B000 0x4003_BFFF RTC/Port Ctrl 0x4003_C000 0x4003_C0FF Low-speed CR Prescaler 0x4003_C100 0x4003_C7FF Peripheral Clock Gating 0x4003_C800 0x4003_EFFF Reserved 0x4003_F000 0x4003_FFFF External Memory interface 0x4004_0000 0x4004_FFFF USB ch.0 0x4005_0000 0x4005_FFFF Reserved 0x4006_0000 0x4006_0FFF DMAC register 0x4006_1000 0x4006_3FFF DSTC register 0x4006_4000 0x4006_DFFF AHB Reserved 0x4006_E000 0x4006_EFFF SD-Card I/F 0x4006_F000 0x4006_FFFF GPIO 0x4006_7000 0x41FF_FFFF Reserved 0x200E_0000 0x200E_FFFF WorkFlash I/F register Document Number: Rev.*B Page 59 of 168

60 11. Pin Status in Each CPU State The terms used for pin status have the following meanings. INITX=0 INITX=1 SPL=0 SPL=1 This is the period when the INITX pin is the "L" level. This is the period when the INITX pin is the "H" level. This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to "0". This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to "1". Input Indicates that the input function can be used. at "0" Hi-Z This is the status that the input function cannot be used. input is fixed at "L". Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z. Setting disabled Indicates that the setting is disabled. s the that was immediately prior to entering the current mode. If a built-in peripheral function is operating, the output follows the peripheral function. If the pin is being used as a port, that output is maintained. Analog input is Indicates that the analog input is. Trace output Indicates that the trace function can be used. GPIO selected In Deep standby mode, pins switch to the general-purpose I/O port. Setting prohibition Prohibition of a setting by specification limitation. Document Number: Rev.*B Page 60 of 168

61 List of Pin Status Pin status type A Function group GPIO selected Main crystal oscillator input pin/ External main clock input selected GPIO selected Power-on reset or lowvoltage detection Power supply unstable Setting disabled Input Setting disabled INITX input Device internal reset Power supply stable Run mode or SLEEP mode Power supply stable TIMER mode, RTC mode, or STOP mode Power supply stable Deep standby RTC mode or Deep standby STOP mode Power supply stable Return from Deep standby mode Power supply stable INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 SPL=0 SPL=1 SPL=0 SPL=1 - Setting disabled Input Setting disabled Setting disabled Input Setting disabled Input Input at "0" Input at "0" GPIO selected at "0" Input GPIO selected at "0" at "0" Input at "0" GPIO selected Input GPIO selected B External main clock input selected Main crystal oscillator output pin Setting disabled at "0"/ or Input enable Setting disabled input fixed at "0" Setting disabled input fixed at "0" /When oscillation stops* 1, at "0" /When oscillation stops* 1, at "0" at "0" /When oscillation stops* 1, at "0" /When oscillation stops* 1, at "0" at "0" /When oscillation stops* 1, at "0" /When oscillation stops* 1, at "0" C INITX input pin Pull-up / Input Pull-up / Input Pull-up / Input Pull-up / Input Pull-up / Input Pull-up / Input Pull-up / Input Pull-up / Input Pull-up / Input D Mode input pin Input Input Input Input Input Input Input Input Input E Mode input pin GPIO selected Input Setting disabled Input Setting disabled Input Setting disabled Input Input Input Input Input GPIO selected Input Input Input GPIO selected Document Number: Rev.*B Page 61 of 168

62 Pin status type F Function group NMIX selected Resource other than above selected GPIO selected Power-on reset or lowvoltage detection Power supply unstable Setting disabled Hi-Z INITX input Device internal reset Power supply stable Run mode or SLEEP mode Power supply stable TIMER mode, RTC mode, or STOP mode Power supply stable Deep standby RTC mode or Deep standby STOP mode Power supply stable Return from Deep standby mode Power supply stable INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 SPL=0 SPL=1 SPL=0 SPL=1 - Setting disabled Input Setting disabled Input at "0" WKUP input WKUP input GPIO selected G JTAG selected GPIO selected Hi-Z Setting disabled Pull-up / Input Setting disabled Pull-up / Input Setting disabled at "0" GPIO selected at "0" at "0" GPIO selected H I JTAG selected Resource other than above selected GPIO selected Resource selected GPIO selected Hi-Z Setting disabled Hi-Z Pull-up / Input Setting disabled Input Pull-up / Input Setting disabled Input at "0" at "0" GPIO selected at "0" GPIO selected at "0" at "0" at "0" GPIO selected GPIO selected J Analog output selected Resource other than above selected GPIO selected Setting disabled Hi-Z Setting disabled Input Setting disabled Input *2 *3 at "0" GPIO selected at "0" at "0" GPIO selected Document Number: Rev.*B Page 62 of 168

63 Pin status type K L Function group External interrupt selected Resource other than above selected GPIO selected Analog input selected Power-on reset or lowvoltage detection Power supply unstable Setting disabled Hi-Z Hi-Z INITX input Device internal reset Power supply stable Run mode or SLEEP mode Power supply stable TIMER mode, RTC mode, or STOP mode Power supply stable Deep standby RTC mode or Deep standby STOP mode Power supply stable Return from Deep standby mode Power supply stable INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 SPL=0 SPL=1 SPL=0 SPL=1 - Setting disabled Input input fixedat "0" / Analog input Setting disabled Input input fixedat "0" / Analog input at "0" / Analog input at "0" / Analog input at "0" at "0" / Analog input GPIO selected at "0" at "0" / Analog input at "0" at "0" / Analog input GPIO selected at "0" / Analog input M Resource other than above selected GPIO selected Analog input selected External interrupt selected Resource other than above selected GPIO selected Setting disabled Hi-Z Setting disabled Setting disabled input fixed at "0" / Analog input Setting disabled Setting disabled input fixed at "0" / Analog input Setting disabled at "0" / Analog input at "0" / Analog input at "0" at "0" / Analog input at "0" GPIO selected at "0" at "0" / Analog input GPIO selected at "0" at "0" at "0" / Analog input at "0" GPIO selected at "0" / Analog input GPIO selected Document Number: Rev.*B Page 63 of 168

64 Pin status type N O Function group Analog input selected Trace selected Resource other than above selected GPIO selected Analog input selected Trace selected External interrupt selected Resource other than above selected GPIO selected Power-on reset or lowvoltage detection Power supply unstable Hi-Z Setting disabled Hi-Z Setting disabled INITX input Device internal reset Power supply stable Run mode or SLEEP mode Power supply stable TIMER mode, RTC mode, or STOP mode Power supply stable Deep standby RTC mode or Deep standby STOP mode Power supply stable Return from Deep standby mode Power supply stable INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 SPL=0 SPL=1 SPL=0 SPL=1 - input fixed at"0" / Analog input Setting disabled input fixed at "0" / Analog input Setting disabled input fixed at "0" / Analog input Setting disabled input fixed at "0" / Analog input Setting disabled at "0" / Analog input at "0" / Analog input at "0" / Analog input at "0" / Analog input at "0" / Analog input Trace output at "0" at "0" / Analog input Trace output at "0" at "0" / Analog input GPIO selected at "0" at "0" / Analog input GPIO selected at "0" at "0" / Analog input at "0" at "0" / Analog input at "0" at "0" / Analog input GPIO selected at "0" / Analog input GPIO selected Document Number: Rev.*B Page 64 of 168

65 Pin status type P Q R Function group Analog input selected WKUP Resource other than above selected GPIO selected WKUP External interrupt selected Resource other than above selected GPIO selected GPIO selected USB I/O pin Power-on reset or lowvoltage detection Power supply unstable Hi-Z Setting disabled Setting disabled Hi-Z Hi-Z Setting disabled INITX input Device internal reset Power supply stable Run mode or SLEEP mode Power supply stable TIMER mode, RTC mode, or STOP mode Power supply stable Deep standby RTC mode or Deep standby STOP mode Power supply stable Return from Deep standby mode Power supply stable INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 SPL=0 SPL=1 SPL=0 SPL=1 - input fixedat "0" / Analog input Setting disabled Setting disabled Input Input Setting disabled input fixedat "0" / Analog input Setting disabled Setting disabled Input Input Setting disabled at "0" / Analog input at "0" / Analog input Hi-Z at transmission/ Input / at "0" at reception at "0" / Analog input at "0" at "0" at "0" Hi-Z at transmission/ Input / at "0" at reception at "0" / Analog input WKUP input GPIO selected at "0" WKUP input GPIO selected at "0" GPIO selected at "0" Input at "0" / Analog input WKUP input at "0" WKUP input at "0" at "0" Input at "0" / Analog input GPIO selected GPIO selected GPIO selected Input *1: Oscillation is stopped at Sub timer mode, sub CR timer mode, RTC mode, STOP mode, Deep standby RTC mode, and Deep standby STOP mode. *2: at timer mode. GPIO selected at "0" at RTC mode, STOP mode. *3: at timer mode. Hi-Z/ at "0" at RTC mode, STOP mode. Document Number: Rev.*B Page 65 of 168

66 List of VBAT Domain Pin Status VBAT pin status type S T Function group GPIO selected Sub crystal oscillator input pin / External sub clock input selected GPIO selected External sub clock input selected Sub crystal oscillator output pin Power-on reset *1 Power supply unstable Setting disabled Input Setting disabled Setting disabled INITX input Device internal reset Power supply stable Run mode or SLEEP mode Power supply stable TIMER mode, RTC mode, or STOP mode Power supply stable Deep standby RTC mode or Deep standby STOP mode Power supply stable Return from Deep standby mode Power supply stable VBAT RTC mode Power supply stable INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 - - SPL=0 SPL=1 SPL=0 SPL= Previous Input Previous Previous Previous at "0"/ or Input enable Previous Input Previous Previous Previous Input Input /When oscillation stops, Hi-Z *2 Previous Input Previous Previous /When oscillation stops, Hi-Z *2 Previous Input Previous /When oscillation stops, Hi-Z *2 Previous Input Previous Previous /When oscillation stops, Hi-Z *2 Previous Input Previous Previous Setting prohibition - Setting prohibition - Return from VBAT RTC mode Power supply stable U Resource selected GPIO selected Hi-Z *1: When VBAT and VCC power on. *2: When the SOSCNTL bit in the WTOSCCNT register is 0, the sub crystal oscillator output pin is maintained in the. When the SOSCNTL bit in the WTOSCCNT register is 1, oscillation is stopped at Stop mode and Deep Standby Stop. Document Number: Rev.*B Page 66 of 168

67 12. Electrical Characteristics 12.1 Absolute Maximum Ratings Parameter Symbol Min Rating Power supply voltage * 1, * 2 V CC VSS VSS V Power supply voltage (for USB)* 1, * 3 USBV CC VSS VSS V Power supply voltage (VBAT) * 1, * 4 V BAT VSS VSS V Analog power supply voltage * 1, * 5 AV CC VSS VSS V Analog reference voltage * 1, * 5 AVRH VSS VSS V VSS VCC ( 6.5V) V Input voltage * 1 V I USBVCC VSS ( 6.5V) V Max Unit Remarks Except for USB pin USB pin VSS VSS V 5V tolerant Analog pin input voltage * 1 V IA VSS AVCC ( 6.5V) V Output voltage * 1 V O VSS VCC ( 6.5V) V 10 ma 4mA type "L" level maximum output current * 6 I OL - 20 ma 8mA type 20 ma 12mA type 22.4 ma I 2 C Fm+ 4 ma 4mA type "L" level average output current * 7 I OLAV - 8 ma 8mA type 12 ma 12mA type 20 ma I 2 C Fm+ "L" level total maximum output current I OL ma "L" level total maximum output current * 8 I OLAV - 50 ma - 10 ma 4mA type "H" level maximum output current * 6 I OH - 20 ma 8mA type - 20 ma 12mA type - 4 ma 4mA type "H" level average output current * 7 I OHAV - 8 ma 8mA type - 12 ma 12mA type "H" level total maximum output current I OH ma "H" level total average output current * 8 I OHAV ma Storage temperature T STG C *1: These parameters are based on the condition that VSS = AVSS = 0.0V. *2: VCC must not drop below VSS - 0.5V. *3: USBVCC must not drop below VSS - 0.5V. *4: VBAT must not drop below VSS - 0.5V. *5: Ensure that the voltage does not exceed VCC + 0.5V, for example, when the power is turned on. *6: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *7: The average output current is defined as the average current value flowing through any one of the corresponding pins for a 100ms period. *8: The total average output current is defined as the average current value flowing through all of corresponding pins for a 100ms. WARNING: Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings. Document Number: Rev.*B Page 67 of 168

68 12.2 Recommended Operating Conditions Value Parameter Symbol Conditions Unit Min Max Power supply voltage V CC *5 5.5 V ( VCC) Power supply voltage (for USB) USBV CC - V ( VCC) *1 *2 Remarks Power supply voltage (VBAT) V BAT V Analog power supply voltage AV CC V AV CC=V CC Analog reference voltage AVRH - *4 AVCC V Operating temperature Junction temperature Tj C Ambient temperature T A *3 C *1: When P81/UDP0 and P80/UDM0 pins are used as USB (UDP0, UDM0). *2: When P81/UDP0 and P80/UDM0 pins are used as GPIO (P81, P80). *3: The maximum temperature of the ambient temperature (TA) can guarantee a range that does not exceed the junction temperature (Tj). The calculation formula of the ambient temperature (TA) is shown below. TA(Max) = Tj(Max) - Pd(Max) θja Pd: θja: Power dissipation (W) Package thermal resistance ( C/W) Pd (Max) = VCC ICC (Max) + Σ (IOL VOL) + Σ ((VCC-VOH) (- IOH)) IOL: IOH: VOL: VOH: "L" level output current "H" level output current "L" level output voltage "H" level output voltage *4: The minimum value of Analog reference voltage depends on the value of compare clock cycle (Tcck). See bit A/D Converter for the details. *5: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction execution and low voltage detection function by built-in High-speed CR(including Main PLL is used) or built-in Low-speed CR is possible to operate only. Package thermal resistance and maximum permissible power for each package are shown below. The operation is guaranteed maximum permissible power or less for semiconductor devices. Table for package thermal resistance and maximum permissible power Package Printed circuit board Maximum permissible power Thermal resistance (mw) θja ( C/W) TA=+85 C TA=+105 C LQH080 Single-layered both sides (0.5mm pitch) 4 layers LQJ080 Single-layered both sides (0.65mm pitch) 4 layers LQI100 Single-layered both sides (0.5mm pitch) 4 layers PQH100 Single-layered both sides (0.65mm pitch) 4 layers LQM120 Single-layered both sides (0.5mm pitch) 4 layers LDC112 Single-layered both sides (0.5mm pitch) 4 layers LDC144 Single-layered both sides (0.5mm pitch) 4 layers Document Number: Rev.*B Page 68 of 168

69 WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. Any use of semiconductor devices will be under their recommended operating condition. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. Calculation method of power dissipation (Pd) The power dissipation is shown in the following formula. Pd = VCC ICC + Σ (IOL VOL) + Σ ((VCC-VOH) (-IOH)) IOL: IOH: VOL: VOH: "L" level output current "H" level output current "L" level output voltage "H" level output voltage ICC is a current consumed in device. It can be analyzed as follows. ICC = ICC(INT) + ΣICC(IO) ICC(INT): ΣICC(IO): Current consumed in internal logic and memory, etc. through regulator Sum of current (I/O switching current) consumed in output pin For ICC (INT), it can be anticipated by "(1) Current Rating" in "3. DC Characteristics" (This rating value does not include ICC (IO) for a value at pin fixed). For Icc (IO), it depends on system used by customers. The calculation formula is shown below. ICC(IO) = (CINT + CEXT) VCC fsw CINT: Pin internal load capacitance CEXT: External load capacitance of output pin fsw: Pin switching frequency Parameter Symbol Conditions Capacitance value Pin internal load capacitance C INT 4mA type 8mA type 12mA type Calculate ICC (Max) as follows when the power dissipation can be evaluated by yourself. 1. Measure current value ICC (Typ) at normal temperature (+25 C). 2. Add maximum leak current value ICC (leak_max) at operating on a value in (1). ICC(Max) = ICC(Typ) + ICC(leak_max) 1.93pF 3.45pF 3.42pF Parameter Symbol Conditions Current value Tj = +125 C 45.5mA Maximum leak current at I CC(leak_max) Tj = +105 C 26.8mA operating Tj = +85 C 16.2mA Document Number: Rev.*B Page 69 of 168

70 Current explanation diagram ICC A VCC Pd = VCC ICC + Σ(IOL VOL)+Σ((VCC-VOH) (-IOH)) ICC = ICC(INT)+ΣICC(IO) Chip ICC(INT) ΣICC(IO) Regulator A IOL V VOL Flash RAM Logic ICC(IO) VOH V A CEXT IOH Document Number: Rev.*B Page 70 of 168

71 12.3 DC Characteristics Current Rating Table Typical and maximum current consumption in Normal operation(pll), code running from Flash memory (Flash accelerator mode and trace buffer function ) Parameter Power supply current Symbol I CC Pin name VCC Conditions Frequency* 4 Typ *1 Value Max *2 160MHz Normal operation* 5, * 6 (PLL) 144MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz Document Number: Rev.*B Page 71 of 168 Unit ma ma Remarks *3 When all peripheral clocks are ON *3 When all peripheral clocks are OFF Table Typical and maximum current consumption in Normal operation(pll), code with data accessing running from Flash memory (Flash accelerator mode and trace buffer function disabled) Parameter Symbol Pin name Conditions Frequency* 7 Value Typ* 1 Max* 2 160MHz MHz MHz MHz MHz MHz MHz MHz MHz Normal Power supply 4MHz I current CC VCC operation* 8 160MHz (PLL) 144MHz MHz MHz MHz MHz MHz MHz MHz MHz *1: TA=+25 C, VCC=3.3V *2: Tj=+125 C, VCC=5.5V *3: When all ports are fixed. *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2 *5: When operating flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 1) Unit ma ma Remarks *3 When all peripheral clocks are ON *3 When all peripheral clocks are OFF

72 *6: Data access is nothing to MainFlash memory *7: Frequency is a value of HCLK. PCLK0=PCLK2=HCLK/2, PCLK1=HCLK *8: When stopping flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 0) Table Typical and maximum current consumption in Normal operation(pll), code with data accessing running from Flash memory (flash 0 wait-cycle mode and read access 0 wait) Parameter Power supply current Symbol I CC *1: TA=+25 C, VCC=3.3V *2: Tj=+125 C, VCC=5.5V *3: When all ports are fixed. Pin name VCC Conditions Normal operation* 5 (PLL) Frequency* 4 (MHz) *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK *5: When 0 wait-cycle mode (FRWTR.RWT = 00, FSYNDN.SD = 00) Value Typ* 1 Max* 2 72MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz Unit ma ma Remarks *3 When all peripheral clocks are ON *3 When all peripheral clocks are OFF Document Number: Rev.*B Page 72 of 168

73 Table Typical and maximum current consumption in Normal operation(other than PLL), code with data accessing running from Flash memory (flash 0 wait-cycle mode and read access 0 wait Parameter Power supply current Symbol I CC *1: TA=+25 C, VCC=3.3V *2: Tj=+125 C, VCC=5.5V *3: When all ports are fixed. Pin name VCC Conditions Frequency* 4 Normal operation* 5 (built-in highspeed CR) Normal operation* 5 (sub oscillation) Normal operation* 5 (built-in low-speed CR) 4MHz 32kHz 100kHz *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2 *5: When 0 wait-cycle mode (FRWTR.RWT = 00, FSYNDN.SD = 000) Value Typ* 1 Max* 2 Unit ma ma ma ma ma ma Remarks *3 When all peripheral clocks are ON *3 When all peripheral clocks are OFF *3 When all peripheral clocks are ON *3 When all peripheral clocks are OFF *3 When all peripheral clocks are ON *3 When all peripheral clocks are OFF Document Number: Rev.*B Page 73 of 168

74 Table Typical and maximum current consumption in Sleep operation(pll), when PCLK0 = PCLK1 = PCLK2 = HCLK/2 Parameter Power supply current Symbol I CCS Pin name VCC Conditions Frequency* 4 Value Typ* 1 Max* 2 160MHz SLEEP operation (PLL) 144MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz Unit ma ma Remarks *3 When all peripheral clocks are ON *3 When all peripheral clocks are OFF Table Typical and maximum current consumption in Sleep operation(pll), when PCLK0 = PCLK1 = PCLK2 = HCLK Parameter Power supply current Symbol I CCS *1: TA=+25 C, VCC=3.3V *2: Tj=+125 C, VCC=5.5V *3: When all ports are fixed. Pin name VCC Conditions Frequency* 5 Value Typ* 1 Max* 2 72MHz MHz SLEEP operation (PLL) *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2 *5: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK 48MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz Unit ma ma Remarks *3 When all peripheral clocks are ON *3 When all peripheral clocks are OFF Document Number: Rev.*B Page 74 of 168

75 Table Typical and maximum current consumption in Sleep operation(other than PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK/2 Parameter Power supply current Symbol I CCS *1: TA=+25 C, VCC=3.3V *2: Tj=+125 C, VCC=5.5V *3: When all ports are fixed. Pin name VCC Conditions Frequency* 4 SLEEP operation (built-in highspeed CR) SLEEP operation (sub oscillation) SLEEP operation (built-in lowspeed CR) 4MHz 32kHz 100kHz *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2 Value Typ* 1 Max* 2 Unit ma ma ma ma ma ma Remarks *3 When all peripheral clocks are ON *3 When all peripheral clocks are OFF *3 When all peripheral clocks are ON *3 When all peripheral clocks are OFF *3 When all peripheral clocks are ON *3 When all peripheral clocks are OFF Document Number: Rev.*B Page 75 of 168

76 Table Typical and maximum current consumption in STOP mode, TIMER mode and RTC mode Parameter Symbol Pin name Conditions Frequency Power supply current *1: VCC=3.3V *2: VCC=5.5V I CCH I CCT I CCR *3: When all ports are fixed. *4: When LVD is OFF VCC STOP mode - TIMER mode (built-in highspeed CR) TIMER mode (sub oscillation) TIMER mode (built-in low-speed CR) RTC mode (sub oscillation) 4MHz 32kHz 100kHz 32kHz Value Typ* 1 Max* 2 Unit ma - 15 ma - 22 ma ma - 16 ma - 22 ma ma - 15 ma - 22 ma ma - 15 ma - 22 ma ma - 15 ma - 22 ma Remarks *3, *4 T A=+25 C *3, *4 T A=+85 C *3, *4 T A=+105 C *3, *4 T A=+25 C *3, *4 T A=+85 C *3, *4 T A=+105 C *3, *4 T A=+25 C *3, *4 T A=+85 C *3, *4 T A=+105 C *3, *4 T A=+25 C *3, *4 T A=+85 C *3, *4 T A=+105 C *3, *4 T A=+25 C *3, *4 T A=+85 C *3, *4 T A=+105 C Document Number: Rev.*B Page 76 of 168

77 Table Typical and maximum current consumption in Deep Standby STOP mode, Deep Standby RTC mode and VBAT Parameter Symbol Pin name Conditions Frequency Power supply current *1: VCC=3.3V *2: VCC=5.5V I CCHD I CCRD I CCVBAT *3: When all ports are fixed. *4: When LVD is OFF *5: When sub oscillation is OFF VCC VBAT *6: In the case of setting RTC after VCC power on Deep standby STOP mode (When RAM is OFF) Deep standby STOP mode (When RAM is ON) Deep standby RTC mode (When RAM is OFF) Deep standby RTC mode (When RAM is ON) RTC stop*6 RTC operation*6-32khz - Value Typ* 1 Max* 2 Unit μa μa μa μa μa μa μa μa μa μa μa μa μa μa μa μa μa μa Remarks *3, *4 T A=+25 C *3, *4 T A=+85 C *3, *4 T A=+105 C *3, *4 T A=+25 C *3, *4 T A=+85 C *3, *4 T A=+105 C *3, *4 T A=+25 C *3, *4 T A=+85 C *3, *4 T A=+105 C *3, *4 T A=+25 C *3, *4 T A=+85 C *3, *4 T A=+105 C *3, *4, *5 T A=+25 C *3, *4, *5 T A=+85 C *3, *4, *5 T A=+105 C *3, *4 T A=+25 C *3, *4 T A=+85 C *3, *4 T A=+105 C Document Number: Rev.*B Page 77 of 168

78 Table Typical and maximum current consumption in Low-voltage detection circuit, Main flash memory write/erase Value Parameter Symbol Pin name Conditions Unit Remarks Min Typ Max Low-voltage detection circuit (LVD) power supply current I CCLVD At operation μa For occurrence of interrupt Main flash memory write/erase current Work flash memory write/erase current VCC I CCFLASH At Write/Erase ma I CCWFLASH At Write/Erase ma Peripheral current dissipation Clock system Peripheral Unit Frequency (MHz) GPIO All ports DMAC Unit Remarks HCLK PCLK1 DSTC External bus I/F SD card I/F USB 1ch Base timer 4ch Multi-functional timer/ppg Quadrature position/revolution counter 1unit/4ch unit A/DC 1unit ma ma PCLK2 Muli-function serial 1ch ma Document Number: Rev.*B Page 78 of 168

79 Pin Characteristics Parameter Symbol Pin name Conditions "H" level input voltage (hysteresis input) "L" level input voltage (hysteresis input) "H" level output voltage V IHS V ILS V OH CMOS hysteresis input pin, MD0, MD1 5V tolerant input pin Input pin doubled as I 2 C Fm+ CMOS hysteresis input pin, MD0, MD1 5V tolerant input pin Input pin doubled as I 2 C Fm+ 4mA type 8mA type 12mA type The pin doubled as USB I/O The pin doubled as I 2 C Fm+ (VCC = USBVCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V) Value Min Typ Max - VCC VCC V - VCC VSS V - VCC VSS V - VSS VCC 0.2 V - VSS VCC 0.2 V - VSS - VCC 0.3 V V CC 4.5 V, I OH = - 4mA V CC < 4.5 V, I OH = - 2mA V CC 4.5 V, I OH = - 8mA V CC < 4.5 V, I OH = - 4mA V CC 4.5 V, I OH = - 12mA V CC < 4.5 V, I OH = - 8mA USBV CC 4.5 V, I OH = mA USBV CC < 4.5 V, I OH = mA V CC 4.5 V, I OH = - 4mA V CC < 4.5 V, I OH = - 3mA Unit VCC VCC V VCC VCC V VCC VCC V USBVCC USBVCC V Remarks VCC VCC V At GPIO Document Number: Rev.*B Page 79 of 168

80 Parameter Symbol Pin name Conditions Value Min Typ Max Unit Remarks 4mA type V CC 4.5 V, I OL = 4mA V CC < 4.5 V, I OL = 2mA VSS V 8mA type V CC 4.5 V, I OH = 8mA V CC < 4.5 V, I OH = 4mA VSS V "L" level output voltage V OL 12mA type V CC 4.5 V, I OL = 12mA V CC < 4.5 V, I OL = 8mA VSS V The pin doubled as USB I/O USBV CC 4.5 V, I OL = 18.5mA USBV CC < 4.5 V, I OL = 10.5mA VSS V The pin doubled as I 2 C Fm+ V CC 4.5 V, I OH = 4mA V CC < 4.5 V, I OH = 3mA VSS V At GPIO V CC 5.5 V, I OH = 20mA At I 2 C Fm+ Input leak current I IL μa Pull-up resistor V CC 4.5 V R PU Pull-up pin kω value V CC < 4.5 V Input capacitance C IN Other than VCC, USBVCC, VBAT, VSS, AVCC, AVSS, AVRH pf Document Number: Rev.*B Page 80 of 168

81 12.4 AC Characteristics Main Clock Input Characteristics Parameter Symbol Pin name Conditions Input frequency Input clock cycle Input clock pulse width Input clock rising time and falling time operating clock* 1 frequency operating clock* 1 cycle time F CH t CYLH - t CF, t CR X0, X1 Min Value Max (VCC = 2.7V to 5.5V, VSS = 0V) Unit V CC 4.5V 4 48 V CC < 4.5V 4 20 MHz V CC 4.5V 4 48 V CC < 4.5V 4 20 MHz V CC 4.5V V CC < 4.5V ns P WH/t CYLH, P WL/t CYLH % ns F CC MHz Remarks When crystal oscillator is connected When using external clock When using external clock When using external clock When using external clock Base clock (HCLK/FCLK) F CP MHz APB0 bus clock* 2 F CP MHz APB1 bus clock* 2 F CP MHz APB2 bus clock* 2 t CYCC ns Base clock (HCLK/FCLK) t CYCP ns APB0 bus clock* 2 t CYCP ns APB1 bus clock* 2 t CYCP ns APB2 bus clock* 2 *1: For more information about each internal operating clock, see Chapter: Clock in FM4 Family Peripheral Manual. *2: For about each APB bus which each peripheral is connected to, see Block Diagram in this datasheet. X0 Document Number: Rev.*B Page 81 of 168

82 Sub Clock Input Characteristics Parameter Symbol Pin name Conditions Value Min Typ Max khz Input frequency 1/ t CYLL Input clock cycle t CYLL X0A, X1A khz μs Input clock pulse width - PWH/tCYLL, PWL/t CYLL (VBAT = 2.7V to 5.5V, VSS = 0V) Unit % Remarks When crystal oscillator is connected When using external clock When using external clock When using external clock 0.8 VBAT VBAT VBAT X0A VBAT VBAT Built-in CR Oscillation Characteristics Built-in High-speed CR Parameter Symbol Conditions Value Min Typ Max Clock frequency F CRH Tj = -20 C to C Tj = - 40 C to C (VCC = 2.7V to 5.5V, VSS = 0V) Unit Remarks When trimming *1 MHz Clock frequency F CRH Tj = - 40 C to C When not trimming Frequency tcrwt μs *2 stabilization time *1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency/temperature trimming. *2: This is the time to stabilize the frequency of high-speed CR clock after setting trimming value. This period is able to use highspeed CR clock as source clock. Built-in Low-speed CR Parameter Symbol Condition Value Min Typ Max (VCC = 2.7V to 5.5V, VSS = 0V) Unit Remarks Clock frequency F CRL khz Document Number: Rev.*B Page 82 of 168

83 Operating Conditions of Main PLL (In the case of using main clock for input clock of PLL) Parameter Symbol (VCC = 2.7V to 5.5V, VSS = 0V) Value Unit Remarks Min Typ Max PLL oscillation stabilization wait time* 1 t LOCK μs (LOCK UP time) PLL input clock frequency F PLLI 4-16 MHz PLL multiplication rate multiplier PLL macro oscillation clock frequency F PLLO MHz Main PLL clock frequency* 2 F CLKPLL MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see Chapter: Clock in FM4 Family Peripheral Manual Operating Conditions of USB PLL (In the case of using main clock for input clock of PLL) Parameter PLL oscillation stabilization wait time* 1 (LOCK UP time) Symbol (VCC = 2.7V to 5.5V, VSS = 0V) Value Unit Remarks Min Typ Max t LOCK μs PLL input clock frequency F PLLI 4-16 MHz PLL multiplication rate multiplier PLL macro oscillation clock frequency F PLLO MHz USB clock frequency* 2 F CLKSPLL MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about USB clock, see "Chapter: USB Clock Generation" in "FM4 Family Peripheral Manual Communication Macro Part". After the M frequency division Operating Conditions of Main PLL (In the case of using built-in high-speed CR clock for input clock of main PLL) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Value Unit Remarks Min Typ Max PLL oscillation stabilization wait time* 1 t LOCK μs (LOCK UP time) PLL input clock frequency F PLLI MHz PLL multiplication rate multiplier PLL macro oscillation clock frequency F PLLO MHz Main PLL clock frequency* 2 F CLKPLL MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see Chapter: Clock in FM4 Family Peripheral Manual. Note: Make sure to input to the main PLL source clock, the high-speed CR clock (CLKHC) that the frequency and temperature has been trimmed. Document Number: Rev.*B Page 83 of 168

84 Reset Input Characteristics (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin name Condition Reset input time Value t INITX INITX ns Min Max Unit Remarks Power-on Reset Timing (VSS = 0V, TA = -40 C to +85 C) Parameter Symbol Pin Name Conditions Value Min Typ Max Unit Remarks Power supply shut down time toff ms *1 Power ramp rate dv/dt VCC VCC: 0.2V to 2.70V mv/µs *2 Time until releasing Power-on reset tprt ms *1: VCC must be held below 0.2V for a minimum period of toff. Improper initialization may occur if this condition is not met. *2: This dv/dt characteristic is applied at the power-on of cold start (toff>50ms). Note: If toff cannot be satisfied designs must assert external reset(initx) at power-up and at any brownout event per V V CC V DH 0.2V dv/dt 0.2V 0.2V tprt toff RST CPU Operation RST Active release start Glossary: VDH: detection voltage of Low Voltage detection reset. See Low-Voltage Detection Characteristics. Document Number: Rev.*B Page 84 of 168

85 GPIO Output Characteristics Parameter Symbol Pin name Conditions Output frequency t PCYCLE Pxx * *: GPIO is a target. Min (VCC = 2.7V to 5.5V, VSS = 0V) Value Max Unit V CC 4.5 V - 50 MHz V CC < 4.5 V - 32 MHz Pxx t PCYCLE External Bus Timing External bus clock output characteristics Parameter Symbol Pin name Conditions Output frequency t CYCLE MCLKOUT* 1 Min (VCC = 2.7V to 5.5V, VSS = 0V) Value Max Unit V CC 4.5 V - 50* 2 MHz V CC < 4.5 V - 32* 3 MHz *1: The external bus clock (MCLKOUT) is a divided clock of HCLK. For more information about setting of clock divider, see Chapter: External Bus Interface in FM4 Family Peripheral Manual. *2: Generate MCLKOUT at setting more than 4 division when the AHB bus clock exceeds 100MHz. *3: Generate MCLKOUT at setting more than 4 division when the AHB bus clock exceeds 64MHz. MCLK 0.8 Vcc 0.8 Vcc t CYCLE Document Number: Rev.*B Page 85 of 168

86 External bus signal input/output characteristics (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions Value Unit Remarks Signal input characteristics Signal output characteristics V IH 0.8 VCC V V IL 0.2 VCC V - V OH 0.8 VCC V V OL 0.2 VCC V Signal input VIH VIL VIH VIL Signal output VOH VOL VOH VOL Document Number: Rev.*B Page 86 of 168

87 Separate Bus Access Asynchronous SRAM Mode Parameter Symbol Pin name Conditions MOEX Mininum pulse width MCSX Address output delay time MOEX Address hold time MCSX MOEX delay time MOEX MCSX time MCSX MDQM delay time Data set up MOEX time MOEX Data hold time MWEX Mininum pulse width MWEX Address output delay time MCSX MWEX delay time MWEX MCSX delay time MCSX MDQM delay time MCSX Data output time MWEX Data hold time t OEW t CSL AV t OEH - AX t CSL - OEL t OEH - CSH t CSL - RDQML t DS - OE t DH - OE t WEW t WEH - AX t CSL - WEL t WEH - CSH t CSL-WDQML t CSL-DX t WEH - DX MOEX MCSX[7:0], MAD[24:0] MOEX, MAD[24:0] MOEX, MCSX[7:0] MCSX, MDQM[1:0] MOEX, MADATA[15:0] MOEX, MADATA[15:0] MWEX MWEX, MAD[24:0] MWEX, MCSX[7:0] MCSX, MDQM[1:0] MCSX, MADATA[15:0] MWEX, MADATA[15:0] V CC 4.5V V CC < 4.5V Note: When the external load capacitance CL = 30pF (m=0 to 15, n=1 to 16) Min Value (VCC = 2.7V to 5.5V, VSS = 0V) Max Unit MCLK n-3 - ns V CC 4.5V V CC < 4.5V ns V CC 4.5V MCLK m+9 0 V CC < 4.5V MCLK m+12 ns V CC 4.5V MCLK m-9 MCLK m+9 V CC < 4.5V MCLK m-12 MCLK m+12 ns V CC 4.5V MCLK m+9 0 V CC < 4.5V MCLK m+12 ns V CC 4.5V MCLK m-9 MCLK m+9 V CC < 4.5V MCLK m-12 MCLK m+12 ns V CC 4.5V 20 - V CC < 4.5V 38 - ns V CC 4.5V V CC < 4.5V 0 - ns V CC 4.5V V CC < 4.5V MCLK n-3 - ns V CC 4.5V MCLK m+9 0 V CC < 4.5V MCLK m+12 V CC 4.5V MCLK n-9 MCLK n+9 V CC < 4.5V MCLK n-12 MCLK n+12 V CC 4.5V MCLK m+9 0 V CC < 4.5V MCLK m+12 V CC 4.5V MCLK n-9 MCLK n+9 V CC < 4.5V MCLK n-12 MCLK n+12 V CC 4.5V MCLK-9 MCLK+9 V CC < 4.5V MCLK-12 MCLK+12 V CC 4.5V MCLK m+9 0 V CC < 4.5V MCLK m+12 ns ns ns ns ns ns Document Number: Rev.*B Page 87 of 168

88 t CYCLE MCLK t OEH-CSH t WEH-CSH MCSX[7:0] MAD[24:0] t CSL-AV t CSL-OEL t OEH-AX Address t CSL-AV Address t WEH-AX MOEX tcsl-rdqml t OEW t CSL-WDQML MDQM[1:0] t CSL-WEL t WEW MWEX MADATA[15:0] t DS-OE RD t DH-OE Invalid WD t WEH-DX t CSL-DX Document Number: Rev.*B Page 88 of 168

89 Separate Bus Access Synchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin name Conditions Value Min Max Unit Address delay time t AV MCLK, V CC 4.5V 9 1 MAD[24:0] V CC < 4.5V 12 ns MCSX delay time t CSL V CC 4.5V 9 1 MCLK, V CC < 4.5V 12 ns t CSH MCSX[7:0] V CC 4.5V 9 1 V CC < 4.5V 12 ns MOEX delay time t REL V CC 4.5V 9 1 MCLK, V CC < 4.5V 12 ns t REH MOEX V CC 4.5V 9 1 V CC < 4.5V 12 ns Data set up MCLK, V CC 4.5V 19 t DS MCLK time MADATA[15:0] V CC < 4.5V 37 - ns MCLK Data hold time MWEX delay time MDQM[1:0] delay time MCLK Data output time MCLK Data hold time t DH t WEL t WEH t DQML t DQMH t ODS t OD MCLK, MADATA[15:0] MCLK, MWEX MCLK, MDQM[1:0] MCLK, MADATA[15:0] MCLK, MADATA[15:0] Note: When the external load capacitance CL = 30pF V CC 4.5V V CC < 4.5V 0 - ns V CC 4.5V 9 1 V CC < 4.5V 12 ns V CC 4.5V 9 1 V CC < 4.5V 12 ns V CC 4.5V 9 1 V CC < 4.5V 12 ns V CC 4.5V 9 1 V CC < 4.5V 12 ns V CC 4.5V MCLK+18 MCLK+1 V CC < 4.5V MCLK+24 ns V CC 4.5V 18 1 V CC < 4.5V 24 ns Document Number: Rev.*B Page 89 of 168

90 t CYCLE MCLK MCSX[7:0] t CSL t CSH MAD[24:0] t AV Address t AV Address MOEX t REL t REH MDQM[1:0] t DQML t DQMH t DQML t DQMH MWEX t WEL t WEH MADATA[15:0] t DS RD t DH Invalid WD t OD t ODS Document Number: Rev.*B Page 90 of 168

91 Multiplexed Bus Access Asynchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V) Value Parameter Symbol Pin name Conditions Min Max Multiplexed V CC 4.5V 10 t ALE-CHMADV 0 address delay time V MALE, CC < 4.5V 20 Multiplexed MADATA[15:0] V CC 4.5V MCLK n+0 MCLK n+10 t address hold time CHMADH V CC < 4.5V MCLK n+0 MCLK n+20 Note: When the external load capacitance CL = 30pF (m=0 to 15, n=1 to 16) Unit ns ns MCLK MCSX[7:0] MALE MAD [24:0] MOEX MDQM [1:0] MWEX MADATA[15:0] Document Number: Rev.*B Page 91 of 168

92 Multiplexed Bus Access Synchronous SRAM Mode Value Parameter Symbol Pin name Conditions Unit Min Max V CC 4.5V 9 ns t CHAL 1 MALE delay MCLK, V CC < 4.5V 12 ns time ALE V CC 4.5V 9 ns t CHAH 1 V CC < 4.5V 12 ns MCLK Multiplexed address delay time MCLK Multiplexed data output time t CHMADV t CHMADX MCLK, MADATA[15:0] Note: When the external load capacitance CL = 30pF V CC 4.5V V CC < 4.5V V CC 4.5V V CC < 4.5V 1 tod ns 1 tod ns (VCC = 2.7V to 5.5V, VSS = 0V) Remarks MCLK MCSX[7:0] MALE MAD [24:0] MOEX MDQM [1:0] MWEX MADATA[15:0] Document Number: Rev.*B Page 92 of 168

93 NAND Flash Mode MNREX Min pulse width Data set up MNREX time MNREX Data hold time MNALE MNWEX delay time MNALE MNWEX delay time MNCLE MNWEX delay time MNWEX MNCLE delay time MNWEX Min pulse width MNWEX Data output time MNWEX Data hold time (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin name Conditions Min Value Max Unit t NREW MNREX V CC 4.5V V CC < 4.5V MCLK n-3 - ns t DS NRE MNREX, V CC 4.5V 20 - MADATA[15:0] V CC < 4.5V 38 - ns t DH NRE MNREX, MADATA[15:0] V CC 4.5V V CC < 4.5V 0 - ns t ALEH - NWEL MNALE, V CC 4.5V MCLK m-9 MCLK m+9 MNWEX V CC < 4.5V MCLK m-12 MCLK m+12 ns t ALEL - NWEL t CLEH - NWEL t NWEH - CLEL t NWEW t NWEL DV t NWEH DX MNALE, MNWEX MNCLE, MNWEX MNCLE, MNWEX MNWEX MNWEX, MADATA[15:0] MNWEX, MADATA[15:0] V CC 4.5V MCLK m-9 MCLK m+9 V CC < 4.5V MCLK m-12 MCLK m+12 V CC 4.5V MCLK m-9 MCLK m+9 V CC < 4.5V MCLK m-12 MCLK m+12 V CC 4.5V V CC < 4.5V Note: When the external load capacitance CL = 30pF (m=0 to 15, n=1 to 16) 0 MCLK m+9 MCLK m+12 V CC 4.5V V CC < 4.5V MCLK n-3 - ns V CC 4.5V V CC < 4.5V ns V CC 4.5V MCLK m+9 0 V CC < 4.5V MCLK m+12 ns ns ns ns NAND Flash Read MCLK MNREX MADATA[15:0] Read Document Number: Rev.*B Page 93 of 168

94 NAND Flash Address Write MCLK MNALE MNCLE MNWEX MADATA[15:0] Write NAND Flash Command Write MCLK MNALE MNCLE MNWEX MADATA[15:0] Write Document Number: Rev.*B Page 94 of 168

95 External Ready Input Timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin name Conditions Min Value Max Unit Remarks MCLK MRDY input setup time t RDYI MCLK, MRDY V CC 4.5V 19 V CC < 4.5V 37 - ns When RDY is input MCLK Original MOEX MWEX Over 2cycle t RDYI MRDY When RDY is released MCLK 2 cycle Extended MOEX MWEX trdyi MRDY 0.5 VCC Document Number: Rev.*B Page 95 of 168

96 SDRAM Mode Parameter Symbol Pin name (VCC = 2.7V to 3.6V, VSS = 0V) Output frequency t CYCSD MSDCLK - 32 MHz Address delay time t AOSD MSDCLK, MAD[15:0] Min Value Max Unit 2 12 ns MSDCLK Data output delay time t DOSD MSDCLK, MADATA[31:0] 2 12 ns MSDCLK Data output Hi-Z time t DOZSD MSDCLK, MADATA[31:0] 2 20 ns MDQM[1:0] delay time t WROSD MSDCLK, MDQM[1:0] 1 12 ns MCSX delay time t MCSSD MSDCLK, MCSX ns MRASX delay time t RASSD MSDCLK, MRASX 2 12 ns MCASX delay time t CASSD MSDCLK, MCASX 2 12 ns MSDWEX delay time t MWESD MSDCLK, MSDWEX 2 12 ns MSDCKE delay time t CKESD MSDCLK, MSDCKE 2 12 ns Data set up time t DSSD MSDCLK, MADATA[31:0] 23 - ns Data hold time t DHSD MSDCLK, MADATA[31:0] 0 - ns Note: When the external load capacitance CL = 30pF Document Number: Rev.*B Page 96 of 168

97 SDRAM Access t CYCSD MSDCLK MAD[24:0] t AOSD Address MDQM[1:0] t WROSD MCSX t MCSSD MRASX t RASSD MCASX t CASSD MSDWEX t MWESD MSDCKE t CKESD MADATA[15:0] t DSSD RD t DHSD MADATA[15:0] t DOSD WD t DOZSD Document Number: Rev.*B Page 97 of 168

98 Base Timer Input Timing Timer input timing Parameter Symbol Pin name Conditions Input pulse width t TIWH, t TIWL TIOAn/TIOBn (when using as ECK, TIN) Min Value Max (VCC = 2.7V to 5.5V, VSS = 0V) Unit - 2tCYCP - ns Remarks ECK t TIWH t TIWL TIN V IHS V IHS V ILS V ILS Trigger input timing Parameter Symbol Pin name Conditions Input pulse width t TRGH, t TRGL TIOAn/TIOBn (when using as TGIN) Min Value Max (VCC = 2.7V to 5.5V, VSS = 0V) Unit - 2tCYCP - ns Remarks t TRGH t TRGL TGIN V IHS V IHS V ILS V ILS Note: tcycp indicates the APB bus clock cycle time. About the APB bus number which the Base Timer is connected to, see Block Diagram in this data sheet. Document Number: Rev.*B Page 98 of 168

99 CSIO/UART Timing Synchronous serial (SPI = 0, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin name Conditions VCC < 4.5V VCC 4.5V Min Max Min Max Unit Baud rate Mbps Serial clock cycle time t SCYC SCKx 4tCYCP - 4tCYCP - ns SCK SOT SCKx, t SLOVI shift ns delay time SOTx clock SIN SCK SCKx, t IVSHI operation ns setup time SINx SCK SIN SCKx, t SHIXI hold time SINx ns Serial clock "L" pulse width t SLSH SCKx 2tCYCP tCYCP ns Serial clock "H" pulse width t SHSL SCKx tcycp tcycp ns SCK SOT SCKx, t SLOVE delay time SOTx External shift ns SIN SCK SCKx, clock t IVSHE setup time SINx operation ns SCK SIN SCKx, t SHIXE hold time SINx ns SCK falling time tf SCKx ns SCK rising time tr SCKx ns Notes: The above characteristics apply to CLK synchronous mode. tcycp indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see Block Diagram in this datasheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. When the external load capacitance CL = 30pF. Document Number: Rev.*B Page 99 of 168

100 tscyc SCK VOL VOH VOL t SLOVI SOT VOH VOL SIN VIH VIL tivshi tshixi VIH VIL MS bit = 0 tslsh tshsl SCK VIH tf VIL t SLOVE VIL VIH tr VIH SOT VOH VOL SIN tivshe VIH VIL MS bit = 1 tshixe VIH VIL Document Number: Rev.*B Page 100 of 168

101 Synchronous serial (SPI = 0, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) VCC < 4.5V VCC 4.5V Parameter Symbol Pin name Conditions Unit Min Max Min Max Baud rate Mbps Serial clock t SCYC SCKx 4tCYCP - 4tCYCP - ns cycle time SCK SOT delay time t SHOVI SCKx, SOTx shift clock operation ns SIN SCK SCKx, t IVSLI setup time SINx ns SCK SIN SCKx, t SLIXI hold time SINx ns Serial clock "L" pulse width t SLSH SCKx 2tCYCP tCYCP ns Serial clock "H" pulse width t SHSL SCKx tcycp tcycp ns SCK SOT SCKx, t SHOVE delay time SOTx External shift ns SIN SCK SCKx, clock t IVSLE setup time SINx operation ns SCK SIN SCKx, t SLIXE hold time SINx ns SCK falling time tf SCKx ns SCK rising time tr SCKx ns Notes: The above characteristics apply to CLK synchronous mode. tcycp indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see Block Diagram in this datasheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. When the external load capacitance CL = 30pF. Document Number: Rev.*B Page 101 of 168

102 tscyc SCK VOH VOH VOL t SHOVI SOT VOH VOL SIN VIH VIL tivsli tslixi VIH VIL MS bit = 0 tshsl tslsh SCK VIH VIH tr VIL t SHOVE tf VIL VIL SOT VOH VOL tivsle tslixe SIN VIH VIL VIH VIL MS bit = 1 Document Number: Rev.*B Page 102 of 168

103 Synchronous serial (SPI = 1, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) VCC < 4.5V VCC 4.5V Parameter Symbol Pin name Conditions Unit Min Max Min Max Baud rate Mbps Serial clock t SCYC SCKx 4tCYCP - 4tCYCP - ns cycle time SCK SOT delay time t SHOVI SCKx, SOTx shift clock operation ns SIN SCK SCKx, t IVSLI setup time SINx ns SCK SIN SCKx, t SLIXI hold time SINx ns SOT SCK SCKx, t delay time SOVLI SOTx 2tCYCP tCYCP ns Serial clock "L" pulse width t SLSH SCKx 2tCYCP tCYCP ns Serial clock "H" pulse width t SHSL SCKx tcycp tcycp ns SCK SOT SCKx, t SHOVE delay time SOTx External shift ns SIN SCK SCKx, clock t IVSLE setup time SINx operation ns SCK SIN SCKx, t SLIXE hold time SINx ns SCK falling time tf SCKx ns SCK rising time tr SCKx ns Notes: The above characteristics apply to CLK synchronous mode. tcycp indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see Block Diagram in this datasheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. When the external load capacitance CL = 30pF. Document Number: Rev.*B Page 103 of 168

104 tscyc SCK tsovli VOL VOH tshovi VOL SOT VOH VOL VOH VOL tivsli tslixi SIN VIH VIL VIH VIL MS bit = 0 tslsh tshsl SCK VIH VIH VIH VIL VIL SOT * VOH VOL tf tr tshove VOH VOL tivsle tslixe SIN VIH VIL VIH VIL *: Changes when writing to TDR register MS bit = 1 Document Number: Rev.*B Page 104 of 168

105 Synchronous serial (SPI = 1, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin name Conditions VCC < 4.5V VCC 4.5V Min Max Min Max Unit Baud rate Mbps Serial clock cycle time t SCYC SCKx 4tCYCP - 4tCYCP - ns SCK SOT SCKx, t SLOVI ns delay time SOTx shift SIN SCK SCKx, t IVSHI clock ns setup time SINx operation SCK SIN SCKx, t SHIXI ns hold time SINx SOT SCK SCKx, t delay time SOVHI SOTx 2tCYCP tCYCP ns Serial clock "L" pulse width t SLSH SCKx 2tCYCP tCYCP ns Serial clock "H" pulse width t SHSL SCKx tcycp tcycp ns SCK SOT SCKx, t SLOVE delay time SOTx External shift ns SIN SCK SCKx, clock t IVSHE setup time SINx operation ns SCK SIN SCKx, t SHIXE hold time SINx ns SCK falling time tf SCKx ns SCK rising time tr SCKx ns Notes: The above characteristics apply to CLK synchronous mode. tcycp indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see Block Diagram in this datasheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. When the external load capacitance CL = 30pF. Document Number: Rev.*B Page 105 of 168

106 tscyc SCK VOH VOL VOH tsovhi tslovi SOT VOH VOL VOH VOL tivshi tshixi SIN VIH VIL VIH VIL MS bit = 0 SCK tr tshsl tslsh tf VIL VIH VIH VIL VIL VIH tslove SOT VOH VOH VOL VOL tivshe tshixe SIN VIH VIL VIH VIL MS bit = 1 Document Number: Rev.*B Page 106 of 168

107 When using synchronous serial chip select (SCINV = 0, CSLVL=1) (VCC = 2.7V to 5.5V, VSS = 0V) SCS SCK setup time VCC < 4.5V VCC 4.5V Parameter Symbol Conditions Unit Min Max Min Max t CSSI (*1)-50 (*1)+0 (*1)-50 (*1)+0 ns SCK SCS hold time t CSHI shift (*2)+0 (*2)+50 (*2)+0 (*2)+50 ns clock operation (*3)-50 (*3)+50 (*3)-50 (*3)+50 SCS deselect time ns SCS SCK setup time t CSDI t CSSE +5tCYCP +5tCYCP +5tCYCP +5tCYCP 3tCYCP+30-3tCYCP+30 - ns SCK SCS hold time t CSHE ns SCS deselect time t CSDE External shift clock operation 3tCYCP+30-3tCYCP+30 - ns SCS SUT delay time t DSE ns SCS SUT delay time t DEE ns (*1): CSSU bit value serial chip select timing operating clock cycle [ns] (*2): CSHD bit value serial chip select timing operating clock cycle [ns] (*3): CSDS bit value serial chip select timing operating clock cycle [ns] Notes: tcycp indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see Block Diagram in this datasheet. About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual. When the external load capacitance CL = 30pF. Document Number: Rev.*B Page 107 of 168

108 SCS output tcssi tcshi tcsdi SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 SCS input tcsde tcsse tcshe SCK input tdee SOT (SPI=0) tdse SOT (SPI=1) MS bit = 1 Document Number: Rev.*B Page 108 of 168

109 When using synchronous serial chip select (SCINV = 1, CSLVL=1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions VCC < 4.5V VCC 4.5V Min Max Min Max SCS SCK setup time t CSSI (*1)-50 (*1)+0 (*1)-50 (*1)+0 ns SCK SCS hold time t CSHI shift clock (*2)+0 (*2)+50 (*2)+0 (*2)+50 ns SCS deselect time operation (*3)-50 (*3)+50 (*3)-50 (*3)+50 ns SCS SCK setup time t CSDI t CSSE +5tCYCP +5tCYCP +5tCYCP +5tCYCP SCK SCS hold time t CSHE External shift ns SCS deselect time t CSDE clock 3tCYCP+30-3tCYCP+30 - ns SCS SOT delay time t DSE operation ns Unit 3tCYCP+30-3tCYCP+30 - ns SCS SOT delay time t DEE ns (*1): CSSU bit value serial chip select timing operating clock cycle [ns] (*2): CSHD bit value serial chip select timing operating clock cycle [ns] (*3): CSDS bit value serial chip select timing operating clock cycle [ns] Notes: tcycp indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see Block Diagram in this datasheet. About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual. When the external load capacitance CL = 30pF. Document Number: Rev.*B Page 109 of 168

110 SCS output tcssi tcshi tcsdi SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 SCS input tcsde tcsse tcshe SCK input tdee SOT (SPI=0) tdse SOT (SPI=1) MS bit = 1 Document Number: Rev.*B Page 110 of 168

111 When using synchronous serial chip select (SCINV = 0, CSLVL=0) (VCC = 2.7V to 5.5V, VSS = 0V) VCC < 4.5V VCC 4.5V Parameter Symbol Conditions Unit Min Max Min Max SCS SCK setup time t CSSI (*1)-50 (*1)+0 (*1)-50 (*1)+0 ns SCK SCS hold time t CSHI shift (*2)+0 (*2)+50 (*2)+0 (*2)+50 ns clock operation (*3)-50 (*3)+50 (*3)-50 (*3)+50 SCS deselect time ns SCS SCK setup time t CSDI t CSSE +5tCYCP +5tCYCP +5tCYCP +5tCYCP 3tCYCP+30-3tCYCP+30 - ns SCK SCS hold time t CSHE ns SCS deselect time t CSDE External shift clock operation 3tCYCP+30-3tCYCP+30 - ns SCS SOT delay time t DSE ns SCS SOT delay time t DEE ns (*1): CSSU bit value serial chip select timing operating clock cycle [ns] (*2): CSHD bit value serial chip select timing operating clock cycle [ns] (*3): CSDS bit value serial chip select timing operating clock cycle [ns] Notes: tcycp indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see Block Diagram in this datasheet. About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual. When the external load capacitance CL = 30pF. Document Number: Rev.*B Page 111 of 168

112 tcsdi SCS output tcssi tcshi SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 tcsde SCS input tcsse tcshe SCK input tdee SOT (SPI=0) tdse SOT (SPI=1) MS bit = 1 Document Number: Rev.*B Page 112 of 168

113 When using synchronous serial chip select (SCINV = 1, CSLVL=0) (VCC = 2.7V to 5.5V, VSS = 0V) VCC < 4.5V VCC 4.5V Parameter Symbol Conditions Unit Min Max Min Max SCS SCK setup time t CSSI (*1)-50 (*1)+0 (*1)-50 (*1)+0 ns SCK SCS hold time t CSHI shift (*2)+0 (*2)+50 (*2)+0 (*2)+50 ns clock operation (*3)-50 (*3)+50 (*3)-50 (*3)+50 SCS deselect time ns SCS SCK setup time t CSDI t CSSE +5tCYCP +5tCYCP +5tCYCP +5tCYCP 3tCYCP+30-3tCYCP+30 - ns SCK SCS hold time t CSHE ns SCS deselect time t CSDE External shift clock operation 3tCYCP+30-3tCYCP+30 - ns SCS SOT delay time t DSE ns SCS SOT delay time t DEE ns (*1): CSSU bit value serial chip select timing operating clock cycle [ns] (*2): CSHD bit value serial chip select timing operating clock cycle [ns] (*3): CSDS bit value serial chip select timing operating clock cycle [ns] Notes: tcycp indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see Block Diagram in this datasheet. About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual. When the external load capacitance CL = 30pF. Document Number: Rev.*B Page 113 of 168

114 tcsdi SCS output tcssi tcshi SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 SCS input tcsse tcshe tcsde SCK input tdee SOT (SPI=0) tdse SOT (SPI=1) MS bit = 1 Document Number: Rev.*B Page 114 of 168

115 High-speed synchronous serial (SPI = 0, SCINV = 0) Parameter Symbol Pin name Conditions Serial clock cycle time t SCYC SCKx (VCC = 2.7V to 5.5V, VSS = 0V) VCC < 4.5V VCC 4.5V Unit Min Max Min Max 4tCYCP - 4tCYCP - ns SCK SOT delay time SIN SCK setup time t SLOVI t IVSHI SCKx, SOTx SCKx, SINx shift clock operation ns * ns SCK SIN hold time t SHIXI SCKx, SINx ns Serial clock "L" pulse width t SLSH SCKx 2tCYCP 5-2tCYCP 5 - ns Serial clock "H" pulse width t SHSL SCKx tcycp tcycp ns SCK SOT delay time SIN SCK setup time t SLOVE t IVSHE SCKx, SOTx SCKx, SINx External shift clock operation ns ns SCK SIN hold time t SHIXE SCKx, ns SINx SCK falling time tf SCKx ns SCK rising time tr SCKx ns Notes: The above characteristics apply to CLK synchronous mode. tcycp indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see Block Diagram in this datasheet. These characteristics only guarantee the following pins. No chip select: SIN4_1, SOT4_1, SCK4_1 Chip select: SIN6_1, SOT6_1, SCK6_1, SCS6_1 When the external load capacitance CL = 30pF. (For *, when CL = 10pF) Document Number: Rev.*B Page 115 of 168

116 tscyc SCK VOL VOH VOL t SLOVI SOT VOH VOL SIN VIH VIL tivshi tshixi VIH VIL MS bit = 0 tslsh tshsl SCK VIH tf VIL t SLOVE VIL VIH tr VIH SOT VOH VOL SIN tivshe VIH VIL MS bit = 1 tshixe VIH VIL Document Number: Rev.*B Page 116 of 168

117 High-speed synchronous serial (SPI = 0, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin name Conditions VCC < 4.5V VCC 4.5V Min Max Min Max Unit Serial clock cycle time t SCYC SCKx 4tCYCP - 4tCYCP - ns SCK SOT delay time SIN SCK setup time t SHOVI t IVSLI SCKx, SOTx SCKx, SINx shift clock operation ns * ns SCK SIN hold time t SLIXI SCKx, SINx ns Serial clock "L" pulse width t SLSH SCKx 2tCYCP 5-2tCYCP 5 - ns Serial clock "H" pulse width t SHSL SCKx tcycp tcycp ns SCK SOT delay time t SHOVE SCKx, SOTx ns SIN SCK setup time t IVSLE SCKx, SINx External shift clock operation ns SCK SIN hold time t SLIXE SCKx, SINx ns SCK falling time tf SCKx ns SCK rising time tr SCKx ns Notes: The above characteristics apply to CLK synchronous mode. tcycp indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see Block Diagram in this datasheet. These characteristics only guarantee the following pins. No chip select: SIN4_1, SOT4_1, SCK4_1 Chip select: SIN6_1, SOT6_1, SCK6_1, SCS6_1 When the external load capacitance CL = 30pF. (For *, when CL = 10pF) Document Number: Rev.*B Page 117 of 168

118 tscyc SCK VOH VOH VOL t SHOVI SOT VOH VOL SIN VIH VIL tivsli tslixi VIH VIL MS bit = 0 tshsl tslsh SCK VIH VIH tr VIL t SHOVE tf VIL VIL SOT VOH VOL tivsle tslixe SIN VIH VIL VIH VIL MS bit = 1 Document Number: Rev.*B Page 118 of 168

119 High-speed synchronous serial (SPI = 1, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin name Conditions VCC < 4.5V VCC 4.5V Min Max Min Max Unit Serial clock cycle time t SCYC SCKx 4tCYCP - 4tCYCP - ns SCK SOT delay time t SHOVI SCKx, SOTx ns SIN SCK setup time t IVSLI SCKx, SINx shift clock operation * ns SCK SIN hold time t SLIXI SCKx, SINx ns SOT SCK delay time t SOVLI SCKx, SOTx 2tCYCP 10-2tCYCP 10 - ns Serial clock "L" pulse width t SLSH SCKx 2tCYCP 5-2tCYCP 5 - ns Serial clock "H" pulse width t SHSL SCKx tcycp tcycp ns SCK SOT delay time t SHOVE SCKx, SOTx ns SIN SCK setup time t IVSLE SCKx, SINx External shift clock operation ns SCK SIN hold time t SLIXE SCKx, SINx ns SCK falling time tf SCKx ns SCK rising time tr SCKx ns Notes: The above characteristics apply to CLK synchronous mode. tcycp indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see Block Diagram in this datasheet. These characteristics only guarantee the following pins. No chip select: SIN4_1, SOT4_1, SCK4_1 Chip select: SIN6_1, SOT6_1, SCK6_1, SCS6_1 When the external load capacitance CL = 30pF. (For *, when CL = 10pF) Document Number: Rev.*B Page 119 of 168

120 tscyc SCK tsovli VOL VOH tshovi VOL SOT VOH VOL VOH VOL tivsli tslixi SIN VIH VIL VIH VIL MS bit = 0 tslsh tshsl SCK VIH VIH VIH VIL VIL SOT * VOH VOL tf tr tshove VOH VOL tivsle tslixe SIN VIH VIL VIH VIL *: Changes when writing to TDR register MS bit = 1 Document Number: Rev.*B Page 120 of 168

121 High-speed synchronous serial (SPI = 1, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin name Conditions VCC < 4.5V VCC 4.5V Min Max Min Max Unit shift clock operation t SCYC SCKx 4tCYCP - 4tCYCP - ns SCK SOT delay time t SLOVI SCKx, SOTx ns SIN SCK setup time t IVSHI SCKx, SINx shift clock operation * ns SCK SIN hold time t SHIXI SCKx, SINx ns SOT SCK delay time t SOVHI SCKx, SOTx 2tCYCP 10-2tCYCP 10 - ns Serial clock "L" pulse width t SLSH SCKx 2tCYCP 5-2tCYCP 5 - ns Serial clock "H" pulse width t SHSL SCKx tcycp tcycp ns SCK SOT delay time t SLOVE SCKx, SOTx ns SIN SCK setup time t IVSHE SCKx, SINx External shift clock operation ns SCK SIN hold time t SHIXE SCKx, SINx ns SCK falling time tf SCKx ns SCK rising time tr SCKx ns Notes: The above characteristics apply to CLK synchronous mode. tcycp indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see Block Diagram in this datasheet. These characteristics only guarantee the following pins. No chip select: SIN4_1, SOT4_1, SCK4_1 Chip select: SIN6_1, SOT6_1, SCK6_1, SCS6_1 When the external load capacitance CL = 30pF. (For *, when CL = 10pF) Document Number: Rev.*B Page 121 of 168

122 tscyc SCK VOH VOL VOH tsovhi tslovi SOT VOH VOL VOH VOL tivshi tshixi SIN VIH VIL VIH VIL MS bit = 0 tr tshsl tslsh tf SCK VIL VIH VIH VIL VIL VIH tslove SOT VOH VOL VOH VOL tivshe tshixe SIN VIH VIL VIH VIL MS bit = 1 Document Number: Rev.*B Page 122 of 168

123 When using high-speed synchronous serial chip select (SCINV = 0, CSLVL=1) (VCC = 2.7V to 5.5V, VSS = 0V) VCC < 4.5V VCC 4.5V Parameter Symbol Conditions Unit Min Max Min Max SCS SCK setup time t CSSI (*1)-20 (*1)+0 (*1)-20 (*1)+0 ns SCK SCS hold time t CSHI shift clock (*2)+0 (*2)+20 (*2)+0 (*2)+20 ns operation (*3)-20 (*3)+20 (*3)-20 (*3)+20 SCS deselect time ns SCS SCK setup time t CSDI t CSSE +5tCYCP +5tCYCP +5tCYCP +5tCYCP 3tCYCP+15-3tCYCP+15 - ns SCK SCS hold time t CSHE ns SCS deselect time t CSDE External shift clock operation 3tCYCP+15-3tCYCP+15 - ns SCS SOT delay time t DSE ns SCS SOT delay time t DEE ns (*1): CSSU bit value serial chip select timing operating clock cycle [ns] (*2): CSHD bit value serial chip select timing operating clock cycle [ns] (*3): CSDS bit value serial chip select timing operating clock cycle [ns] Notes: tcycp indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see Block Diagram in this datasheet. About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual. When the external load capacitance CL = 30pF. Document Number: Rev.*B Page 123 of 168

124 SCS output tcssi tcshi tcsdi SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 SCS input tcsde tcsse tcshe SCK input tdee SOT (SPI=0) tdse SOT (SPI=1) MS bit = 1 Document Number: Rev.*B Page 124 of 168

125 When using high-speed synchronous serial chip select (SCINV = 1, CSLVL=1) (VCC = 2.7V to 5.5V, VSS = 0V) VCC < 4.5V VCC 4.5V Parameter Symbol Conditions Unit Min Max Min Max SCS SCK setup time t CSSI (*1)-20 (*1)+0 (*1)-20 (*1)+0 ns SCK SCS hold time t CSHI shift clock (*2)+0 (*2)+20 (*2)+0 (*2)+20 ns operation (*3)-20 (*3)+20 (*3)-20 (*3)+20 SCS deselect time ns SCS SCK setup time t CSDI t CSSE +5tCYCP +5tCYCP +5tCYCP +5tCYCP 3tCYCP+15-3tCYCP+15 - ns SCK SCS hold time t CSHE ns SCS deselect time t CSDE External shift clock operation 3tCYCP+15-3tCYCP+15 - ns SCS SOT delay time t DSE ns SCS SOT delay time t DEE ns (*1): CSSU bit value serial chip select timing operating clock cycle [ns] (*2): CSHD bit value serial chip select timing operating clock cycle [ns] (*3): CSDS bit value serial chip select timing operating clock cycle [ns] Notes: tcycp indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see Block Diagram in this datasheet. About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual. When the external load capacitance CL = 30pF. Document Number: Rev.*B Page 125 of 168

126 SCS output tcssi tcshi tcsdi SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 SCS input tcsde tcsse tcshe SCK input tdee SOT (SPI=0) tdse SOT (SPI=1) MS bit = 1 Document Number: Rev.*B Page 126 of 168

127 When using high-speed synchronous serial chip select (SCINV = 0, CSLVL=0) (VCC = 2.7V to 5.5V, VSS = 0V) VCC < 4.5V VCC 4.5V Parameter Symbol Conditions Unit Min Max Min Max SCS SCK setup time t CSSI (*1)-20 (*1)+0 (*1)-20 (*1)+0 ns SCK SCS hold time t CSHI shift clock (*2)+0 (*2)+20 (*2)+0 (*2)+20 ns operation (*3)-20 (*3)+20 (*3)-20 (*3)+20 SCS deselect time ns SCS SCK setup time t CSDI t CSSE +5tCYCP +5tCYCP +5tCYCP +5tCYCP 3tCYCP+15-3tCYCP+15 - ns SCK SCS hold time t CSHE ns SCS deselect time t CSDE External shift clock operation 3tCYCP+15-3tCYCP+15 - ns SCS SOT delay time t DSE ns SCS SOT delay time t DEE ns (*1): CSSU bit value serial chip select timing operating clock cycle [ns] (*2): CSHD bit value serial chip select timing operating clock cycle [ns] (*3): CSDS bit value serial chip select timing operating clock cycle [ns] Notes: tcycp indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see Block Diagram in this datasheet. About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual. When the external load capacitance CL = 30pF. Document Number: Rev.*B Page 127 of 168

128 tcsdi SCS output tcssi tcshi SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 tcsde SCS input tcsse tcshe SCK input tdee SOT (SPI=0) tdse SOT (SPI=1) MS bit = 1 Document Number: Rev.*B Page 128 of 168

129 When using high-speed synchronous serial chip select (SCINV = 1, CSLVL=0) (VCC = 2.7V to 5.5V, VSS = 0V) VCC < 4.5V VCC 4.5V Parameter Symbol Conditions Unit Min Max Min Max SCS SCK setup time t CSSI (*1)-20 (*1)+0 (*1)-20 (*1)+0 ns SCK SCS hold time t CSHI shift clock (*2)+0 (*2)+20 (*2)+0 (*2)+20 ns operation (*3)-20 (*3)+20 (*3)-20 (*3)+20 SCS deselect time ns SCS SCK setup time t CSDI t CSSE +5tCYCP +5tCYCP +5tCYCP +5tCYCP 3tCYCP+15-3tCYCP+15 - ns SCK SCS hold time t CSHE ns SCS deselect time t CSDE External shift clock operation 3tCYCP+15-3tCYCP+15 - ns SCS SOT delay time t DSE ns SCS SOT delay time t DEE ns (*1): CSSU bit value serial chip select timing operating clock cycle [ns] (*2): CSHD bit value serial chip select timing operating clock cycle [ns] (*3): CSDS bit value serial chip select timing operating clock cycle [ns] Notes: tcycp indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see Block Diagram in this datasheet. About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual. When the external load capacitance CL = 30pF. Document Number: Rev.*B Page 129 of 168

130 tcsdi SCS output tcssi tcshi SCK output SOT (SPI=0) SOT (SPI=1) MS bit = 0 SCS input tcsse tcshe tcsde SCK input tdee SOT (SPI=0) tdse SOT (SPI=1) MS bit = 1 Document Number: Rev.*B Page 130 of 168

131 External clock (EXT = 1) : when in asynchronous mode only Parameter Symbol Condition Min Value Serial clock "L" pulse width t SLSH tcycp ns Serial clock "H" pulse width t SHSL C L = 30pF tcycp ns SCK falling time tf - 5 ns SCK rising time tr - 5 ns Max (VCC = 2.7V to 5.5V, VSS = 0V) Unit Remarks SCK tr tshsl tslsh V IH V IH V IH V IL V IL V IL tf Document Number: Rev.*B Page 131 of 168

132 External Input Timing Parameter Symbol Pin name Conditions Input pulse width t INH, t INL ADTG FRCKx ICxx Min Value Max (VCC = 2.7V to 5.5V, VSS = 0V) Unit - 2tCYCP* 1 - ns Remarks A/D converter trigger input Free-run timer input clock Input capture DTTIxX - 2tCYCP* 1 - ns Waveform generator INT00 to INT31, NMIX - 2tCYCP + 100* 1 - ns 500* 2 - ns External interrupt, NMI WKUPx - 500* 3 - ns Deep standby wake up *1: tcycp indicates the APB bus clock cycle time except stop when in STOP mode, in timer mode. About the APB bus number which the A/D converter, Multi-function Timer, External interrupt are connected to, see Block Diagram in this data sheet. *2: When in STOP mode, in timer mode. *3: When in deep standby RTC mode, in deep standby STOP mode. Document Number: Rev.*B Page 132 of 168

133 Quadrature Position/Revolution Counter Timing Parameter Symbol Conditions AIN pin "H" width t AHL - AIN pin "L" width t ALL - BIN pin "H" width t BHL - BIN pin "L" width t BLL - BIN rising time from AIN pin "H" level t AUBU PC_Mode2 or PC_Mode3 AIN falling time from BIN pin "H" level t BUAD PC_Mode2 or PC_Mode3 BIN falling time from AIN pin "L" level t ADBD PC_Mode2 or PC_Mode3 AIN rising time from BIN pin "L" level t BDAU PC_Mode2 or PC_Mode3 AIN rising time from BIN pin "H" level t BUAU PC_Mode2 or PC_Mode3 BIN falling time from AIN pin "H" level t AUBD PC_Mode2 or PC_Mode3 AIN falling time from BIN pin "L" level t BDAD PC_Mode2 or PC_Mode3 BIN rising time from AIN pin "L" level t ADBU PC_Mode2 or PC_Mode3 ZIN pin "H" width t ZHL QCR:CGSC="0" ZIN pin "L" width t ZLL QCR:CGSC="0" AIN/BIN rising and falling time from determined ZIN level t ZABE QCR:CGSC="1" Determined ZIN level from AIN/BIN rising and falling time t ABEZ QCR:CGSC="1" Min (VCC = 2.7V to 5.5V, VSS = 0V) Value Max Unit 2tCYCP* - ns *: tcycp indicates the APB bus clock cycle time except stop when in STOP mode, in timer mode. About the APB bus number which Quadrature Position/Revolution Counter is connected to, see Block Diagram in this data sheet. tahl tall AIN taubu tbuad tadbd tbdau BIN tbhl tbll Document Number: Rev.*B Page 133 of 168

134 tbhl tbll BIN tbuau taubd tbdad tadbu AIN tahl tall ZIN ZIN AIN/BIN Document Number: Rev.*B Page 134 of 168

135 I 2 C Timing Standard-mode, Fast-mode Parameter Symbol Conditions SCL clock frequency (Repeated) START condition hold time SDA SCL SCL clock "L" width SCL clock "H" width (Repeated) START condition setup time SCL SDA Data hold time SCL SDA Data setup time SDA SCL STOP condition setup time SCL SDA Bus free time between "STOP condition" and "START condition" F SCL Standard-mode Fast-mode Min Max Min Max C L = 30pF, t HDDAT R = (Vp/I OL)* * * 3 μs (VCC = 2.7V to 5.5V, VSS = 0V) Unit khz t HDSTA μs t LOW μs t HIGH μs t SUSTA μs t SUDAT ns t SUSTO μs t BUF μs Remarks Document Number: Rev.*B Page 135 of 168

136 Parameter Symbol Conditions Noise filter t SP 2MHz t CYCP<40MHz 40MHz t CYCP<60MHz 60MHz t CYCP<80MHz 80MHz t CYCP<100MHz 100MHz t CYCP<120MHz 120MHz t CYCP<140MHz 140MHz t CYCP<160MHz 160MHz t CYCP<180MHz Typical mode High-speed mode Min Max Min Max Unit 2tCYCP* 4-2tCYCP* 4 - ns 4tCYCP* 4-4tCYCP* 4 - ns 6tCYCP* 4-6tCYCP* 4 - ns 8tCYCP* 4-8tCYCP* 4 - ns 10tCYCP* 4-10tCYCP* 4 - ns 12tCYCP* 4-12tCYCP* 4 - ns 14tCYCP* 4-14tCYCP* 4 - ns 16tCYCP* 4-16tCYCP* 4 - ns *5 Remarks *1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current. *2: The maximum thddat must satisfy that it does not extend at least "L" period (tlow) of device's SCL signal. *3: A Fast-mode I 2 C bus device can be used on a Standard-mode I 2 C bus system as long as the device satisfies the requirement of "tsudat 250 ns". *4: tcycp is the APB bus clock cycle time. About the APB bus number that I 2 C is connected to, see Block Diagram in this data sheet. *5: The noise filter time can be changed by register settings. Change the number of the noise filter steps according to APB bus clock frequency. Document Number: Rev.*B Page 136 of 168

137 Fast-mode Plus (Fm+) Parameter Symbol Conditions Fast-mode Plus (Fm+)* 6 SCL clock frequency F SCL khz (Repeated) START condition hold time t HDSTA μs SDA SCL SCL clock "L" width t LOW μs SCL clock "H" width t HIGH μs SCL clock frequency t SUSTA μs (Repeated) START condition hold time t HDDAT C L = 30pF, R = (Vp/I OL) * * 2, * 3 μs SDA SCL Data setup time SDA SCL t SUDAT 50 - ns STOP condition setup time SCL SDA t SUSTO μs Bus free time between "STOP condition" and "START condition" t BUF μs 60MHz t CYCP<80MHz 6 tcycp * 4 - ns 80MHz t CYCP<100MHz 8 tcycp * 4 - ns Noise filter t SP 100MHz t CYCP<120MHz 10 tcycp * 4 - ns 120MHz t CYCP<140MHz 12 tcycp * 4 - ns 140MHz t CYCP<160MHz 14 tcycp * 4 - ns 160MHz t CYCP<180MHz 16 tcycp * 4 - ns Min Max (VCC = 2.7V to 5.5V, VSS = 0V) Unit *5 Remarks *1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current. *2: The maximum thddat must satisfy that it does not extend at least "L" period (tlow) of device's SCL signal. *3: A Fast-mode mode I 2 C bus device can be used on a Standard-mode I 2 C bus system as long as the device satisfies the requirement of "tsudat 250 ns". *4: tcycp is the APB bus clock cycle time. About the APB bus number that I 2 C is connected to, see Block Diagram in this data sheet. To use Fast-mode Plus (Fm+), set the peripheral bus clock at 64 MHz or more. *5: The noise filter time can be changed by register settings. Change the number of the noise filter steps according to APB bus clock frequency. *6: When using Fast-mode Plus (Fm+), set the I/O pin to the mode corresponding to I 2 C Fm+ in the EPFR register. See Chapter: I/O Port in FM4 Family Peripheral Manual for the details. SDA SCL Document Number: Rev.*B Page 137 of 168

138 SD Card Interface Timing Default-Speed Mode Clock CLK (All values are referred to VIH and VIL) Parameter Symbol Pin name Conditions Clock frequency Data Transfer Mode f PP S_CLK Min Value (VCC = 2.7V to 3.6V, VSS = 0V) Max Unit 0 16 MHz Clock frequency f OD S_CLK Identification Mode C CARD 10pF 0*/ khz Clock low time t WL S_CLK (1card) 10 - ns Clock high time t WH S_CLK 10 - ns Clock rising time t TLH S_CLK - 10 ns Clock falling time t THL S_CLK - 10 ns *: 0Hz means to stop the clock. The given minimum frequency range is for cases were continues clock is required. Card Inputs CMD, DAT (referenced to Clock CLK) Parameter Symbol Pin name Conditions Input set-up time Input hold time t ISU t IH S_CMD, S_DATA3:0 S_CMD, S_DATA3:0 C CARD 10pF (1card) Value Min Max Unit 5 - ns 5 - ns Card Outputs CMD, DAT (referenced to Clock CLK) Parameter Symbol Pin name Conditions Output Delay time during Data Transfer Mode Output Delay time durinn Identification Mode t ODLY t ODLY S_CMD, S_DATA3:0 S_CMD, S_DATA3:0 C CARD 40pF (1card) Value Min Max Unit 0 22 ns 0 50 ns twl twh S_CLK (SD Clock) S_CMD, S_DATA3:0 (Card Input) VIH tthl VIL todly(max) tisu VIL VIH VIL VIH ttlh VIH VIL tih todly(min) VIH S_CMD, S_DATA3:0 (Card Output) VOH VOL VOH VOL Defalt-Speed Mode Note: The Card Input corresponds to the Host Output and the Card Output corresponds to the Host Input because this model is the Host. Document Number: Rev.*B Page 138 of 168

139 High-Speed Mode Clock CLK (All values are referred to VIH and VIL) (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin name Conditions Value Min Max Unit Clock frequency Data Transfer Mode f PP S_CLK 0 32 MHz Clock low time t WL S_CLK C CARD 10pF 7 - ns Clock high time t WH S_CLK (1card) 7 - ns Clock rising time t TLH S_CLK - 3 ns Clock falling time t THL S_CLK - 3 ns Card Inputs CMD, DAT (referenced to Clock CLK) Parameter Symbol Pin name Conditions Input set-up time Input hold time t ISU t IH S_CMD, S_DATA3:0 S_CMD, S_DATA3:0 C CARD 10pF (1card) Value Min Max Unit 8 - ns 2 - ns Card Outputs CMD, DAT (referenced to Clock CLK) Parameter Symbol Pin name Conditions Output Delay time during Data Transfer Mode Output Hold time Total System capacitance for each line* t ODLY t OH S_CMD, S_DATA3:0 S_CMD, S_DATA3:0 C L 40pF (1card) C L 15pF (1card) Min Value Max Unit - 22 ns ns C L - 1card - 40 pf *: In order to satisfy severe timing, host shall drive only one card. twl twh S_CLK (SD Clock) S_CMD, S_DATA3:0 (Card Input) 50%V CC todly(max) VIH tthl VIL tisu VIH VIL VIL VIH ttlh tih VIH VIL toh(min) 50%V CC VIH S_CMD, S_DATA3:0 (Card Output) VOH VOL VOH VOL High-Speed Mode Notes: The Card Input corresponds to the Host Output and the Card Output corresponds to the Host Input because this model is the Host. In high-speed mode, set the Clock frequency (fpp) and the AHB Bus Clock frequency to the same values. Document Number: Rev.*B Page 139 of 168

140 ETM Timing Parameter Symbol Pin name Conditions Data hold t ETMH TRACECLK, TRACED[3:0] Min Value Max V CC 4.5V 2 9 V CC < 4.5V 2 15 (VCC = 2.7V to 5.5V, VSS = 0V) Unit ns Remarks TRACECLK frequency TRACECLK clock cycle 1/ t TRACE t TRACE TRACECLK V CC 4.5V - 50 MHz V CC < 4.5V - 32 MHz V CC 4.5V 20 - ns V CC < 4.5V ns Note: When the external load capacitance CL= 30pF. HCLK TRACECLK TRACED[3:0] Document Number: Rev.*B Page 140 of 168

141 JTAG Timing Parameter Symbol Pin name Conditions TMS, TDI setup time TMS, TDI hold time TDO delay time t JTAGS t JTAGH t JTAGD TCK, TMS, TDI TCK, TMS, TDI TCK, TDO Note: When the external load capacitance CL= 30pF. V CC 4.5V V CC < 4.5V Min Value Max (VCC = 2.7V to 5.5V, VSS = 0V) Unit 15 - ns V CC 4.5V 15 - ns V CC < 4.5V V CC 4.5V - 25 ns V CC < 4.5V - 45 Remarks TCK TMS/TDI TDO Document Number: Rev.*B Page 141 of 168

142 bit A/D Converter Electrical Characteristics for the A/D Converter (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V) Parameter Symbol Pin Value name Min Typ Max Unit Resolution bit Integral Nonlinearity LSB Differential Nonlinearity LSB Zero transition voltage V ZT ANxx mv Full-scale transition voltage V FST ANxx AVRH AVRH + 15 mv Remarks AVRH = 2.7V to 5.5V Conversion time * μs AV CC 4.5V Sampling time * 2 Ts - Compare clock cycle * 3 State transition time to operation permission Power supply current (analog + digital) Reference power supply current (AVRH) Analog input capacity Analog input resistance Interchannel disparity Analog port input leak current Analog input voltage Reference voltage Tcck AV CC 4.5V 10 μs AV CC < 4.5V AV CC 4.5V ns AV CC < 4.5V Tstt μs A/D 1unit ma - AVCC operation μa When A/D stop A/D 1unit - AVRH ma operation AVRH=5.5V μa When A/D stop C AIN pf R AIN AV CC 4.5V kω 1.8 AV CC < 4.5V LSB - ANxx μa - ANxx AVSS - AVRH V - AVRH AVCC Tcck < 50ns V AVCC Tcck 50ns *1: The conversion time is the value of sampling time (Ts) + compare time (Tc). The condition of the minimum conversion time is when the value of sampling time: 150ns, the value of compare time: 350ns (AVCC 4.5V). Ensure that it satisfies the value of sampling time (Ts) and compare clock cycle (Tcck). For setting* 4 of sampling time and compare clock cycle, see "Chapter: A/D Converter" in "FM4 Family Peripheral Manual Analog Macro Part". The register setting of the A/D Converter is reflected by the peripheral clock timing. The sampling and compare clock are set at Base clock (HCLK). *2: A necessary sampling time changes by external impedance. Ensure that it set the sampling time to satisfy (Equation 1). *3: The compare time (Tc) is the value of (Equation 2). *4: The register setting of the A/D Converter is reflected by the timing of the APB bus clock. The sampling clock and compare clock are set in base clock (HCLK). About the APB bus number which the A/D Converter is connected to, see Block Diagram in this data sheet. Document Number: Rev.*B Page 142 of 168

143 Analog signal source Rext ANxx Analog input pin RAIN Comparator CAIN (Equation 1) Ts (RAIN + Rext ) CAIN 9 Ts: Sampling time RAIN: Input resistance of A/D = 1.2kΩ at 4.5V < AVCC < 5.5V Input resistance of A/D = 1.8kΩ at 2.7V < AVCC < 4.5V CAIN: Input capacity of A/D = 12.05pF at 2.7V < AVCC < 5.5V Rext: Output impedance of external circuit (Equation 2) Tc = Tcck 14 Tc: Compare time Tcck: Compare clock cycle Document Number: Rev.*B Page 143 of 168

144 Digital output Digital output MB9B360R Series Definition of 12-bit A/D Converter Terms Resolution: Analog variation that is recognized by an A/D converter. Integral Nonlinearity: Deviation of the line between the zero-transition point (0b b ) and the full-scale transition point (0b b ) from the actual conversion characteristics. Differential Nonlinearity: Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB. 0xFFF 0xFFE 0xFFD 0x004 0x003 0x002 0x001 Integral Nonlinearity Actual conversion characteristics {1 LSB(N-1) + VZT} (Actuallymeasured value) Actual conversion characteristics Ideal characteristics VZT VNT VFST (Actually-measured value) (Actually-measured value) 0x(N+1) 0xN 0x(N-1) 0x(N-2) Differential Nonlinearity Actual conversion characteristics Ideal characteristics VNT V(N+1)T (Actually-measured value) (Actually-measured value) Actual conversion characteristics AVss AVRH AVss AVRH Analog input Analog input Integral Nonlinearity of digital output N = V NT - {1LSB (N - 1) + V ZT} 1LSB [LSB] Differential Nonlinearity of digital output N = V (N + 1) T - V NT 1LSB - 1 [LSB] 1LSB = V FST - V ZT 4094 N: A/D converter digital output value. VZT: Voltage at which the digital output changes from 0x000 to 0x001. VFST: VNT: Voltage at which the digital output changes from 0xFFE to 0xFFF. Voltage at which the digital output changes from 0x(N 1) to 0xN. Document Number: Rev.*B Page 144 of 168

145 bit D/A Converter Electrical Characteristics for the D/A Converter Parameter Symbol Pin name Resolution - Conversion time Integral Nonlinearity* Differential Nonlinearity* Output voltage offset Analog output impedance Power supply current* *: During no load (VCC = AVCC = 2.7Vto5.5V, VSS = AVSS = 0V) Value Unit Min Typ Max bit DNL DAx LSB Remarks tc μs Load 20pF tc μs Load 100pF INL LSB V OFF R O IDDA AVCC mv When setting 0x mv When setting 0xFFF kω D/A operation MΩ When D/A stop μa D/A 1unit operation AV CC=3.3V μa D/A 1unit operation AV CC=5.0V IDSA μa When D/A stop Document Number: Rev.*B Page 145 of 168

146 12.7 USB Characteristics Input character -istics Output character -istics Parameter Symbol Pin name Conditions (VCC = 2.7V to 5.5V, USBVCC = 3.0V to 3.6V, VSS = 0V) Min Value Input "H" level voltage V IH USBVCC V *1 Input "L" level voltage V IL - VSS V *1 Differential input sensitivity V DI V *2 Different common mode range V CM V *2 Output "H" level External pull-down V OH voltage resistance = 15kΩ V *3 Output "L" level External pull-up V voltage OL UDP0,UDM0 resistance = 1.5kΩ V *3 Crossover voltage V CRS V *4 Rising time t FR Full-Speed 4 20 ns *5 Falling time t FF Full-Speed 4 20 ns *5 Rising/falling time matching t FRFM Full-Speed % *5 Output impedance Z DRV Full-Speed Ω *6 Rising time t LR Low-Speed ns *7 Falling time t LF Low-Speed ns *7 Rising/falling time matching t LRFM Low-Speed % *7 *1: The switching threshold voltage of Single-End-Receiver of USB I/O buffer is set as within VIL (Max) = 0.8 V, VIH (Min) = 2.0 V (TTL input standard). There are some hysteresis to lower noise sensitivity. *2: Use differential-receiver to receive USB differential data signal. Differential-Receiver has 200 mv of differential input sensitivity when the differential data input is within 0.8 V to 2.5 V to the local ground reference level. Above voltage range is the common mode input voltage range. Max Unit Remarks Minimum differential input sensitivity [V] Common mode input voltage [V] Document Number: Rev.*B Page 146 of 168

147 *3: The output drive capability of the driver is below 0.3 V at Low-State (VOL) (to 3.6 V and 1.5 kω load), and 2.8 V or above (to the VSS and 1.5 kω load) at High-State (VOH). *4: The cross voltage of the external differential output signal (D + /D ) of USB I/O buffer is within 1.3 V to 2.0 V. VCRS specified range *5: They indicate rising time (Trise) and falling time (Tfall) of the full-speed differential data signal. They are defined by the time between 10% and 90% of the output signal voltage. For full-speed buffer, Tr/Tf ratio is regulated as within ± 10% to minimize RFI emission. Rising time Falling time Document Number: Rev.*B Page 147 of 168

148 *6: USB Full-speed connection is performed via twist pair cable shield with 90Ω ± 15% characteristic impedance (Differential Mode). USB standard defines that output impedance of USB driver must be in range from 28Ω to 44Ω. So, discrete series resistor (Rs) addition is defined in order to satisfy the above definition and keep balance. When using this USB I/O, use it with 25Ω to 30Ω (recommendation value 27Ω) Series resistor Rs. 28Ω to 44Ω Equiv. Imped. 28Ω to 44Ω Equiv. Imped. Mount it as external resistance. Rs series resistor 25Ω to 30Ω Series resistor of 27Ω (recommendation value) must be added. And, use "resistance with an uncertainty of 5% by E24 sequence". *7: They indicate rising time (Trise) and falling time (Tfall) of the low-speed differential data signal. They are defined by the time between 10% and 90% of the output signal voltage. Rising time Falling time See Low-Speed Load (Compliance Load)" for conditions of external load. Document Number: Rev.*B Page 148 of 168

149 Low-Speed Load (Upstream Port Load) - Reference 1 CL = 50pF to 150pF CL = 50pF to 150pF Low-Speed Load (Downstream Port Load) - Reference 2 CL =200pF to 600pF CL =200pF to 600pF Low-Speed Load (Compliance Load) CL = 200pF to 450pF CL = 200pF to 450pF Document Number: Rev.*B Page 149 of 168