For More Information Please contact your local sales office for additional information about Cypress products and solutions.

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1 The following document contains information on Cypress products. The document has the series name, product name, and ordering part numbering with the prefix MB. However, Cypress will offer these products to new and existing customers with the series name, product name, and ordering part number with the prefix CY. How to Check the Ordering Part Number 1. Go to 2. nter the keyword (for example, ordering part number) in the SARCH PCNS field and click Apply. 3. Click the corresponding title from the search results. 4. Download the Affected Parts List file, which has details of all changes For More Information Please contact your local sales office for additional information about Cypress products and solutions. About Cypress Cypress is the leader in advanced embedded system solutions for the world's most innovative automotive, industrial, smart home appliances, consumer electronics and medical products. Cypress' microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable, high-performance memories help engineers design differentiated products and get them to market first. Cypress is committed to providing customers with the best support and development resources on the planet enabling them to disrupt markets by creating new product categories in record time. To learn more, go to

2 32-bit Arm Cortex -M3 FM3 Microcontroller The are highly integrated 32-bit microcontrollers dedicated for embedded controllers with low-power consumption mode and competitive cost. These series are based on the Arm Cortex -M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions such as various timers, ADCs, DACs and Communication Interfaces (USB, CAN, UART, CSIO, I 2 C, LIN). The products which are described in this data sheet are placed into TYP12 product categories in FM3 Family Peripheral Manual. Features 32-bit Arm Cortex -M3 Core Processor version: r2p1 Up to 60 MHz Frequency Operation Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels 24-bit System timer (Sys Tick): System timer for OS task management On-chip Memories [Flash memory] Dual operation Flash memory Main area: Up to 1.5 Mbytes (1008 Kbytes (ROM0) Kbytes (ROM1) of Upper bank and 16 Kbytes (ROM0) of Lower bank) Work area: 64 Kbytes (ROM1) of Lower bank Read cycle: 0 wait-cycle Security function for code protection [SRAM] This Series on-chip SRAM is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is connected to System bus. SRAM0: Up to 96 Kbytes SRAM1: Up to 96 Kbytes xternal Bus Interface Supports SRAM, NOR NAND Flash memory device Up to 8 chip selects 8-/16-bit Data width Up to 25-bit Address bit Maximum area size: Up to 256 Mbytes Supports Address/Data multiplex Supports external RDY function USB Interface The USB interface is composed of Device and Host. PLL for USB is built-in, USB clock can be generated by multiplication of Main clock. [USB Device] USB2.0 Full-Speed supported Max 6 ndpoint supported ndpoint 0 is control transfer ndpoint 1, 2 can select Bulk-transfer, Interrupt-transfer or Isochronous-transfer ndpoint 3 to 5 can select Bulk-transfer or Interrupt-transfer ndpoint 1 to 5 are comprised of Double Buffers. The size of each ndpoint is as follows. ndpoint 0, 2 to 5: 64 bytes ndpoint 1: 256 bytes [USB host] USB2.0 Full/Low-speed supported Bulk-transfer, interrupt-transfer and Isochronous-transfer support USB Device connected/dis-connected automatic detection Automatic processing of the IN/OUT token handshake packet Max 256-byte packet-length supported Wake-up function supported CAN Interface Compatible with CAN Specification 2.0A/B Maximum transfer rate: 1 Mbps Built-in 32 message buffer Cypress Semiconductor Corporation 198 Champion Court San Jose, CA Document Number: Rev. *D Revised January 12, 2018

3 Multi-function Serial Interface (Max 16 channels) 16 channels with 16 steps 9-bit FIFO Operation mode is selectable from the followings for each channel. UART CSIO LIN I 2 C [UART] Full duplex double buffer Selection with or without parity supported Built-in dedicated baud rate generator xternal clock available as a serial clock Hardware Flow control: Automatically control the transmission/reception by CTS/RTS (only ch.4) Various error detection functions available (parity errors, framing errors, and overrun errors) [CSIO] Full duplex double buffer Built-in dedicated baud rate generator Overrun error detection function available [LIN] LIN protocol Rev.2.1 supported Full duplex double buffer Master/Slave mode supported LIN break field generation (can be changed to 13 to 16-bit length) LIN break delimiter generation (can be changed to 1 to 4-bit length) Various error detection functions available (parity errors, framing errors, and overrun errors) [I 2 C] Standard - mode (Max 100 kbps) / Fast - mode (Max 400 kbps) supported DMA Controller (8 channels) The DMA Controller has an independent bus from the CPU, so CPU and DMA Controller can process simultaneously. 8 independently configured and operated channels Transfer can be started by software or request from the built-in peripherals Transfer address area: 32-bit (4 Gbytes) Transfer mode: Block transfer/burst transfer/demand transfer Transfer data type: byte/half-word/word Transfer block count: 1 to 16 Number of transfers: 1 to A/D Converter (Max 24 channels) [12-bit A/D Converter] Successive Approximation type Built-in 2units Conversion time: 2.7V to 5.5V Priority conversion available (priority at 2levels) Scanning conversion mode Built-in FIFO for conversion data storage (for SCAN conversion: 16 steps, for Priority conversion: 4 steps) D/A Converter (Max 2 channels) R-2R type 10-bit resolution Base Timer (Max 16 channels) Operation mode is selectable from the followings for each channel. 16-bit PWM timer 16-bit PPG timer 16-/32-bit reload timer 16-/32-bit PWC timer Document Number: Rev. *D Page 2 of 131

4 General-Purpose I/O Port This series can use its pins as general-purpose I/O ports when they are not used for external bus or peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function can be allocated to. Capable of pull-up control per pin Capable of reading pin level directly Built-in the port relocate function Up to 154 high-speed general-purpose I/O 176pin Package Some ports are 5V tolerant. See 4. List of Pin Functions and 5. I/O Circuit Type to confirm the corresponding pins. Dual Timer (32-/16-bit Down Counter) The Dual Timer consists of two programmable 32-/16-bit down counters. Operation mode is selectable from the followings for each channel. Free-running Periodic (=Reload) One-shot Quadrature Position/Revolution Counter (QPRC) (Max 2 channels) The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position encoder. Moreover, it is possible to use as the up/down counter. The detection edge of the three external event input pins AIN, BIN and ZIN is configurable. 16-bit position counter 16-bit revolution counter Two 16-bit compare registers HDMI-CC/Remote Control Reception (Up to 2 channels) HDMI-CC transmission Header block automatic transmission by judging Signal free Generating status interrupt by detecting Arbitration lost Generating START, OM, ACK automatically to output CC transmission by setting 1 byte data Generating transmission status interrupt when transmitting 1 block (1 byte data and OM/ACK) HDMI-CC reception Automatic ACK reply function available Line error detection function available Remote control reception 4 bytes reception buffer Repeat code detection function available Multi-function Timer The Multi-function timer is composed of the following blocks. 16-bit free-run timer 3 ch capture 4 ch Output compare 6 ch A/D activation compare 2 ch Waveform generator 3 ch 16-bit PPG timer 3 ch The following function can be used to achieve the motor control. PWM signal output function DC chopper waveform output function Dead time function capture function A/D convertor activate function DTIF (Motor emergency stop) interrupt function Real-time clock (RTC) The Real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 00 to 99. The interrupt function with specifying date and time (Year/Month/Day/Hour/Minute.) is available. This function is also available by specifying only Year, Month, Day, Hour or Minute. Timer interrupt function after set time or each set time. Capable of rewriting the time with continuing the time count. Leap year automatic count is available. Watch Counter The Watch counter is used for wake up from sleep and timer mode. Interval timer: up to 64 s Sub Clock: khz xternal Interrupt Controller Unit Up to 32 external interrupt input 176pin Package Include one non-maskable interrupt (NMI) input pin Watchdog Timer (2 channels) A watchdog timer can generate interrupts or a reset when a time-out value is reached. This series consists of two different watchdogs, a "Hardware" watchdog and a "Software" watchdog. The "Hardware" watchdog timer is clocked by the built-in low-speed CR oscillator. Therefore, the "Hardware" watchdog is active in any low-power consumption modes except RTC, STOP, Deep standby RTC, Deep standby STOP modes. Document Number: Rev. *D Page 3 of 131

5 CRC (Cyclic Redundancy Check) Accelerator The CRC accelerator calculates the CRC which has a heavy software processing load, and achieves a reduction of the integrity check processing load for reception data and storage. CCITT CRC16 and I CRC32 are supported. CCITT CRC16 Generator Polynomial: 0x1021 I CRC32 Generator Polynomial: 0x04C11DB7 Clock and Reset [Clocks] Selectable from five clock sources (2 external oscillators, 2 built-in CR oscillators, and Main PLL). Main Clock: Sub Clock: Built-in high-speed CR Clock: Built-in low-speed CR Clock: Main PLL Clock [Resets] Reset requests from INITX pin Power-on reset Software reset Watchdog timers reset Low-voltage detection reset Clock Super Visor reset 4 MHz to 48 MHz khz 4 MHz 100 khz Clock Super Visor (CSV) Clocks generated by built-in CR oscillators are used to supervise abnormality of the external clocks. If external clock failure (clock stop) is detected, reset is asserted. If external frequency anomaly is detected, interrupt or reset is asserted. Low-Voltage Detector (LVD) This Series includes 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the voltage that has been set, Low-Voltage Detector generates an interrupt or reset. LVD1: error reporting via interrupt LVD2: auto-reset operation Low-Power Consumption Mode Six low-power consumption modes supported. SLP TIMR RTC STOP Deep standby RTC (selectable between keeping the value of RAM and not) Deep standby STOP (selectable between keeping the value of RAM and not) Debug Serial Wire JTAG Debug Port (SWJ-DP) mbedded Trace Macrocell (TM) Unique ID Unique value of the device (41-bits) is set. Power Supply Wide range voltage: VCC = 2.7 V to 5.5 V : USBVCC = 3.0 V to 3.6 V (when USB is used) = 2.7 V to 5.5 V (when GPIO is used) Document Number: Rev. *D Page 4 of 131

6 Contents 1. Product Lineup Packages Pin Assignment List of Pin Functions I/O Circuit Type Handling Precautions Precautions for Product Design Precautions for Package Mounting Precautions for Use nvironment Handling Devices Block Diagram Memory Size Memory Map Pin Status in ach CPU State lectrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions DC Characteristics Current Rating Pin Characteristics AC Characteristics Main Clock Characteristics Sub Clock Characteristics Built-in CR Oscillation Characteristics Operating Conditions of Main and USB PLL (In the case of using main clock for input of PLL) Operating Conditions of Main PLL (In the case of using built-in high-speed CR for input clock of Main PLL) Reset Characteristics Power-on Reset Timing xternal Bus Timing Base Timer Timing CSIO/UART Timing xternal Timing Quadrature Position/Revolution Counter timing I 2 C Timing TM Timing JTAG Timing bit A/D Converter bit D/A Converter USB Characteristics Low-Voltage Detection Characteristics Low-Voltage Detection Reset Interrupt of Low-Voltage Detection Flash Memory Write/rase Characteristics Write / rase time Write cycles and data hold time Return Time from Low-Power Consumption Mode Document Number: Rev. *D Page 5 of 131

7 Return Factor: Interrupt/WKUP Return Factor: Reset Ordering Information Package Dimensions rrata Part Numbers Affected Qualification Status rrata Summary rrata Detail HDMI-CC polling message issue Major Changes Document History Sales, Solutions, and Legal Information Document Number: Rev. *D Page 6 of 131

8 MF Timer 1. Product Lineup Memory Size On-chip Flash memory On-chip SRAM Product name MB9BF528SA/TA MB9BF529SA/TA Main area 1 Mbytes 1.5 Mbytes Work area 64 Kbytes 64 Kbytes SRAM0 80 Kbytes 96 Kbytes SRAM1 80 Kbytes 96 Kbytes Total 160 Kbytes 192 Kbytes Function Product name MB9BF528SA MB9BF529SA Pin count /192 CPU Cortex-M3 Freq. 60 MHz Power supply voltage range 2.7 V to 5.5 V USB2.0 (Device/Host) 1 ch. CAN 1 ch. DMAC 8 ch. xternal Bus Interface Addr: 25-bit (Max) R/Wdata : 8-/16-bit (Max) CS: 8 (Max) SRAM, NOR Flash memory, NAND Flash memory Multi-function Serial Interface (UART/CSIO/LIN/I 2 C) 16 ch. (Max) with 16 steps 9-bit FIFO Base Timer (PWC/Reload timer/pwm/ppg) 16 ch. (Max) A/D activation compare 2 ch. capture 4 ch. Free-run timer 3 ch. 1 unit Output compare 6 ch. Waveform generator 3 ch. PPG 3 ch. QPRC 1 ch. (Max) 2 ch. (Max) Dual Timer HDMI-CC/ Remote Control Reception 1 unit 2 ch. (Max) Real-Time Clock 1 unit Watch Counter 1 unit CRC Accelerator Yes Watchdog timer 1 ch. (SW) + 1 ch. (HW) xternal Interrupts 32 pins (Max) + NMI 1 I/O ports 122 pins (Max) 154 pins (Max) 12-bit A/D converter 24 ch. (2 units) 10-bit D/A converter 2 ch. (Max) CSV (Clock Super Visor) Yes LVD (Low-Voltage Detector) 2 ch. Built-in CR High-speed 4 MHz Low-speed 100 khz Debug Function SWJ-DP / TM Unique ID Yes MB9BF528TA MB9BF529TA Note: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use the port relocate function of the I/O port according to your function use. See 12. lectrical Characteristics AC Characteristics Built-in CR Oscillation Characteristics for accuracy of built-in CR. Document Number: Rev. *D Page 7 of 131

9 2. Packages Package Product name MB9BF528SA MB9BF529SA MB9BF528TA MB9BF529TA LQFP: LQS144 (0.5 mm pitch) - LQP: LQP176 (0.5 mm pitch) - BGA: LB192 (0.8 mm pitch) - : Supported Note: See 14. Package Dimensions for detailed information on each package. Document Number: Rev. *D Page 8 of 131

10 VCC P40/SIN10_0/TIOA00_0/INT12_1/MCSX2_0 P41/SOT10_0/TIOA01_0/INT13_1/MCSX3_0 P42/SCK10_0/TIOA02_0/MCLKOUT_0 P43/ADTG_7/SIN11_0/TIOA03_0 P44/SOT11_0/TIOA04_0 P45/SCK11_0/TIOA05_0 C VSS VCC P46/X0A P47/X1A INITX P48/SIN3_2/INT14_1 P49/SOT3_2/AIN0_1/TIOB00_0 P4A/SCK3_2/BIN0_1/TIOB01_0/MADATA00_0 P4B/IGTRG0_0/ZIN0_1/TIOB02_0/MADATA01_0 P4C/SCK7_1/AIN1_2/TIOB03_0/MADATA02_0 P4D/SOT7_1/BIN1_2/TIOB04_0/MADATA03_0 P4/SIN7_1/ZIN1_2/TIOB05_0/INT06_2/MADATA04_0 P70/TX0_0/TIOA04_2/MADATA05_0 P71/RX0_0/TIOB04_2/INT13_2/MADATA06_0 P72/SIN2_0/INT14_2/WKUP2/MADATA07_0 P73/SOT2_0/INT15_2/MADATA08_0 P74/SCK2_0/MADATA09_0 P75/ADTG_8/SIN3_0/INT07_1/MADATA10_0 P76/SOT3_0/TIOA07_2/INT11_2/MADATA11_0 P77/SCK3_0/TIOB07_2/INT12_2/MADATA12_0 P78/AIN1_0/TIOA15_0/MADATA13_0 P79/BIN1_0/TIOB15_0/INT23_1/MADATA14_0 P7A/ZIN1_0/INT24_1/MADATA15_0 P7B/TIOB07_0/INT10_0 P7C/TIOA07_0/INT11_0 P7D/TIOA14_1/INT12_0 P7/TIOB14_1/INT24_0 P7F/TIOA15_1/INT25_0 PF0/SIN1_2/TIOB15_1/INT13_0/CC0_0 PF1/SOT1_2/TIOA08_1/INT14_0 PF2/SCK1_2/TIOB08_1/INT15_0 P0/MD1 MD0 P2/X0 P3/X1 VSS VSS P81/UDP0 P80/UDM0 USBVCC PF5/SCK6_2/IGTRG0_1/INT08_0/WKUP3/CC1_ PF4/SOT6_2/TIOB06_0/INT07_0 PF3/SIN6_2/TIOA06_0/INT06_0 P60/SIN5_0/TIOA02_2/INT15_1/WKUP5/MAD20_ P61/UHCONX/SOT5_0/TIOB02_2/MAD19_0 P62/ADTG_3/SCK5_0/MAD18_0 PD3/TIOB03_2/MAD17_0 PD2/SIN4_0/TIOA03_2/INT00_2/MAD16_0 PD1/SOT4_0/TIOB14_0/INT31_1/MAD15_0 PD0/SCK4_0/TIOB10_2/INT30_1/MAD14_0 PCF/CTS4_0/TIOB08_2/MAD13_0 PC/RTS4_0/TIOB06_1/MAD12_0 PCD/MAD11_0 PCC/MAD10_0 PCB/MAD09_0 VSS VCC PCA/SCK15_0/MAD08_0 PC9/SOT15_0/MAD07_0 PC8/SIN15_0/MAD06_0 PC7/CROUT_1/RTCCO_0/SUBOUT_0/MAD05_0 PC6/SCK14_0/TIOA14_0/MAD04_0 PC5/SOT14_0/TIOA10_2/MAD03_0 PC4/SIN14_0/TIOA08_2/CC0_1/MAD02_0 PC3/TIOA06_1/MAD01_0 PC2/SCK13_0/MAD00_0 PC1/DA1_0/SOT13_0/MCSX4_0 PC0/DA0_0/SIN13_0/MCSX5_0 P95/TIOB13_0/INT27_0 P94/SCK5_1/TIOB12_0/INT26_0 P93/SOT5_1/TIOB11_0 P92/SIN5_1/TIOB10_0 P91/TIOB09_0/INT31_0 P90/TIOB08_0/INT30_0 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX VCC 3. Pin Assignment LQP176 (TOP VIW) VCC VSS PA0/SIN8_0/TIOA08_0/MAD21_ VCC PA1/SOT8_0/TIOA09_0/MAD22_ P83/MCSX6_0 PA2/SCK8_0/TIOA10_0/MAD23_ P82/MCSX7_0 PA3/SIN9_0/TIOA11_0/MAD24_ PF6/NMIX/WKUP0 PA4/RX0_2/SOT9_0/TIOA12_0/INT03_ P20/AIN1_1/INT05_0/CROUT_0 PA5/TX0_2/SCK9_0/TIOA13_0/INT10_ P21/SIN0_0/BIN1_1/INT06_1 P05/TRACD0/SIN4_2/TIOA05_2/INT00_ P22/AN23/SOT0_0/ZIN1_1/TIOB07_1 P06/TRACD1/SOT4_2/TIOB05_2/INT01_ P23/AN22/SCK0_0/RTO00_1/TIOA07_1 P07/TRACD2/ADTG_0/SCK4_ P24/AN21/SIN2_1/RTO01_1/INT01_2 P08/TRACD3/CTS4_2/TIOA00_ P25/AN20/SOT2_1/RTO02_1 P09/TRACCLK/RTS4_2/TIOB00_ P26/AN19/SCK2_1/RTO03_1 P50/SIN3_1/AIN0_2/INT00_0/MOX_ P27/AN18/SCK12_0/RTO04_1/INT02_2 P51/SOT3_1/BIN0_2/INT01_0/MWX_ P28/AN17/ADTG_4/SOT12_0/RTO05_1/INT09_0 P52/SCK3_1/ZIN0_2/INT02_0/MDQM0_ P29/AN16/SIN12_0 P53/SIN6_0/TIOA01_2/INT07_2/MDQM1_ AVRH P54/SOT6_0/TIOB01_2/MAL_ AVRL P55/ADTG_1/SCK6_0/MRDY_ AVSS P56/SIN1_0/TIOA09_2/INT08_2/CC1_1/MNAL_ AVCC P57/SOT1_0/TIOB09_2/INT16_1/MNCL_ PB7/TIOB12_1/INT23_0 P58/SCK1_0/TIOA11_2/INT17_1/MNWX_ PB6/SCK0_2/TIOA12_1/INT22_0 LQFP P59/SIN7_0/TIOB11_2/INT09_2/MNRX_ PB5/SOT0_2/TIOB11_1/INT21_0 P5A/SOT7_0/TIOA13_1/INT18_1/MCSX0_ PB4/SIN0_2/TIOA11_1/INT20_0 P5B/SCK7_0/TIOB13_1/INT19_1/MCSX1_ PB3/TIOB10_1/INT19_0 P5C/TIOA06_2/INT28_ PB2/SCK7_2/TIOA10_1/INT18_0 P5D/TIOB06_2/INT29_ PB1/SOT7_2/TIOB09_1/INT17_0 VSS PB0/SIN7_2/TIOA09_1/INT16_0 P30/AIN0_0/TIOB00_1/INT03_2/WKUP P1F/AN15/ADTG_5/FRCK0_1/TIOB15_2/INT29_1 P31/SCK6_1/BIN0_0/TIOB01_1/INT04_ P1/AN14/RTS4_1/DTTI0X_1/TIOA15_2/INT28_1 P32/SOT6_1/ZIN0_0/TIOB02_1/INT05_ P1D/AN13/CTS4_1/IC03_1/TIOB14_2/INT27_1 P33/ADTG_6/SIN6_1/TIOB03_1/INT04_ P1C/AN12/SCK4_1/IC02_1/TIOA14_2/INT26_1 P34/TX0_1/FRCK0_0/TIOB04_ P1B/AN11/SOT4_1/IC01_1/TIOB13_2/INT25_1 P35/RX0_1/IC03_0/TIOB05_1/INT08_ P1A/AN10/SIN4_1/IC00_1/TIOA13_2/INT05_1 P36/SIN5_2/IC02_0/TIOA12_2/INT09_ P19/AN09/SCK2_2/INT22_1 P37/SOT5_2/IC01_0/TIOB12_2/INT10_ P18/AN08/SOT2_2/INT21_1 P38/SCK5_2/IC00_0/INT11_ P17/AN07/SIN2_2/INT04_1 P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_ P16/AN06/SCK0_1/INT20_1 P3A/RTO00_0/TIOA00_ P15/AN05/SOT0_1/IC03_2 P3B/RTO01_0/TIOA01_ P14/AN04/SIN0_1/IC02_2/INT03_1 P3C/RTO02_0/TIOA02_ P13/AN03/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1 P3D/RTO03_0/TIOA03_ P12/AN02/SOT1_1/IC00_2 P3/RTO04_0/TIOA04_ P11/AN01/SIN1_1/FRCK0_2/INT02_1/WKUP1 P3F/RTO05_0/TIOA05_ P10/AN00 VSS VCC Note: The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (PFR) to select the pin. Document Number: Rev. *D Page 9 of 131

11 VCC P40/SIN10_0/TIOA00_0/INT12_1/MCSX2_0 P41/SOT10_0/TIOA01_0/INT13_1/MCSX3_0 P42/SCK10_0/TIOA02_0/MCLKOUT_0 P43/ADTG_7/SIN11_0/TIOA03_0 P44/SOT11_0/TIOA04_0 P45/SCK11_0/TIOA05_0 C VSS VCC P46/X0A P47/X1A INITX P48/SIN3_2/INT14_1 P49/SOT3_2/AIN0_1/TIOB00_0 P4A/SCK3_2/BIN0_1/TIOB01_0/MADATA00_0 P4B/IGTRG0_0/ZIN0_1/TIOB02_0/MADATA01_0 P4C/SCK7_1/AIN1_2/TIOB03_0/MADATA02_0 P4D/SOT7_1/BIN1_2/TIOB04_0/MADATA03_0 P4/SIN7_1/ZIN1_2/TIOB05_0/INT06_2/MADATA04_0 P70/TX0_0/TIOA04_2/MADATA05_0 P71/RX0_0/TIOB04_2/INT13_2/MADATA06_0 P72/SIN2_0/INT14_2/WKUP2/MADATA07_0 P73/SOT2_0/INT15_2/MADATA08_0 P74/SCK2_0/MADATA09_0 P75/ADTG_8/SIN3_0/INT07_1/MADATA10_0 P76/SOT3_0/TIOA07_2/INT11_2/MADATA11_0 P77/SCK3_0/TIOB07_2/INT12_2/MADATA12_0 P78/AIN1_0/TIOA15_0/MADATA13_0 P79/BIN1_0/TIOB15_0/INT23_1/MADATA14_0 P7A/ZIN1_0/INT24_1/MADATA15_0 P0/MD1 MD0 P2/X0 P3/X1 VSS VSS P81/UDP0 P80/UDM0 USBVCC PF5/IGTRG0_1/INT08_0/WKUP3/CC1_0 P60/SIN5_0/TIOA02_2/INT15_1/WKUP5/MAD20_0 P61/UHCONX/SOT5_0/TIOB02_2/MAD19_0 P62/ADTG_3/SCK5_0/MAD18_0 PD3/TIOB03_2/MAD17_0 PD2/SIN4_0/TIOA03_2/INT00_2/MAD16_0 PD1/SOT4_0/TIOB14_0/INT31_1/MAD15_0 PD0/SCK4_0/TIOB10_2/INT30_1/MAD14_0 PCF/CTS4_0/TIOB08_2/MAD13_0 PC/RTS4_0/TIOB06_1/MAD12_0 PCD/MAD11_0 PCC/MAD10_0 PCB/MAD09_0 VSS VCC PCA/SCK15_0/MAD08_0 PC9/SOT15_0/MAD07_0 PC8/SIN15_0/MAD06_0 PC7/CROUT_1/RTCCO_0/SUBOUT_0/MAD05_0 PC6/SCK14_0/TIOA14_0/MAD04_0 PC5/SOT14_0/TIOA10_2/MAD03_0 PC4/SIN14_0/TIOA08_2/CC0_1/MAD02_0 PC3/TIOA06_1/MAD01_0 PC2/SCK13_0/MAD00_0 PC1/DA1_0/SOT13_0/MCSX4_0 PC0/DA0_0/SIN13_0/MCSX5_0 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX VCC LQS144 (TOP VIW) VCC VSS PA0/SIN8_0/TIOA08_0/MAD21_ VCC PA1/SOT8_0/TIOA09_0/MAD22_ P83/MCSX6_0 PA2/SCK8_0/TIOA10_0/MAD23_ P82/MCSX7_0 PA3/SIN9_0/TIOA11_0/MAD24_ PF6/NMIX/WKUP0 PA4/RX0_2/SOT9_0/TIOA12_0/INT03_ P20/AIN1_1/INT05_0/CROUT_0 PA5/TX0_2/SCK9_0/TIOA13_0/INT10_ P21/SIN0_0/BIN1_1/INT06_1 P05/TRACD0/SIN4_2/TIOA05_2/INT00_ P22/AN23/SOT0_0/ZIN1_1/TIOB07_1 P06/TRACD1/SOT4_2/TIOB05_2/INT01_ P23/AN22/SCK0_0/RTO00_1/TIOA07_1 P07/TRACD2/ADTG_0/SCK4_ P24/AN21/SIN2_1/RTO01_1/INT01_2 P08/TRACD3/CTS4_2/TIOA00_ P25/AN20/SOT2_1/RTO02_1 P09/TRACCLK/RTS4_2/TIOB00_ P26/AN19/SCK2_1/RTO03_1 P50/SIN3_1/AIN0_2/INT00_0/MOX_ P27/AN18/SCK12_0/RTO04_1/INT02_2 P51/SOT3_1/BIN0_2/INT01_0/MWX_ P28/AN17/ADTG_4/SOT12_0/RTO05_1/INT09_0 P52/SCK3_1/ZIN0_2/INT02_0/MDQM0_ P29/AN16/SIN12_0 P53/SIN6_0/TIOA01_2/INT07_2/MDQM1_ AVRH P54/SOT6_0/TIOB01_2/MAL_ AVRL LQFP P55/ADTG_1/SCK6_0/MRDY_ AVSS P56/SIN1_0/TIOA09_2/INT08_2/CC1_1/MNAL_ AVCC P57/SOT1_0/TIOB09_2/INT16_1/MNCL_ P1F/AN15/ADTG_5/FRCK0_1/TIOB15_2/INT29_1 P58/SCK1_0/TIOA11_2/INT17_1/MNWX_ P1/AN14/RTS4_1/DTTI0X_1/TIOA15_2/INT28_1 P59/SIN7_0/TIOB11_2/INT09_2/MNRX_ P1D/AN13/CTS4_1/IC03_1/TIOB14_2/INT27_1 P5A/SOT7_0/TIOA13_1/INT18_1/MCSX0_ P1C/AN12/SCK4_1/IC02_1/TIOA14_2/INT26_1 P5B/SCK7_0/TIOB13_1/INT19_1/MCSX1_ P1B/AN11/SOT4_1/IC01_1/TIOB13_2/INT25_1 VSS P1A/AN10/SIN4_1/IC00_1/TIOA13_2/INT05_1 P36/SIN5_2/IC02_0/TIOA12_2/INT09_ P19/AN09/SCK2_2/INT22_1 P37/SOT5_2/IC01_0/TIOB12_2/INT10_ P18/AN08/SOT2_2/INT21_1 P38/SCK5_2/IC00_0/INT11_ P17/AN07/SIN2_2/INT04_1 P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_ P16/AN06/SCK0_1/INT20_1 P3A/RTO00_0/TIOA00_ P15/AN05/SOT0_1/IC03_2 P3B/RTO01_0/TIOA01_ P14/AN04/SIN0_1/IC02_2/INT03_1 P3C/RTO02_0/TIOA02_ P13/AN03/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1 P3D/RTO03_0/TIOA03_ P12/AN02/SOT1_1/IC00_2 P3/RTO04_0/TIOA04_ P11/AN01/SIN1_1/FRCK0_2/INT02_1/WKUP1 P3F/RTO05_0/TIOA05_ P10/AN00 VSS VCC Note: The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (PFR) to select the pin. Document Number: Rev. *D Page 10 of 131

12 LB192 (TOP VIW) A UDP0 UDM0 USB VCC VSS PCD PCB VSS VCC PC8 VSS TCK VCC B VSS PA0 PF5 PF3 P61 PD1 PCA PC1 P95 P92 TDO TMS TRSTX VSS C VCC PA1 PA2 PF4 P60 PD2 PCC PC5 PC0 P93 P90 TDI PF6 VCC D PA5 PA4 P05 P06 PA3 PD3 PC PC6 PC2 P94 P91 P21 P20 P83 VSS P07 P08 P09 P50 P62 PCF PC7 PC3 P25 P24 P23 P22 P82 F P51 P52 P53 P54 P55 P56 PD0 PC9 PC4 P29 P28 P27 P26 AVRH G VSS P57 P58 P59 P5A P5B VSS VSS PB7 PB6 PB5 PB4 PB3 AVRL H P5C P5D P30 P31 P32 P33 VSS VSS P1F P1 PB2 PB1 PB0 AVSS J VSS P37 P36 P35 P34 P70 VSS P76 P1D P1C P1B P1A P19 AVCC K P38 P39 P3A P3B P4A P4 VSS P74 P7B P7F P18 P16 P15 P17 L P3C P3D P3 P43 P49 P4D VSS P73 P7A P7 P14 P13 P12 VSS M VSS P3F P42 P44 P48 P4C VSS P72 P79 PF0 PF2 P11 P10 VCC N VCC P40 P41 P45 INITX P4B VSS P71 P78 P7D PF1 MD0 MD1 VSS P C VSS VCC X0A X1A VSS P75 P77 P7C VSS X0 X1 Note: The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (PFR) to select the pin. Document Number: Rev. *D Page 11 of 131

13 4. List of Pin Functions List of pin numbers The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (PFR) to select the pin. Pin No I/O circuit Pin Name LQFP-176 LQFP-144 BGA-192 type 1 1 C1 VCC - PA0 2 2 B2 SIN8_0 TIOA08_0 I* J MAD21_0 PA1 3 3 C2 SOT8_0 TIOA09_0 I* J MAD22_0 PA2 4 4 C3 SCK8_0 TIOA10_0 I* J MAD23_0 PA3 5 5 D5 SIN9_0 TIOA11_0 I* J MAD24_0 PA4 RX0_2 6 6 D2 SOT9_0 I* K TIOA12_0 INT03_0 PA5 TX0_2 7 7 D1 SCK9_0 I* K TIOA13_0 INT10_2 P05 TRACD0 8 8 D3 SIN4_2 Q TIOA05_2 9 9 D INT00_1 P06 TRACD1 SOT4_2 TIOB05_2 INT01_1 P07 TRACD2 ADTG_0 SCK4_2 Q P Pin type Document Number: Rev. *D Page 12 of 131

14 Pin No LQFP-176 LQFP-144 BGA-192 Pin Name I/O circuit type Pin type P TRACD3 CTS4_2 P TIOA00_2 P TRACCLK RTS4_2 P TIOB00_2 P50 SIN3_ AIN0_2 K INT00_0 MOX_0 P51 SOT3_ F1 BIN0_2 K INT01_0 MWX_0 P52 SCK3_ F2 ZIN0_2 K INT02_0 MDQM0_0 P53 SIN6_ F3 TIOA01_2 K INT07_2 MDQM1_0 P F4 SOT6_0 TIOB01_2 J MAL_0 P F5 ADTG_1 SCK6_0 J MRDY_0 P56 SIN1_ F6 TIOA09_2 INT08_2 I* S CC1_1 MNAL_0 Document Number: Rev. *D Page 13 of 131

15 Pin No LQFP-176 LQFP-144 BGA G G G G G H H2 P57 SOT1_0 TIOB09_2 INT16_1 MNCL_0 P58 SCK1_0 TIOA11_2 INT17_1 MNWX_0 P59 SIN7_0 TIOB11_2 INT09_2 MNRX_0 P5A SOT7_0 TIOA13_1 INT18_1 MCSX0_0 P5B SCK7_0 TIOB13_1 INT19_1 MCSX1_0 P5C TIOA06_2 INT28_0 P5D TIOB06_2 INT29_0 Pin Name A5 VSS H H4 P30 AIN0_0 TIOB00_1 INT03_2 WKUP4 P31 SCK6_1 BIN0_0 TIOB01_1 INT04_2 I/O circuit type I* K I* K K K K K K U K Pin type Document Number: Rev. *D Page 14 of 131

16 Pin No LQFP-176 LQFP-144 BGA-192 Pin Name I/O circuit type Pin type P32 SOT6_ H5 ZIN0_0 K TIOB02_1 INT05_2 P33 ADTG_ H6 SIN6_1 K TIOB03_1 INT04_0 P J5 TX0_1 FRCK0_0 J TIOB04_1 P35 RX0_ J4 IC03_0 K TIOB05_1 INT08_1 P36 SIN5_ J3 IC02_0 K TIOA12_2 INT09_1 P37 SOT5_ J2 IC01_0 K TIOB12_2 INT10_1 P K1 SCK5_2 IC00_0 K INT11_1 P39 ADTG_ K2 DTTI0X_0 J RTCCO_2 SUBOUT_2 P3A K3 RTO00_0 F J TIOA00_1 P3B K4 RTO01_0 F J TIOA01_1 Document Number: Rev. *D Page 15 of 131

17 Pin No LQFP-176 LQFP-144 BGA L1 P3C RTO02_0 Pin Name F I/O circuit type TIOA02_1 P3D L2 RTO03_0 TIOA03_1 F J P L3 RTO04_0 TIOA04_1 F J P3F M2 RTO05_0 TIOA05_1 F J A8 VSS N1 VCC - P N2 SIN10_0 TIOA00_0 INT12_1 MCSX2_0 K P N3 SOT10_0 TIOA01_0 INT13_1 MCSX3_0 K P M3 SCK10_0 TIOA02_0 MCLKOUT_0 J P L4 ADTG_7 SIN11_0 TIOA03_0 I* J P M4 SOT11_0 TIOA04_0 I* J P N4 SCK11_0 TIOA05_0 I* J P2 C A11 VSS P4 VCC P5 P46 X0A D F P6 P47 X1A D G N5 INITX B C P M5 SIN3_2 K INT14_1 J Pin type Document Number: Rev. *D Page 16 of 131

18 Pin No LQFP-176 LQFP-144 BGA L K N M L K J N M L8 P49 SOT3_2 AIN0_1 TIOB00_0 P4A SCK3_2 BIN0_1 TIOB01_0 MADATA00_0 P4B IGTRG0_0 ZIN0_1 TIOB02_0 MADATA01_0 P4C SCK7_1 AIN1_2 TIOB03_0 MADATA02_0 P4D SOT7_1 BIN1_2 TIOB04_0 MADATA03_0 P4 SIN7_1 ZIN1_2 TIOB05_0 INT06_2 MADATA04_0 P70 TX0_0 TIOA04_2 MADATA05_0 P71 RX0_0 TIOB04_2 INT13_2 MADATA06_0 P72 SIN2_0 INT14_2 WKUP2 MADATA07_0 P73 SOT2_0 INT15_2 MADATA08_0 Pin name I/O circuit type J J J J J K J K U K Pin type Document Number: Rev. *D Page 17 of 131

19 Pin No LQFP-176 LQFP-144 BGA K8 P74 SCK2_0 MADATA09_0 Pin name P75 ADTG_ P8 SIN3_0 INT07_1 MADATA10_0 P76 SOT3_ J8 TIOA07_2 INT11_2 MADATA11_0 P77 SCK3_ P9 TIOB07_2 INT12_2 MADATA12_0 P N9 AIN1_0 TIOA15_0 MADATA13_0 P79 BIN1_ M9 TIOB15_0 INT23_1 MADATA14_0 - - M1 VSS P3 VSS - P7A L9 ZIN1_0 INT24_1 MADATA15_0 P7B 76 - K9 TIOB07_0 INT10_0 P7C 77 - P10 TIOA07_0 INT11_0 P7D 78 - N10 TIOA14_1 INT12_0 P L10 TIOB14_1 INT24_0 P7F 80 - K10 TIOA15_1 INT25_0 I/O circuit type J K K K J K K K K K K K Pin type Document Number: Rev. *D Page 18 of 131

20 Pin No LQFP-176 LQFP-144 BGA-192 Pin name I/O circuit type PF M10 SIN1_2 TIOB15_1 INT13_0 CC0_0 I* S PF N11 SOT1_2 TIOA08_1 INT14_0 I* K PF M11 SCK1_2 TIOB08_1 INT15_0 I* K N13 P0 MD1 C N12 MD0 J D P12 P2 X0 A A P13 P3 X1 A B VSS M14 VCC P7 VSS N7 VSS M13 P10 AN00 G L P M12 AN01 SIN1_1 FRCK0_2 INT02_1 WKUP1 G N P L13 AN02 SOT1_1 IC00_2 G L P L12 AN03 SCK1_1 IC01_2 RTCCO_1 SUBOUT_1 G L P L11 AN04 SIN0_1 IC02_2 INT03_1 G M P K13 AN05 SOT0_1 G L IC03_2 Pin type Document Number: Rev. *D Page 19 of 131

21 Pin No LQFP-176 LQFP-144 BGA-192 Pin name P K12 AN06 SCK0_1 G INT20_1 P K14 AN07 SIN2_2 G INT04_1 - - M7 VSS L7 VSS K7 VSS - P K11 AN08 SOT2_2 G INT21_1 P J13 AN09 SCK2_2 G INT22_1 P1A AN J12 SIN4_1 IC00_1 G TIOA13_2 INT05_1 P1B AN J11 SOT4_1 IC01_1 G TIOB13_2 INT25_1 P1C AN J10 SCK4_1 IC02_1 G TIOA14_2 INT26_1 P1D AN J9 CTS4_1 IC03_1 G TIOB14_2 INT27_ H10 P1 AN14 RTS4_1 DTTI0X_1 TIOA15_2 INT28_1 G I/O circuit type M M M M M M M M M Pin type Document Number: Rev. *D Page 20 of 131

22 Pin No I/O circuit Pin name LQFP-176 LQFP-144 BGA-192 type P1F AN H9 ADTG_5 FRCK0_1 G TIOB15_2 INT29_1 PB H13 SIN7_2 TIOA09_1 INT16_0 PB H12 SOT7_2 TIOB09_1 INT17_0 PB H11 SCK7_2 TIOA10_1 INT18_0 PB G13 TIOB10_1 INT19_0 PB G12 SIN0_2 TIOA11_1 INT20_0 PB G11 SOT0_2 TIOB11_1 INT21_0 PB G10 SCK0_2 TIOA12_1 INT22_0 PB G9 TIOB12_1 INT23_ J14 AVCC H14 AVSS J7 VSS P11 VSS G14 AVRL F14 AVRH - P F10 AN16 G SIN12_0 P28 AN F11 ADTG_4 SOT12_0 G RTO05_1 INT09_0 M K K K K K K K K L M Pin type Document Number: Rev. *D Page 21 of 131

23 Pin No I/O circuit Pin name LQFP-176 LQFP-144 BGA-192 type P27 AN F12 SCK12_0 G M RTO04_1 INT02_2 P F13 AN19 SCK2_1 G L RTO03_1 P AN20 SOT2_1 G L RTO02_1 P24 AN SIN2_1 G M RTO01_1 INT01_2 P23 AN SCK0_0 G L RTO00_1 TIOA07_1 P22 AN SOT0_0 G L ZIN1_1 TIOB07_1 P D12 SIN0_0 BIN1_1 K INT06_1 P D13 AIN1_1 INT05_0 K CROUT_0 PF C13 NMIX I* H WKUP P82 MCSX7_0 J D14 P83 MCSX6_0 J C14 VCC G7 VSS A13 VCC B13 P00 TRSTX I P A12 TCK I SWCLK Pin type Document Number: Rev. *D Page 22 of 131

24 Pin No LQFP-176 LQFP-144 BGA-192 Pin name C12 P02 TDI P B12 TMS SWDIO P B11 TDO SWO P C11 TIOB08_0 INT30_0 - - N14 VSS - P D11 TIOB09_0 INT31_0 P B10 SIN5_1 TIOB10_0 P C10 SOT5_1 TIOB11_0 P D10 SCK5_1 TIOB12_0 INT26_0 I/O circuit type P B9 TIOB13_0 INT27_0 K PC C9 DA0_0 SIN13_0 MCSX5_0 H O PC B8 DA1_0 SOT13_0 MCSX4_0 H O PC D9 SCK13_0 MAD00_0 J PC TIOA06_1 MAD01_0 J PC F9 SIN14_0 TIOA08_2 CC0_1 MAD02_0 I* R PC C8 SOT14_0 TIOA10_2 MAD03_0 I* J - - L14 VSS - I I I K K J J K Pin type Document Number: Rev. *D Page 23 of 131

25 Pin No LQFP-176 LQFP-144 BGA-192 Pin name I/O circuit type PC D8 SCK14_0 TIOA14_0 MAD04_0 I* J PC CROUT_1 RTCCO_0 SUBOUT_0 MAD05_0 J PC A10 SIN15_0 MAD06_0 J PC F8 SOT15_0 MAD07_0 J PCA B7 SCK15_0 MAD08_0 J A9 VCC G8 VSS A7 PCB MAD09_0 J C7 PCC MAD10_0 J A6 PCD MAD11_0 J PC D7 RTS4_0 TIOB06_1 MAD12_0 J PCF CTS4_0 TIOB08_2 MAD13_0 J PD F7 SCK4_0 TIOB10_2 INT30_1 MAD14_0 K PD B6 SOT4_0 TIOB14_0 INT31_1 MAD15_0 K - - B14 VSS H7 VSS B1 VSS G1 VSS - Pin type Document Number: Rev. *D Page 24 of 131

26 Pin No LQFP-176 LQFP-144 BGA-192 Pin name I/O circuit type PD C6 SIN4_0 TIOA03_2 INT00_2 MAD16_0 K PD D6 TIOB03_2 MAD17_0 J P ADTG_3 SCK5_0 MAD18_0 J P B5 UHCONX SOT5_0 TIOB02_2 MAD19_0 J P C5 SIN5_0 TIOA02_2 INT15_1 WKUP5 MAD20_0 U PF B4 SIN6_2 TIOA06_0 INT06_0 I* K PF C4 SOT6_2 TIOB06_0 INT07_0 I* K PF5 IGTRG0_ INT08_0 B3 WKUP3 CC1_0 I* T - SCK6_ A4 USBVCC A3 P80 UDM0 K V A2 P81 UDP0 K V H8 VSS J1 VSS - *: 5V tolerant I/O Pin type Document Number: Rev. *D Page 25 of 131

27 List of pin functions The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (PFR) to select the pin. ADC Pin function Base Timer 0 Base Timer 1 Base Timer 2 Pin name Function description Pin No LQFP-176 LQFP-144 BGA-192 ADTG_ ADTG_ F5 ADTG_ K2 ADTG_ ADTG_4 A/D converter external trigger input pin F11 ADTG_ H9 ADTG_ H6 ADTG_ L4 ADTG_ P8 AN M13 AN M12 AN L13 AN L12 AN L11 AN K13 AN K12 AN K14 AN K11 AN J13 AN J12 AN11 A/D converter analog input pin J11 AN12 ANxx describes ADC ch.xx J10 AN J9 AN H10 AN H9 AN F10 AN F11 AN F12 AN F13 AN AN AN AN TIOA00_ N2 TIOA00_1 Base timer ch.0 TIOA pin K3 TIOA00_ TIOB00_ L5 TIOB00_1 Base timer ch.0 TIOB pin 28 - H3 TIOB00_ TIOA01_ N3 TIOA01_1 Base timer ch.1 TIOA pin K4 TIOA01_ F3 TIOB01_ K5 TIOB01_1 Base timer ch.1 TIOB pin 29 - H4 TIOB01_ F4 TIOA02_ M3 TIOA02_1 Base timer ch.2 TIOA pin L1 TIOA02_ C5 TIOB02_ N6 TIOB02_1 Base timer ch.2 TIOB pin 30 - H5 TIOB02_ B5 Document Number: Rev. *D Page 26 of 131

28 Pin function Base Timer 3 Base Timer 4 Base Timer 5 Base Timer 6 Base Timer 7 Base Timer 8 Base Timer 9 Base Timer 10 Base Timer 11 Pin name Function description Pin No LQFP-176 LQFP-144 BGA-192 TIOA03_ L4 TIOA03_1 Base timer ch.3 TIOA pin L2 TIOA03_ C6 TIOB03_ M6 TIOB03_1 Base timer ch.3 TIOB pin 31 - H6 TIOB03_ D6 TIOA04_ M4 TIOA04_1 Base timer ch.4 TIOA pin L3 TIOA04_ J6 TIOB04_ L6 TIOB04_1 Base timer ch.4 TIOB pin 32 - J5 TIOB04_ N8 TIOA05_ N4 TIOA05_1 Base timer ch.5 TIOA pin M2 TIOA05_2 8 8 D3 TIOB05_ K6 TIOB05_1 Base timer ch.5 TIOB pin 33 - J4 TIOB05_2 9 9 D4 TIOA06_ B4 TIOA06_1 Base timer ch.6 TIOA pin TIOA06_ H1 TIOB06_ C4 TIOB06_1 Base timer ch.6 TIOB pin D7 TIOB06_ H2 TIOA07_ P10 TIOA07_1 Base timer ch.7 TIOA pin TIOA07_ J8 TIOB07_ K9 TIOB07_1 Base timer ch.7 TIOB pin TIOB07_ P9 TIOA08_0 2 2 B2 TIOA08_1 Base timer ch.8 TIOA pin 82 - N11 TIOA08_ F9 TIOB08_ C11 TIOB08_1 Base timer ch.8 TIOB pin 83 - M11 TIOB08_ TIOA09_0 3 3 C2 TIOA09_1 Base timer ch.9 TIOA pin H13 TIOA09_ F6 TIOB09_ D11 TIOB09_1 Base timer ch.9 TIOB pin H12 TIOB09_ G2 TIOA10_0 4 4 C3 TIOA10_1 Base timer ch.10 TIOA pin H11 TIOA10_ C8 TIOB10_ B10 TIOB10_1 Base timer ch.10 TIOB pin G13 TIOB10_ F7 TIOA11_0 5 5 D5 TIOA11_1 Base timer ch.11 TIOA pin G12 TIOA11_ G3 TIOB11_ C10 TIOB11_1 Base timer ch.11 TIOB pin G11 TIOB11_ G4 Document Number: Rev. *D Page 27 of 131

29 Pin function Base Timer 12 Base Timer 13 Base Timer 14 Base Timer 15 Pin name Function description Pin No LQFP-176 LQFP-144 BGA-192 TIOA12_0 6 6 D2 TIOA12_1 Base timer ch.12 TIOA pin G10 TIOA12_ J3 TIOB12_ D10 TIOB12_1 Base timer ch.12 TIOB pin G9 TIOB12_ J2 TIOA13_0 7 7 D1 TIOA13_1 Base timer ch.13 TIOA pin G5 TIOA13_ J12 TIOB13_ B9 TIOB13_1 Base timer ch.13 TIOB pin G6 TIOB13_ J11 TIOA14_ D8 TIOA14_1 Base timer ch.14 TIOA pin 78 - N10 TIOA14_ J10 TIOB14_ B6 TIOB14_1 Base timer ch.14 TIOB pin 79 - L10 TIOB14_ J9 TIOA15_ N9 TIOA15_1 Base timer ch.15 TIOA pin 80 - K10 TIOA15_ H10 TIOB15_ M9 TIOB15_1 Base timer ch.15 TIOB pin 81 - M10 TIOB15_ H9 Debugger SWCLK Serial wire debug interface clock input A12 SWDIO Serial wire debug interface data input / output B12 SWO Serial wire viewer output B11 TCK JTAG test clock input A12 TDI JTAG test data input C12 TDO JTAG debug data output B11 TMS JTAG test mode input/output B12 TRACCLK Trace CLK output of TM TRACD0 8 8 D3 TRACD1 9 9 D4 Trace data output of TM TRACD TRACD TRSTX JTAG test reset B13 Document Number: Rev. *D Page 28 of 131

30 Pin function xternal Bus Pin name Function description Pin No LQFP-176 LQFP-144 BGA-192 MAD00_ D9 MAD01_ MAD02_ F9 MAD03_ C8 MAD04_ D8 MAD05_ MAD06_ A10 MAD07_ F8 MAD08_ B7 MAD09_ A7 MAD10_ C7 MAD11_ A6 MAD12_0 xternal bus interface address bus D7 MAD13_ MAD14_ F7 MAD15_ B6 MAD16_ C6 MAD17_ D6 MAD18_ MAD19_ B5 MAD20_ C5 MAD21_0 2 2 B2 MAD22_0 3 3 C2 MAD23_0 4 4 C3 MAD24_0 5 5 D5 MCSX0_ G5 MCSX1_ G6 MCSX2_ N2 MCSX3_ N3 xternal bus interface chip select output pin MCSX4_ B8 MCSX5_ C9 MCSX6_ D14 MCSX7_ MDQM0_ F2 xternal bus interface byte mask signal output MDQM1_ F3 MOX_0 xternal bus interface read enable signal for SRAM MWX_0 xternal bus interface write enable signal for SRAM F1 Document Number: Rev. *D Page 29 of 131

31 Pin function xternal Bus MNAL_0 MNCL_0 MNRX_0 MNWX_0 Pin name MADATA00_0 Function description xternal bus interface AL signal to control NAND Flash output pin xternal bus interface CL signal to control NAND Flash output pin xternal bus interface read enable signal to control NAND Flash xternal bus interface write enable signal to control NAND Flash Pin No LQFP-176 LQFP-144 BGA F G G G K5 MADATA01_ N6 MADATA02_ M6 MADATA03_ L6 MADATA04_ K6 MADATA05_ J6 MADATA06_ N8 MADATA07_0 MADATA08_0 xternal bus interface data bus (Address / data multiplex bus) M8 L8 MADATA09_ K8 MADATA10_ P8 MADATA11_ J8 MADATA12_ P9 MADATA13_ N9 MADATA14_ M9 MADATA15_ L9 MAL_0 xternal bus interface Address Latch enable output signal for multiplex F4 MRDY_0 xternal bus interface external RDY input signal F5 MCLKOUT_0 xternal bus interface external clock output M3 Document Number: Rev. *D Page 30 of 131

32 Pin function xternal Interrupt Pin name Function description Pin No LQFP-176 LQFP-144 BGA-192 INT00_ INT00_1 xternal interrupt request 00 input pin 8 8 D3 INT00_ C6 INT01_ F1 INT01_1 xternal interrupt request 01 input pin 9 9 D4 INT01_ INT02_ F2 INT02_1 xternal interrupt request 02 input pin M12 INT02_ F12 INT03_0 6 6 D2 INT03_1 xternal interrupt request 03 input pin L11 INT03_ H3 INT04_ H6 INT04_1 xternal interrupt request 04 input pin K14 INT04_ H4 INT05_ D13 INT05_1 xternal interrupt request 05 input pin J12 INT05_ H5 INT06_ B4 INT06_1 xternal interrupt request 06 input pin D12 INT06_ K6 INT07_ C4 INT07_1 xternal interrupt request 07 input pin P8 INT07_ F3 INT08_ B3 INT08_1 xternal interrupt request 08 input pin 33 - J4 INT08_ F6 INT09_ F11 INT09_1 xternal interrupt request 09 input pin J3 INT09_ G4 INT10_ K9 INT10_1 xternal interrupt request 10 input pin J2 INT10_2 7 7 D1 INT11_ P10 INT11_1 xternal interrupt request 11 input pin K1 INT11_ J8 INT12_ N10 INT12_1 xternal interrupt request 12 input pin N2 INT12_ P9 INT13_ M10 INT13_1 xternal interrupt request 13 input pin N3 INT13_ N8 INT14_ N11 INT14_1 xternal interrupt request 14 input pin M5 INT14_ M8 Document Number: Rev. *D Page 31 of 131

33 Pin function xternal Interrupt Pin No Pin name Function description LQFP-176 LQFP-144 BGA-192 INT15_ M11 INT15_1 xternal interrupt request 15 input pin C5 INT15_ L8 INT16_ H13 xternal interrupt request 16 input pin INT16_ G2 INT17_ H12 xternal interrupt request 17 input pin INT17_ G3 INT18_ H11 xternal interrupt request 18 input pin INT18_ G5 INT19_ G13 xternal interrupt request 19 input pin INT19_ G6 INT20_ G12 xternal interrupt request 20 input pin INT20_ K12 INT21_ G11 xternal interrupt request 21 input pin INT21_ K11 INT22_ G10 xternal interrupt request 22 input pin INT22_ J13 INT23_ G9 xternal interrupt request 23 input pin INT23_ M9 INT24_ L10 xternal interrupt request 24 input pin INT24_ L9 INT25_ K10 xternal interrupt request 25 input pin INT25_ J11 INT26_ D10 xternal interrupt request 26 input pin INT26_ J10 INT27_ B9 xternal interrupt request 27 input pin INT27_ J9 INT28_ H1 xternal interrupt request 28 input pin INT28_ H10 INT29_ H2 xternal interrupt request 29 input pin INT29_ H9 INT30_ C11 xternal interrupt request 30 input pin INT30_ F7 INT31_ D11 xternal interrupt request 31 input pin INT31_ B6 NMIX Non-Maskable Interrupt input C13 Document Number: Rev. *D Page 32 of 131

34 Pin function GPIO Pin name Function description Pin No LQFP-176 LQFP-144 BGA-192 P B13 P A12 P C12 P B12 P B11 General-purpose I/O port 0 P D3 P D4 P P P P M13 P M12 P L13 P L12 P L11 P K13 P K12 P K14 General-purpose I/O port 1 P K11 P J13 P1A J12 P1B J11 P1C J10 P1D J9 P H10 P1F H9 P D13 P D12 P P P General-purpose I/O port 2 P P F13 P F12 P F11 P F10 Document Number: Rev. *D Page 33 of 131

35 Pin function GPIO Pin name Function description Pin No LQFP-176 LQFP-144 BGA-192 P H3 P H4 P H5 P H6 P J5 P J4 P J3 P J2 General-purpose I/O port 3 P K1 P K2 P3A K3 P3B K4 P3C L1 P3D L2 P L3 P3F M2 P N2 P N3 P M3 P L4 P M4 P N4 P P5 P47 General-purpose I/O port P6 P M5 P L5 P4A K5 P4B N6 P4C M6 P4D L6 P K6 P P F1 P F2 P F3 P F4 P F5 P F6 General-purpose I/O port 5 P G2 P G3 P G4 P5A G5 P5B G6 P5C 25 - H1 P5D 26 - H2 Document Number: Rev. *D Page 34 of 131

36 Pin function GPIO Pin name Function description Pin No LQFP-176 LQFP-144 BGA-192 P C5 P61 General-purpose I/O port B5 P P J6 P N8 P M8 P L8 P K8 P P8 P J8 P P9 General-purpose I/O port 7 P N9 P M9 P7A L9 P7B 76 - K9 P7C 77 - P10 P7D 78 - N10 P L10 P7F 80 - K10 P A3 P A2 General-purpose I/O port 8 P P D14 P C11 P D11 P B10 General-purpose I/O port 9 P C10 P D10 P B9 PA0 2 2 B2 PA1 3 3 C2 PA2 4 4 C3 General-purpose I/O port A PA3 5 5 D5 PA4 6 6 D2 PA5 7 7 D1 PB H13 PB H12 PB H11 PB G13 General-purpose I/O port B PB G12 PB G11 PB G10 PB G9 Document Number: Rev. *D Page 35 of 131

37 Pin function GPIO Multi Function Serial 0 Pin name Function description Pin No LQFP-176 LQFP-144 BGA-192 PC C9 PC B8 PC D9 PC PC F9 PC C8 PC D8 PC General-purpose I/O port C PC A10 PC F8 PCA B7 PCB A7 PCC C7 PCD A6 PC D7 PCF PD F7 PD B6 General-purpose I/O port D PD C6 PD D6 P N13 P2 General-purpose I/O port P12 P P13 PF M10 PF N11 PF M11 PF3 General-purpose I/O port F* B4 PF C4 PF B3 PF C13 SIN0_ D12 SIN0_1 Multifunction serial interface ch.0 input pin L11 SIN0_ G12 SOT0_0 (SDA0_0) SOT0_1 (SDA0_1) SOT0_2 (SDA0_2) SCK0_0 (SCL0_0) SCK0_1 (SCL0_1) SCK0_2 (SCL0_2) Multifunction serial interface ch.0 output pin. This pin operates as SOT0 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA0 when it is used in an I 2 C (operation mode 4). Multifunction serial interface ch.0 clock I/O pin. This pin operates as SCK0 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL0 when it is used in an I 2 C (operation mode 4) K G K G10 Document Number: Rev. *D Page 36 of 131

38 Pin function Multi Function Serial 1 Multi Function Serial 2 Multi Function Serial 3 Pin name Function description Pin No. LQFP-176 LQFP-144 BGA-192 SIN1_ F6 SIN1_1 Multifunction serial interface ch.1 input pin M12 SIN1_ M10 SOT1_0 (SDA1_0) SOT1_1 (SDA1_1) SOT1_2 (SDA1_2) SCK1_0 (SCL1_0) SCK1_1 (SCL1_1) SCK1_2 (SCL1_2) Multifunction serial interface ch.1 output pin. This pin operates as SOT1 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA1 when it is used in an I 2 C (operation mode 4). Multifunction serial interface ch.1 clock I/O pin. This pin operates as SCK1 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL1 when it is used in an I 2 C (operation mode 4) G L N G L M11 SIN2_ M8 SIN2_1 Multifunction serial interface ch.2 input pin SIN2_ K14 SOT2_0 (SDA2_0) Multifunction serial interface ch.2 output pin L8 SOT2_1 This pin operates as SOT2 when it is used in a (SDA2_1) UART/CSIO/LIN (operation modes 0 to 3) and as SOT2_2 SDA2 when it is used in an I 2 C (operation mode 4). (SDA2_2) K11 SCK2_0 (SCL2_0) Multifunction serial interface ch.2 clock I/O pin K8 SCK2_1 This pin operates as SCK2 when it is used in a (SCL2_1) UART/CSIO (operation modes 0 to 2) and as F13 SCK2_2 SCL2 when it is used in an I 2 C (operation mode 4). (SCL2_2) J13 SIN3_ P8 SIN3_1 Multifunction serial interface ch.3 input pin SIN3_ M5 SOT3_0 (SDA3_0) SOT3_1 (SDA3_1) SOT3_2 (SDA3_2) SCK3_0 (SCL3_0) SCK3_1 (SCL3_1) SCK3_2 (SCL3_2) Multifunction serial interface ch.3 output pin. This pin operates as SOT3 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA3 when it is used in an I 2 C (operation mode 4). Multifunction serial interface ch.3 clock I/O pin. This pin operates as SCK3 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL3 when it is used in an I 2 C (operation mode 4) J F L P F K5 Document Number: Rev. *D Page 37 of 131

39 Pin function Multi Function Serial 4 Multi Function Serial 5 Multi Function Serial 6 Pin name Function description Pin No. LQFP-176 LQFP-144 BGA-192 SIN4_ C6 SIN4_1 Multifunction serial interface ch.4 input pin J12 SIN4_2 8 8 D3 SOT4_0 Multifunction serial interface ch.4 output pin B6 (SDA4_0) This pin operates as SOT4 when it is used in a SOT4_1 UART/CSIO/LIN (operation modes 0 to 3) and as J11 (SDA4_1) SDA4 when it is used in an I 2 C SOT4_2 (operation mode 4). 9 9 D4 (SDA4_2) SCK4_0 Multifunction serial interface ch.4 clock I/O pin F7 (SCL4_0) This pin operates as SCK4 when it is used in a SCK4_1 UART/CSIO (operation modes 0 to 2) and as J10 (SCL4_1) SCL4 when it is used in an I 2 C SCK4_2 (operation mode 4) (SCL4_2) RTS4_ D7 RTS4_1 Multifunction serial interface ch.4 RTS output pin H10 RTS4_ CTS4_ CTS4_1 Multifunction serial interface ch.4 CTS input pin J9 CTS4_ SIN5_ C5 SIN5_1 Multifunction serial interface ch.5 input pin B10 SIN5_ J3 SOT5_0 (SDA5_0) SOT5_1 (SDA5_1) SOT5_2 (SDA5_2) SCK5_0 (SCL5_0) SCK5_1 (SCL5_1) SCK5_2 (SCL5_2) Multifunction serial interface ch.5 output pin. This pin operates as SOT5 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA5 when it is used in an I 2 C (operation mode 4). Multifunction serial interface ch.5 clock I/O pin. This pin operates as SCK5 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL5 when it is used in an I 2 C (operation mode 4) B C J D K1 SIN6_ F3 SIN6_1 Multifunction serial interface ch.6 input pin 31 - H6 SIN6_ B4 SOT6_0 Multifunction serial interface ch.6 output pin F4 (SDA6_0) This pin operates as SOT6 when it is used in a SOT6_1 UART/CSIO/LIN (operation modes 0 to 3) and as 30 - H5 (SDA6_1) SDA6 when it is used in an I 2 C (operation mode SOT6_2 4) C4 (SDA6_2) SCK6_0 Multifunction serial interface ch.6 clock I/O pin F5 (SCL6_0) This pin operates as SCK6 when it is used in a SCK6_1 UART/CSIO (operation modes 0 to 2) and as 29 - H4 (SCL6_1) SCL6 when it is used in an I 2 C (operation mode SCK6_2 4) B3 (SCL6_2) Document Number: Rev. *D Page 38 of 131

40 Pin function Multi Function Serial 7 Multi Function Serial 8 Multi Function Serial 9 Multi Function Serial 10 SIN7_0 Pin name Function description Pin No. LQFP-176 LQFP-144 BGA G4 SIN7_1 Multifunction serial interface ch.7 input pin K6 SIN7_ H13 SOT7_0 (SDA7_0) SOT7_1 (SDA7_1) SOT7_2 (SDA7_2) SCK7_0 (SCL7_0) SCK7_1 (SCL7_1) SCK7_2 (SCL7_2) Multifunction serial interface ch.7 output pin. This pin operates as SOT7 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA7 when it is used in an I 2 C (operation mode 4). Multifunction serial interface ch.7 clock I/O pin. This pin operates as SCK7 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL7 when it is used in an I 2 C (operation mode 4) G L H G M H11 SIN8_0 Multifunction serial interface ch.8 input pin 2 2 B2 Multifunction serial interface ch.6 output pin. This pin operates as SOT8 when it is used in a SOT8_0 UART/CSIO/LIN (operation modes 0 to 3) and as (SDA8_0) SDA8 when it is used in an I 2 C (operation mode 4). 3 3 C2 SCK8_0 (SCL8_0) Multifunction serial interface ch.7 clock I/O pin. This pin operates as SCK8 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL8 when it is used in an I 2 C (operation mode 4). 4 4 C3 SIN9_0 Multifunction serial interface ch.9 input pin 5 5 D5 Multifunction serial interface ch.9 output pin. This pin operates as SOT9 when it is used in a SOT9_0 UART/CSIO/LIN (operation modes 0 to 3) and as (SDA9_0) SDA9 when it is used in an I 2 C (operation mode 4). 6 6 D2 SCK9_0 (SCL9_0) Multifunction serial interface ch.9 clock I/O pin. This pin operates as SCK9 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL9 when it is used in an I 2 C (operation mode 4). 7 7 D1 SIN10_0 Multifunction serial interface ch.10 input pin N2 Multifunction serial interface ch.10 output pin. This pin operates as SOT10 when it is used in a SOT10_0 UART/CSIO/LIN (operation modes 0 to 3) and as (SDA10_0) SDA10 when it is used in an I 2 C (operation mode 4) N3 SCK10_0 (SCL10_0) Multifunction serial interface ch.10 clock I/O pin. This pin operates as SCK10 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL10 when it is used in an I 2 C (operation mode 4) M3 Document Number: Rev. *D Page 39 of 131

41 Pin function Multi Function Serial 11 Multi Function Serial 12 Multi Function Serial 13 Multi Function Serial 14 Multi Function Serial 15 Pin name Function description Pin No. LQFP-176 LQFP-144 BGA-192 SIN11_0 Multifunction serial interface ch.11 input pin L4 Multifunction serial interface ch.11 output pin. This pin operates as SOT11 when it is used in a SOT11_0 UART/CSIO/LIN (operation modes 0 to 3) and as (SDA11_0) SDA11 when it is used in an I 2 C M4 (operation mode 4). SCK11_0 (SCL11_0) Multifunction serial interface ch.11 clock I/O pin. This pin operates as SCK11 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL11 when it is used in an I 2 C (operation mode 4) N4 SIN12_0 Multifunction serial interface ch.12 input pin F10 Multifunction serial interface ch.12 output pin. This pin operates as SOT12 when it is used in a SOT12_0 UART/CSIO/LIN (operation modes 0 to 3) and as (SDA12_0) SDA12 when it is used in an I 2 C (operation mode 4) F11 SCK12_0 (SCL12_0) Multifunction serial interface ch.12 clock I/O pin. This pin operates as SCK12 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL12 when it is used in an I 2 C (operation mode 4) F12 SIN13_0 Multifunction serial interface ch.13 input pin C9 Multifunction serial interface ch.13 output pin. This pin operates as SOT13 when it is used in a SOT13_0 UART/CSIO/LIN (operation modes 0 to 3) and as (SDA13_0) SDA13 when it is used in an I 2 C (operation mode 4) B8 SCK13_0 (SCL13_0) Multifunction serial interface ch.13 clock I/O pin. This pin operates as SCK13 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL13 when it is used in an I 2 C (operation mode 4) D9 SIN14_0 Multifunction serial interface ch.14 input pin F9 Multifunction serial interface ch.14 output pin. This pin operates as SOT14 when it is used in a SOT14_0 UART/CSIO/LIN (operation modes 0 to 3) and as (SDA14_0) SDA14 when it is used in an I 2 C (operation mode 4) C8 SCK14_0 (SCL14_0) Multifunction serial interface ch.14 clock I/O pin. This pin operates as SCK14 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL14 when it is used in an I 2 C (operation mode 4) D8 SIN15_0 Multifunction serial interface ch.15 input pin A10 Multifunction serial interface ch.15 output pin. This pin operates as SOT15 when it is used in a SOT15_0 UART/CSIO/LIN (operation modes 0 to 3) and as (SDA15_0) SDA15 when it is used in an I 2 C (operation mode 4) F8 SCK15_0 (SCL15_0) Multifunction serial interface ch.15 clock I/O pin. This pin operates as SCK15 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL15 when it is used in an I 2 C (operation mode 4) B7 Document Number: Rev. *D Page 40 of 131

42 Pin function Multi Function Timer 0 Pin name Function description Pin No LQFP-176 LQFP-144 BGA-192 DTTI0X_0 signal controlling wave form generator outputs RTO00 to RTO05 of multi-function K2 DTTI0X_1 timer H10 FRCK0_ J5 FRCK0_1 16-bit free-run timer ch.0 external clock input pin H9 FRCK0_ M12 IC00_ K1 IC00_ J12 IC00_ L13 IC01_ J2 IC01_ J11 16-bit input capture ch.0 input pin of multi-function IC01_ L12 timer 0. IC02_ J3 ICxx describes channel number. IC02_ J10 IC02_ L11 IC03_ J4 IC03_ J9 IC03_ K13 RTO00_0 Wave form generator output of multi-function (PPG00_0) timer K3 RTO00_1 This pin operates as PPG00 when it is used in (PPG00_1) PPG0 output modes RTO01_0 Wave form generator output of multi-function (PPG00_0) timer K4 RTO01_1 This pin operates as PPG00 when it is used in (PPG00_1) PPG0 output modes RTO02_0 Wave form generator output of multi-function (PPG02_0) timer L1 RTO02_1 This pin operates as PPG02 when it is used in (PPG02_1) PPG0 output modes RTO03_0 Wave form generator output of multi-function (PPG02_0) timer L2 RTO03_1 This pin operates as PPG02 when it is used in (PPG02_1) PPG0 output modes F13 RTO04_0 Wave form generator output of multi-function (PPG04_0) timer L3 RTO04_1 This pin operates as PPG04 when it is used in (PPG04_1) PPG0 output modes F12 RTO05_0 Wave form generator output of multi-function (PPG04_0) timer M2 RTO05_1 This pin operates as PPG04 when it is used in (PPG04_1) PPG0 output modes F11 IGTRG0_ N6 PPG IGBT mode external trigger input pin IGTRG0_ B3 Document Number: Rev. *D Page 41 of 131

43 Pin function Quadrature Position/ Revolution Counter 0 Quadrature Position/ Revolution Counter 1 AIN0_0 Pin name Function description Pin No LQFP-176 LQFP-144 BGA H3 AIN0_1 QPRC ch.0 AIN input pin L5 AIN0_ BIN0_ H4 BIN0_1 QPRC ch.0 BIN input pin K5 BIN0_ F1 ZIN0_ H5 ZIN0_1 QPRC ch.0 ZIN input pin N6 ZIN0_ F2 AIN1_ N9 AIN1_1 QPRC ch.1 AIN input pin D13 AIN1_ M6 BIN1_ M9 BIN1_1 QPRC ch.1 BIN input pin D12 BIN1_ L6 ZIN1_ L9 ZIN1_1 QPRC ch.1 ZIN input pin ZIN1_ K6 USB UDM0 USB ch.0 device/host D pin A3 CAN Real-time clock UDP0 USB ch.0 device/host D + pin A2 UHCONX TX0_0 USB ch.0 USB external pull-up control pin B J6 TX0_1 CAN interface ch.0 TX output 32 - J5 TX0_2 7 7 D1 RX0_ N8 RX0_1 CAN interface ch.0 RX output 33 - J4 RX0_2 6 6 D2 RTCCO_ RTCCO_1 0.5 seconds pulse output pin of Real-time clock L12 RTCCO_ K2 SUBOUT_ SUBOUT_1 Sub clock output pin L12 SUBOUT_ K2 Document Number: Rev. *D Page 42 of 131

44 Reset Mode Power Pin function Pin name INITX MD0 MD1 VCC Function description xternal Reset. A reset is valid when INITX="L". Mode 0 Pin. During normal operation, MD0="L" must be input. During serial programming to Flash memory, MD0="H" must be input. Mode 1 Pin. During serial programming to Flash memory, MD1="L" must be input. Power supply Pin Pin No LQFP-176 LQFP-144 BGA N N N C N P M C14 Low-Power Consumption Mode HDMI- CC/ Remote Control Reception A A9 USBVCC 3.3V Power supply port for USB I/O A4 WKUP0 Deep standby mode return signal input pin C13 WKUP1 Deep standby mode return signal input pin M12 WKUP2 Deep standby mode return signal input pin M8 WKUP3 Deep standby mode return signal input pin B3 WKUP4 Deep standby mode return signal input pin H3 WKUP5 Deep standby mode return signal input pin C5 CC0_0 HDMI-CC/Remote Control Reception ch M10 CC0_1 input/output pin F9 CC1_0 HDMI-CC/Remote Control Reception ch B3 CC1_1 input/output pin F6 DAC DA0_0 D/A converter ch.0 analog output pin C9 DA1_0 D/A converter ch.1 analog output pin B8 Document Number: Rev. *D Page 43 of 131

45 GND Pin function Pin name Function description Pin No LQFP-176 LQFP-144 BGA A A A G G H8 - - M1 - - P3 - - P7 - - N7 VSS GND Pin - - M7 - - L7 - - K7 - - J7 - - P N L B H7 - - B1 - - G1 - - J1 Clock X0 Main clock (oscillation) input pin P12 X0A Sub clock (oscillation) input pin P5 X1 Main clock (oscillation) I/O pin P13 X1A Sub clock (oscillation) I/O pin P6 CROUT_ D13 Built-in high-speed CR-osc clock output port CROUT_ Analog AVCC A/D converter, D/A converter analog power pin J14 Power AVRH A/D converter analog reference voltage input pin F14 Analog AVSS A/D converter, D/A converter GND pin H14 GND AVRL A/D converter analog reference voltage input pin G14 C pin C Power supply stabilization capacity pin P2 *: 5V tolerant I/O Note: While this device contains a Test Access Port (TAP) based on the I JTAG standard, it is not fully compliant to all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP controller. Document Number: Rev. *D Page 44 of 131

46 5. I/O Circuit Type Type Circuit Remarks A It is possible to select the main oscillation / GPIO function Pull-up resistor When the main oscillation is. X1 P-ch P-ch Digital output Oscillation feedback resistor : Approximately 1 MΩ With Standby mode control When the GPIO is. R N-ch Digital output Pull-up resistor control Digital input CMOS level output. CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kω IOH = -4 ma, IOL = 4 ma Standby mode control Feedback resistor Clock input Standby mode control Digital input Pull-up Standby mode control R resistor X0 P-ch P-ch Digital output N-ch Digital output Pull-up resistor control B Pull-up resistor CMOS level hysteresis input Pull-up resistor : Approximately 50 kω Digital input Document Number: Rev. *D Page 45 of 131

47 Type Circuit Remarks C Digital input Open drain output CMOS level hysteresis input N-ch Digital output D It is possible to select the sub oscillation / GPIO function Pull-up resistor When the sub oscillation is. X1A P-ch P-ch Digital output Oscillation feedback resistor : Approximately 5 MΩ With Standby mode control When the GPIO is. R N-ch Digital output Pull-up resistor control Digital input CMOS level output. CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kω IOH = -4 ma, IOL = 4 ma Standby mode control Feedback resistor Clock input Standby mode control Digital input Pull-up Standby mode control R resistor X0A P-ch P-ch Digital output N-ch Digital output Pull-up resistor control Document Number: Rev. *D Page 46 of 131

48 Type Circuit Remarks R P-ch P-ch N-ch Digital output Digital output CMOS level output CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kω IOH = -4 ma, IOL = 4 ma When this pin is used as an I 2 C pin, the digital output P-ch transistor is always off +B input available Pull-up resistor control Digital input Standby mode control F P-ch P-ch Digital output CMOS level output CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kω IOH = -12 ma, IOL = 12 ma +B input available R N-ch Digital output Pull-up resistor control Digital input Standby mode control Document Number: Rev. *D Page 47 of 131

49 Type Circuit Remarks G P-ch P-ch N-ch Digital output Digital output CMOS level output CMOS level hysteresis input With input control Analog input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kω IOH = -4 ma, IOL = 4 ma When this pin is used as an I 2 C pin, the digital output P-ch transistor is always off +B input available R Pull-up resistor control Digital input Standby mode control Analog input control H P-ch P-ch N-ch Digital output Digital output CMOS level output CMOS level hysteresis input With input control Analog output With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kω IOH = -4 ma, IOL = 4 ma R Pull-up resistor control Digital input Standby mode Control Analog output Document Number: Rev. *D Page 48 of 131

50 Type Circuit Remarks I R P-ch P-ch N-ch Digital output Digital output CMOS level output CMOS level hysteresis input 5V tolerant With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50 kω IOH = -4 ma, IOL = 4 ma Available to control PZR registers. When this pin is used as an I 2 C pin, the digital output P-ch transistor is always off Pull-up resistor control Digital input Standby mode control J CMOS level hysteresis input Mode input K It is possible to select the USB I/O / GPIO function. GPIO Digital output UDP0/P81 Differential UDM0/P80 GPIO Digital input/output direction GPIO Digital input GPIO Digital input circuit control UDP output USB Full-speed/Low-speed control UDP input Differential input USB/GPIO select UDM input UDM output When the USB I/O is. Full-speed, Low-speed control When the GPIO is. CMOS level output CMOS level hysteresis input With standby mode control USB Digital input/output direction GPIO Digital output GPIO Digital input/output direction GPIO Digital input GPIO Digital input circuit control Document Number: Rev. *D Page 49 of 131

51 6. Handling Precautions Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices. 6.1 Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices. Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. 1. Preventing Over-Voltage and Over-Current Conditions xposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. 2. Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. 3. Handling of Unused Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin. Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred ma to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: 1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. 2. Be sure that abnormal current flows do not occur during the power-on sequence. Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Document Number: Rev. *D Page 50 of 131

52 Precautions Related to Usage of Devices Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 6.2 Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Cypress recommended conditions. For detailed information about mount conditions, contact your sales representative. Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended conditions. Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: 1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. 2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5 C and 30 C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. 3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. 4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust. Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended conditions for baking. Condition: 125 C/24 h Document Number: Rev. *D Page 51 of 131

53 Static lectricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: 1. relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. 2. lectrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. 3. liminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. 4. Ground all fixtures and instruments, or protect with anti-static measures. 5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies. 6.3 Precautions for Use nvironment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: 1. Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. 2. Discharge of Static lectricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. 3. Corrosive Gases, Dust, or Oil xposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. 4. Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. 5. Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Cypress products in other special environmental conditions should consult with sales representatives. Document Number: Rev. *D Page 52 of 131

54 7. Handling Devices Power supply pins In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µf be connected as a bypass capacitor between each Power supply pin and GND pin near this device. Stabilizing power supply voltage A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a momentary fluctuation on switching the power supply. Crystal oscillator circuit Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1, X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by ground plane as this is expected to produce stable operation. valuate oscillation of your using crystal oscillator by your mount board. Sub crystal oscillator This series sub oscillator circuit is low gain to keep the low current consumption. The crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation. Surface mount type Size: More than 3.2 mm 1.5 mm Load capacitance: Approximately 6 pf to 7 pf Lead type Load capacitance: Approximately 6 pf to 7 pf Using an external clock When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1(P3) can be used as a general-purpose I/O port. Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input, and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port. xample of Using an xternal Clock Device Can be used as general-purpose I/O ports. X0(X0A) X1(P3), X1A (P47) Set as xternal clock input Document Number: Rev. *D Page 53 of 131

55 Handling when using Multi-function serial pin as I 2 C pin If it is using the multi-function serial pin as I 2 C pins, P-ch transistor of digital output is always disabled. However, I 2 C pins need to keep the electrical characteristic like other pins and not to connect to the external I 2 C bus system with power OFF. C Pin This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. A smoothing capacitor of about 4.7μF would be recommended for this series. C Device CS VSS GND Mode pins (MD0) Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is because of preventing the device erroneously switching to test mode due to noise. Notes on power-on Turn power on/off in the following order or at the same time. If not using the A/D converter and D/A converter, connect AVCC = VCC and AVSS = VSS. Turning on : VCC USBVCC VCC AVCC AVRH Turning off : AVRH AVCC VCC USBVCC VCC Serial Communication There is a possibility to receive wrong data due to the noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. If an error is detected, retransmit the data. Differences in features among the products with different memory sizes and between Flash memory products and MASK products The electric characteristics including power consumption, SD, latch-up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between Flash memory products and MASK products are different because chip layout and memory structures are different. If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics. Document Number: Rev. *D Page 54 of 131

56 Pull-Up function of 5V tolerant I/O Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5V tolerant I/O. Adjoining wiring on circuit board If wiring of the crystal oscillation circuit (X0/X1 and X0A/X1A) adjoins and also runs in parallel with the wiring of GPIO, there is a possibility that the oscillation erroneously counts because oscillation wave has noise with the change of GPIO. Keep as much distance as possible between both wirings and insert the ground pattern between them in order to avoid this possibility. Document Number: Rev. *D Page 55 of 131

57 8. Block Diagram TRSTX,TCK, TDI,TMS TDO TRACDx, TRACCLK INITX SWJ-DP TPIU Cortex-M3 MHz(Max) Dual-Timer Clock Reset Generator WatchDog Timer (Hardware) CSV NVIC WatchDog Timer (Software) TM ROM Table I D Sys AHB-APB Bridge: APB0(Max 32 MHz) Multi-layer AHB (Max 60 MHz) Flash I/F Security SRAM0 80/96 Kbytes SRAM1 80/96 Kbytes On-Chip Flash 1 Mbytes+64 Kbytes/ 1.5 Mbytes+64 Kbytes USB2.0 PHY (Host/ (Host /Device) Func) DMAC 8ch. UDP0/UDM0 UHCONX CLK X0 X1 X0A X1A CROUT AVCC, AVSS, AVRH ANxx ADTGx DAx TIOAx TIOBx AINx BINx ZINx IC0x FRCK0 DTTI0X RTO0x IGTRGx Main Osc Sub Osc 12-bit A/D Converter Unit 0 Unit 1 PLL CR 4 MHz 10-bit D/Aconverter 2 Units Base Timer 16-bit 16ch./ 32-bit 8ch. QPRC 2ch. A/D Activation Compare 2ch. 16-bit Capture 4ch. 16-bit Free-run Timer 3ch. 16-bit Output Compare 6ch. Waveform Generator 3ch. 16-bit PPG 3ch. Multi-function Timer 1 Source Clock CR 100 khz AHB-APB Bridge : APB1 (Max 32 MHz) AHB-APB Bridge : APB2 (Max 32 MHz) AHB-AHB Bridge xternal Bus I/F CAN Prescaler USB Clock Ctrl LVD Ctrl IRQ-Monitor CRC Accelerator Watch Counter Deep Standby Ctrl HDMI-CC/ Remote Reciver Control Real-Time Clock xternal Interrupt Controller 32pin + NMI MOD-Ctrl GPIO Multi-function Serial I/F 16ch. HW flow control(ch.4) PLL CAN 1ch. Power-On Reset LVD Regulator PIN-Function-Ctrl TX0_x, RX0_x MADx MADATAx MCSXx,MDQMx, MOX,MWX, MAL,MRDY, MNAL,MNCL, MNWX,MNRX, MCLKOUT C WKUPx CC0_x, CC1_x RTCCO, SUBOUT INTx NMIX MD0, MD1 P0x, P1x,... PFx SCKx SINx SOTx CTS4 RTS4 Document Number: Rev. *D Page 56 of 131

58 9. Memory Size See Memory size in 1. Product Lineup to confirm the memory size. 10. Memory Map Memory Map (1) 0x41FF_FFFF Peripherals Area See " Memory map(2)" for the memory size details. 0xFFFF_FFFF Reserved 0x010_0000 Cortex-M3 Private 0x4006_3000 0x000_0000 Peripherals 0x4006_2000 CAN ch.0 0x4006_1000 Reserved 0x4006_0000 DMAC 0x4005_0000 Reserved Reserved 0x4004_0000 USB ch.0 0x4003_F000 XT-bus I/F 0x4003_C000 Reserved 0x7000_0000 0x4003_B000 RTC xternal Device 0x4003_A000 Watch Counter 0x6000_0000 Area 0x4003_9000 CRC 0x4003_8000 MFS Reserved 0x4003_7000 CAN Prescaler 0x4400_0000 0x4003_6000 USB Clock Ctrl 0x4003_5000 LVD/DS mode 32Mbytes HDMI-CC/ Bit band alias 0x4200_0000 0x4003_4000 Remote Control Receiver 0x4003_3000 GPIO Peripherals 0x4000_0000 0x4003_2000 Reserved 0x4003_1000 Int-Req.Read Reserved 0x2400_0000 0x4003_0000 XTI 32Mbytes 0x4002_F000 Reserved 0x2200_0000 Bit band alias 0x4002_000 CR Trim 0x4002_9000 Reserved Reserved 0x2001_8000 0x4002_8000 D/AC 0x2000_0000 SRAM1 0x4002_7000 A/DC 0x1FF_8000 SRAM0 0x4002_6000 QPRC 0x4002_5000 Base Timer Reserved 0x0051_8000 0x4002_4000 PPG 0x0050_8000 Flash(Work area) 0x0040_4000 Reserved Reserved 0x0040_0000 Security/CR Trim 0x4002_1000 0x4002_0000 Reserved MFT unit0 0x0000_0000 Flash(Main area) 0x4001_6000 0x4001_5000 0x4001_3000 0x4001_2000 0x4001_1000 0x4001_0000 0x4000_1000 0x4000_0000 Reserved Dual Timer Reserved SW WDT HW WDT Clock/Reset Reserved Flash I/F Document Number: Rev. *D Page 57 of 131

59 Flash (Work area, ROM1) 64Kbytes Flash (Work area, ROM1) 64Kbytes Flash (Main area, ROM1) 512Kbytes Flash (Main area, ROM0) 1Mbytes Flash (Main area, ROM0) 1Mbytes Memory Map (2) MB9BF529SA/TA MB9BF528SA/TA 0x2008_0000 0x2008_0000 0x2001_8000 Reserved Reserved SRAM1 80Kbytes 0x2001_4000 SRAM1 64Kbytes 0x2000_4000 0x2000_4000 0x2000_0000 SRAM1 16Kbytes* 0x2000_0000 SRAM1 16Kbytes* 0x1FFF_C000 SRAM0 16Kbytes* 0x1FFF_C000 SRAM0 16Kbytes* SRAM0 80Kbytes 0x1FF_C000 SRAM0 64Kbytes 0x1FF_8000 Reserved Reserved 0x0051_8000 0x0051_8000 0x0050_8000 ROM1_SA0-7(8KBx8) 0x0050_8000 ROM1_SA0-7(8KBx8) Reserved Reserved 0x0040_4000 0x0040_4000 0x0040_2000 CR trimming 0x0040_2000 CR trimming 0x0040_0000 Security 0x0040_0000 Security Reserved 0x0018_0000 Reserved ROM1_SA8_15(64KBx8) ROM1_SA8-15(8KBx8) 0x0010_0000 0x0010_0000 ROM0_SA9-23(64KBx15) ROM0_SA9-23(64KBx15) ROM0_SA8(48KB) ROM0_SA8(48KB) 0x0000_0000 ROM0_SA2-3(8KBx2) 0x0000_0000 ROM0_SA2-3(8KBx2) The content of SRAM can be retained at the deep standby modes by the setting of Deep Standby RAM Retention Register (DSRAMR). See "MB9B520T/420T/320T/120T Series Flash Programming Manual" for sector structure of Flash. Document Number: Rev. *D Page 58 of 131

60 Peripheral Address Map Start address nd address Bus Peripherals 0x4000_0000 0x4000_0FFF Flash Memory I/F register AHB 0x4000_1000 0x4000_FFFF Reserved 0x4001_0000 0x4001_0FFF Clock/Reset Control 0x4001_1000 0x4001_1FFF Hardware Watchdog timer 0x4001_2000 0x4001_2FFF Software Watchdog timer APB0 0x4001_3000 0x4001_4FFF Reserved 0x4001_5000 0x4001_5FFF Dual-Timer 0x4001_6000 0x4001_FFFF Reserved 0x4002_0000 0x4002_0FFF Multi-function timer unit0 0x4002_1000 0x4002_3FFF Reserved 0x4002_4000 0x4002_4FFF PPG 0x4002_5000 0x4002_5FFF Base Timer 0x4002_6000 0x4002_6FFF Quadrature Position/Revolution Counter (QPRC) APB1 0x4002_7000 0x4002_7FFF A/D Converter 0x4002_8000 0x4002_8FFF D/A Converter 0x4002_9000 0x4002_DFFF Reserved 0x4002_000 0x4002_FFF Built-in CR trimming 0x4002_F000 0x4002_FFFF Reserved 0x4003_0000 0x4003_0FFF xternal Interrupt 0x4003_1000 0x4003_1FFF Interrupt Source Check Resister 0x4003_2000 0x4003_2FFF Reserved 0x4003_3000 0x4003_3FFF GPIO 0x4003_4000 0x4003_4FFF HDMI-CC/Remote control Reception 0x4003_5000 0x4003_57FF Low-Voltage Detector 0x4003_5800 0x4003_5FFF Deep standby mode Controller 0x4003_6000 0x4003_6FFF APB2 USB clock generator 0x4003_7000 0x4003_7FFF CAN prescaler 0x4003_8000 0x4003_8FFF Multi-function serial Interface 0x4003_9000 0x4003_9FFF CRC 0x4003_A000 0x4003_AFFF Watch Counter 0x4003_B000 0x4003_BFFF Real-time clock 0x4003_C000 0x4003_FFF Reserved 0x4003_F000 0x4003_FFFF xternal bus interface 0x4004_0000 0x4004_FFFF USB ch.0 0x4005_0000 0x4005_FFFF Reserved 0x4006_0000 0x4006_0FFF DMAC register AHB 0x4006_1000 0x4006_1FFF Reserved 0x4006_2000 0x4006_2FFF CAN ch.0 0x4006_3000 0x41FF_FFFF Reserved Document Number: Rev. *D Page 59 of 131

61 11. Pin Status in ach CPU State The terms used for pin status have the following meanings. INITX=0 INITX=1 SPL=0 SPL=1 This is the period when the INITX pin is the "L" level. This is the period when the INITX pin is the "H" level. This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to "0". This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to "1". Indicates that the input function can be used. Hi-Z This is the status that the input function cannot be used. input is fixed at "L". Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z. Setting disabled Indicates that the setting is disabled. s the that was immediately prior to entering the current mode. If a built-in peripheral function is operating, the output follows the peripheral function. If the pin is being used as a port, that output is maintained. Analog input is Indicates that the analog input is. Trace output Indicates that the trace function can be used. GPIO In Deep standby mode, pins switch to the general-purpose I/O port. Document Number: Rev. *D Page 60 of 131

62 Pin status type List of Pin Status Function group Power-on reset or low-voltage detection INITX input Device internal reset Run mode or SLP mode Timer mode, RTC mode, or STOP mode Deep standby RTC mode or Deep standby STOP mode Return from Deep standby mode A GPIO Main crystal oscillator input pin/ xternal main clock input GPIO Power supply unstable Setting disabled Setting disabled Power supply stable Power supply stable Power supply stable Power supply stable Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = SPL = 0 SPL = 1 SPL = 0 SPL = 1 - Setting disabled Setting disabled Setting disabled Setting disabled GPIO GPIO GPIO GPIO xternal main clock input Setting disabled Setting disabled Setting disabled B Main crystal oscillator output pin input fixed / or enable input fixed at "0" input fixed at "0" / When oscillation stops* 1, / When oscillation stops* 1, / When oscillation stops* 1, / When oscillation stops* 1, / When oscillation stops* 1, / When oscillation stops* 1, C INITX input pin Pull-up / Pull-up / Pull-up / Pull-up / Pull-up / Pull-up / Pull-up / Pull-up / Pull-up / D Mode input pin Document Number: Rev. *D Page 61 of 131

63 Pin status type Function group Power-on reset or low-voltage detection Power supply unstable INITX input Device internal reset Power supply stable Run mode or SLP mode Power supply stable Timer mode, RTC mode, or STOP mode Power supply stable Deep standby RTC mode or Deep standby STOP mode Power supply stable Return from Deep standby mode Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = SPL = 0 SPL = 1 SPL = 0 SPL = 1 - Mode input pin GPIO Setting disabled Setting disabled Setting disabled GPIO GPIO GPIO Setting disabled Setting disabled Setting disabled GPIO GPIO F Sub crystal oscillator input pin / xternal sub clock input GPIO Setting disabled Setting disabled Setting disabled GPIO GPIO G xternal sub clock input Sub crystal oscillator output pin Setting disabled input fixed / or enable Setting disabled input fixed at "0" Setting disabled input fixed at "0" / When oscillation stops* 2, / When oscillation stops* 2, / When oscillation stops* 2, Hi-Z/ Hi-Z/ / When oscillation stops* 2, Hi-Z/ / When oscillation stops* 2, Hi-Z/ Document Number: Rev. *D Page 62 of 131

64 Pin status type H Function group NMIX GPIO Power-on reset or low-voltage detection Power supply unstable Setting disabled Hi-Z INITX input Device internal reset Power supply stable Run mode or SLP mode Power supply stable Timer mode, RTC mode, or STOP mode Power supply stable Deep standby RTC mode or Deep standby STOP mode Power supply stable Return from Deep standby mode Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = SPL = 0 SPL = 1 SPL = 0 SPL = 1 - Setting disabled Setting disabled WKUP input WKUP input GPIO I JTAG GPIO Hi-Z Setting disabled Pull-up / Setting disabled Pull-up / Setting disabled GPIO GPIO J K Resource GPIO xternal interrupt Resource other than above GPIO Hi-Z Setting disabled Hi-Z Setting disabled Setting disabled GPIO GPIO GPIO GPIO L Analog input Resource other than above GPIO Hi-Z Setting disabled input fixed at "0" / Analog input Setting disabled input fixed at "0" / Analog input Setting disabled / Analog input / Analog input / Analog input / Analog input GPIO / Analog input / Analog input GPIO Document Number: Rev. *D Page 63 of 131

65 Pin status type M N Function group Analog input xternal interrupt Resource other than above GPIO Analog input WKUP xternal interrupt Resource other than above GPIO Power-on reset or low-voltage detection Power supply unstable Hi-Z Setting disabled Hi-Z Setting disabled INITX input Device internal reset Power supply stable Run mode or SLP mode Power supply stable Timer mode, RTC mode, or STOP mode Power supply stable Deep standby RTC mode or Deep standby STOP mode Power supply stable Return from Deep standby mode Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = SPL = 0 SPL = 1 SPL = 0 SPL = 1 - input fixed at "0" / Analog input Setting disabled input fixed at "0" / Analog input Setting disabled input fixed at "0" / Analog input Setting disabled input fixed at "0" / Analog input Setting disabled / Analog input / Analog input / Analog input / Analog input / Analog input / Analog input / Analog input GPIO / Analog input WKUP input GPIO / Analog input / Analog input WKUP input / Analog input GPIO / Analog input GPIO Document Number: Rev. *D Page 64 of 131

66 Pin status type O Function group Analog output Resource other than above GPIO Power-on reset or low-voltage detection Power supply unstable Setting disabled Hi-Z INITX input Device internal reset Power supply stable Run mode or SLP mode Power supply stable Timer mode, RTC mode, or STOP mode Power supply stable Deep standby RTC mode or Deep standby STOP mode Power supply stable Return from Deep standby mode Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = SPL = 0 SPL = 1 SPL = 0 SPL = 1 - Setting disabled Setting disabled *3 *4 GPIO GPIO P Trace Resource other than above GPIO Setting disabled Hi-Z Setting disabled Setting disabled Trace output GPIO GPIO Q Trace xternal interrupt Resource other than above GPIO Setting disabled Hi-Z Setting disabled Setting disabled Trace output GPIO GPIO CC Setting disabled Setting disabled Setting disabled R Resource other than above GPIO Hi-Z GPIO GPIO Document Number: Rev. *D Page 65 of 131

67 Pin status type S Function group CC xternal interrupt Resource other than above GPIO Power-on reset or low-voltage detection Power supply unstable Setting disabled Hi-Z INITX input Device internal reset Power supply stable Run mode or SLP mode Power supply stable Timer mode, RTC mode, or STOP mode Power supply stable Deep standby RTC mode or Deep standby STOP mode Power supply stable Return from Deep standby mode Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = SPL = 0 SPL = 1 SPL = 0 SPL = 1 - Setting disabled Setting disabled GPIO GPIO CC T WKUP xternal interrupt Resource other than above GPIO Setting disabled Hi-Z Setting disabled Setting disabled WKUP input GPIO WKUP input GPIO U WKUP xternal interrupt Resource other than above GPIO Setting disabled Hi-Z Setting disabled Setting disabled WKUP input GPIO WKUP input GPIO Document Number: Rev. *D Page 66 of 131

68 Pin status type Function group GPIO Power-on reset or low-voltage detection Power supply unstable Hi-Z INITX input Device internal reset Power supply stable Run mode or SLP mode Power supply stable Timer mode, RTC mode, or STOP mode Power supply stable Deep standby RTC mode or Deep standby STOP mode Power supply stable Return from Deep standby mode Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = SPL = 0 SPL = 1 SPL = 0 SPL = 1 - GPIO GPIO V USB I/O pin Setting disabled Setting disabled Setting disabled Hi-Z at transmission/ / at reception Hi-Z at transmission/ / at reception *1: Oscillation is stopped at Sub timer mode, Low-speed CR timer mode, RTC mode, STOP mode, Deep standby RTC mode, and Deep standby STOP mode. *2: Oscillation is stopped at STOP mode and Deep standby STOP mode. *3: at timer mode. GPIO at RTC mode, STOP mode. *4: at timer mode. Hi-Z/ at RTC mode, STOP mode. Document Number: Rev. *D Page 67 of 131

69 12. lectrical Characteristics 12.1 Absolute Maximum Ratings Parameter Symbol Rating Min Max Unit Power supply voltage* 1, * 2 V CC V SS V SS V Power supply voltage (for USB)* 1, * 3 USBV CC V SS V SS V Analog power supply voltage* 1, * 4 AV CC V SS V SS V Analog reference voltage* 1, * 4 AVRH V SS V SS V voltage* 1 V I V SS Analog pin input voltage* 1 V IA V SS Output voltage* 1 V O V SS V CC ( 6.5 V) V Remarks xcept for USB pin V SS USBV CC ( 6.5 V) V USB pin V SS V SS V 5V tolerant V SS V SS V 5V tolerant* 8 AV CC ( 6.5 V) V CC ( 6.5 V) Clamp maximum current I CLAMP ma *9 Clamp total maximum current Σ[I CLAMP] +20 ma *9 "L" level maximum output current* 5 I OL - 10 ma 4mA type 20 ma 12mA type 39 ma P80, P81 4 ma 4mA type "L" level average output current* 6 I OLAV - 12 ma 12mA type 16.5 ma P80, P81 "L" level total maximum output current I OL ma "L" level total average output current* 7 I OLAV - 50 ma "H" level maximum output current* 5 I OH ma 4mA type - 20 ma 12mA type - 39 ma P80, P81-4 ma 4mA type "H" level average output current* 6 I OHAV ma 12mA type - 18 ma P80, P81 "H" level total maximum output current I OH ma "H" level total average output current* 7 I OHAV ma Power consumption P D mw Storage temperature T STG C *1: These parameters are based on the condition that VSS = AVSS = 0 V. *2: VCC must not drop below VSS V. *3: USBVCC must not drop below VSS V. *4: nsure that the voltage does not exceed VCC V, for example, when the power is turned on. *5: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *6: The average output current is defined as the average current value flowing through any one of the corresponding pins for a 100 ms period. *7: The total average output current is defined as the average current value flowing through all of corresponding pins for a 100 ms. *8: VCC = USBVCC = AVCC = AVRH = VSS = AVSS = AVRL = 0.0 V V V Document Number: Rev. *D Page 68 of 131

70 *9: See 4. List of Pin Functions and 5. I/O Circuit Type about +B input available pin. Use within recommended operating conditions. Use at DC voltage (current) the +B input. The +B signal should always be applied a limiting resistance placed between the +B signal and the device. The value of the limiting resistance should be set so that when the +B signal is applied the input current to the device pin does not exceed rated values, either instantaneously or for prolonged periods. Note that when the device drive current is low, such as in the low-power consumption modes, the +B input potential may pass through the protective diode and increase the potential at the VCC and AVCC pin, and this may affect other devices. Note that if a +B signal is input when the device power supply is off (not fixed at 0 V), the power supply is provided from the pins, so that incomplete operation may result. The following is a recommended circuit example (I/O equivalent circuit). Protection Diode VCC VCC +B input (0V to 16V) Limiting resistor P-ch N-ch Digital output R AVCC Digital input Analog input WARNING: Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings. Document Number: Rev. *D Page 69 of 131

71 12.2 Recommended Operating Conditions (VSS = AVSS = 0.0V) Parameter Symbol Conditions Value Min Max Unit Remarks Power supply voltage V CC - 2.7* V * 1 Power supply voltage (3V power supply) for ( V CC) USBV CC - V USB * 2 ( V CC) Analog power supply voltage AV CC V AV CC = V CC Analog reference voltage AVRH AV CC V AVRL - AV SS AV SS V Smoothing capacitor C S μf For built-in Regulator* 3 Operating temperature T A C *1: When P81/UDP0 and P80/UDM0 pins are used as USB (UDP0, UDM0). *2: When P81/UDP0 and P80/UDM0 pins are used as GPIO (P81, P80). *3: See C Pin in 7. Handling Devices for the connection of the smoothing capacitor. *4: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction execution and low voltage detection function by built-in High-speed CR (including Main PLL is used) or built-in Low-speed CR is possible to operate only. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. Any use of semiconductor devices will be under their recommended operating condition. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. Document Number: Rev. *D Page 70 of 131

72 12.3 DC Characteristics Current Rating Symbol Parameter (Pin name) Conditions Value Typ* 1 Max* 2 Unit Remarks PLL RUN mode CPU: 60 MHz, Peripheral: 30 MHz * 3,* 5 CPU: 60 MHz, Peripheral clock stops * 3,* ma ma I CC High-speed CR RUN mode CPU/ Peripheral: 4 MHz* 4 * ma Sub RUN mode CPU/ Peripheral: 32 khz * 3,* µa Low-speed CR RUN mode CPU/ Peripheral: 100 khz * µa Power supply current I CCS I CCH I CCT I CCR PLL SLP mode High-speed CR SLP mode Sub SLP mode Low-speed CR SLP mode STOP mode Main TIMR mode Sub TIMR mode RTC mode Peripheral: 30 MHz * 3,* 5 Peripheral: 4 MHz* 4 * 3 Peripheral: 32 khz * 3,* 6 Peripheral: 100 khz * 3 T A = + 25 C * 3 T A = C * 3 T A = + 25 C * 3,* 6 T A = C * 3,* 6 T A = + 25 C * 3,* 6 T A = C * 3,* 6 T A = + 25 C * 3,* 6 T A = C * 3,* ma ma µa µa μa ma ma ma μa ma μa ma *1: TA =+25 C, VCC = 3.3 V *2: TA =+105 C, VCC = 5.5 V *3: When all ports are fixed. *4: When setting it to 4 MHz by trimming. *5: When using the crystal oscillator of 4 MHz (Including the current consumption of the oscillation circuit) *6: When using the crystal oscillator of 32 khz (Including the current consumption of the oscillation circuit) Document Number: Rev. *D Page 71 of 131

73 Parameter Power supply current Symbol (Pin name) I CCHD I CCRD Deep Standby STOP mode Deep Standby RTC mode Conditions T A = + 25 C, When RAM is off * 3 T A = + 25 C, When RAM is on(16 KB)* 4 * 3 T A = + 25 C, When RAM is on(32 KB) * 4 * 3 T A = C, When RAM is off * 3 T A = C, When RAM is on(16 KB) * 4 * 3 T A = C, When RAM is on(32 KB) * 4 * 3 T A = + 25 C, When RAM is off * 3,* 5 T A = + 25 C, When RAM is on(16 KB) * 4 * 3,* 5 T A = + 25 C, When RAM is on(32 KB) * 4 * 3,* 5 T A = C, When RAM is off * 3,* 5 T A = C, When RAM is on(16 KB) * 4 * 3,* 5 T A = C, When RAM is on(32 KB) * 4 * 3,* 5 Value Typ* 1 Max* 2 Unit μa μa μa 300 μa μa 330 μa μa μa μa 305 μa μa 335 μa Remarks *1: VCC = 3.3 V *2: VCC = 5.5 V *3: When all ports are fixed and LVD off. *4: For more information about RAM retention area, see "Memory Map (2)" in "10. Memory Map". *5: When using the crystal oscillator of 32 khz (Including the current consumption of the oscillation circuit) Document Number: Rev. *D Page 72 of 131

74 Low-Voltage Detection Current Parameter Symbol (Pin name) Conditions (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40 C to C) Value Unit Remarks Min Typ Max Low-voltage detection circuit (LVD) power supply current I CCLVD (VCC) At operation μa μa For occurrence of reset For occurrence of interrupt Flash Memory Current (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40 C to C) Parameter Flash memory write/erase current Symbol I CCFLASH (VCC) Pin name VCC Conditions At ROM0 Write/rase At ROM1 Write/rase - - Value Min Typ Max Unit ma * ma *1 Remarks *1: When programming or erase in flash memory, Flash Memory Write/rase current (ICCFLASH) is added to the Power supply current (ICC). In addition, When programming or erase in flash memory ROM0 and ROM1 at the same time, Flash Memory Write/rase current (ICCFLASH) of both ROM0 and ROM1 are added to the Power supply current (ICC). A/D Converter Current Parameter Symbol Pin name (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40 C to C) Value Conditions Unit Remarks Min Typ Max At 1unit operation ma Power supply current I CCAD (VCC) AVCC At stop μa Reference power supply current (AVRH) I CCAVRH (VCC) AVRH At 1unit operation AVRH=5.5 V ma At stop μa Document Number: Rev. *D Page 73 of 131

75 D/A Converter Current Parameter Power supply current* 1 Symbol I DDA* 2 (VCC) I DSA (VCC) Pin name AVCC Conditions At 1unit operation AV CC=3.3 V At 1unit operation AV CC=5.0 V (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40 C to C) Value Min Typ Max μa μa At stop μa Unit Remarks *1: No-load *2: Generates the max current by the COD about 0x200 Document Number: Rev. *D Page 74 of 131

76 Pin Characteristics Parameter Symbol Pin name Conditions "H" level input voltage (hysteresis input) "L" level input voltage (hysteresis input) "H" level output voltage "L" level output voltage leak current Pull-up resistance value capacitance V IHS V ILS V OH V OL I IL R PU C IN CMOS hysteresis input pin, MD0, MD1 5V tolerant input pin CMOS hysteresis input pin, MD0, MD1 5V tolerant input pin 4mA type 12mA type P80, P81 4mA type (VCC = USBVCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40 C to C) Value Min Typ Max - V CC V CC V - V CC V SS V - V SS V CC 0.2 V - V SS V CC 0.2 V V CC 4.5 V, I OH = - 4 ma V CC < 4.5 V, I OH = - 2 ma V CC 4.5 V, I OH = - 12 ma V CC < 4.5 V, I OH = - 8 ma USBV CC 4.5 V, I OH = ma USBV CC < 4.5 V, I OH = ma V CC 4.5 V, I OL = 4 ma V CC < 4.5 V, I OL = 2 ma V CC V CC V V CC V CC V USBV CC USBV CC V V SS V 12mA type V CC 4.5 V, I OL = 12 ma V CC < 4.5 V, V SS V I OL = 8 ma P80, P81 USBV CC 4.5 V, I OL = 16.5 ma USBVCC < 4.5 V, V SS V I OL = 10.5 ma μa CC0_0, V CC = USBV CC = AV CC = CC0_1, AVRH = V CC1_0, SS = AV SS = AVRL = 0.0 V CC1_ μa Pull-up pin Other than VCC, USBVCC, VSS, AVCC, AVSS, AVRH, AVRL V CC 4.5 V V CC < 4.5 V pf Unit kω Remarks Document Number: Rev. *D Page 75 of 131

77 12.4 AC Characteristics Main Clock Characteristics Parameter Symbol Pin name Conditions Min Value (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40 C to C) Max Unit Remarks V CC 4.5 V 4 48 When crystal oscillator is MHz frequency F CH V CC < 4.5 V 4 20 connected MHz When using external clock clock cycle t CYLH X0, ns When using external clock X1 PWH/tCYLH, clock pulse width % When using external clock PWL/tCYLH clock rising time and falling time operating clock* 1 frequency operating clock* 1 cycle time t CF, t CR ns When using external clock F CM MHz Master clock F CC MHz Base clock (HCLK/FCLK) F CP MHz APB0 bus clock* 2 F CP MHz APB1 bus clock* 2 F CP MHz APB2 bus clock* 2 t CYCC ns Base clock (HCLK/FCLK) t CYCP ns APB0 bus clock* 2 t CYCP ns APB1 bus clock* 2 t CYCP ns APB2 bus clock* 2 *1: For more information about each internal operating clock, see Chapter 2-1: Clock in FM3 Family Peripheral Manual. *2: For about each APB bus which each peripheral is connected to, see 8. Block Diagram in this datasheet. X0 Document Number: Rev. *D Page 76 of 131

78 Sub Clock Characteristics Parameter Symbol Pin name Conditions (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40 C to C) Value Min Typ Max khz frequency 1/ t CYLL clock cycle t CYLL X0A, X1A khz μs clock pulse width - PWH/tCYLL, PWL/tCYLL % *: For more information about crystal oscillator, see "Sub crystal oscillator" in "7. Handling Devices". Unit Remarks When crystal oscillator is connected* When using external clock When using external clock When using external clock X0A Document Number: Rev. *D Page 77 of 131

79 Built-in CR Oscillation Characteristics Built-in High-speed CR Parameter Symbol Conditions Clock frequency F CRH T A = + 25 C, 3.6 V < V CC 5.5 V T A = 0 C to + 85 C, 3.6 V < V CC 5.5 V T A = -40 C to C, 3.6 V < V CC 5.5 V T A = + 25 C, 2.7 V V CC 3.6 V T A = - 20 C to + 85 C, 2.7 V V CC 3.6 V T A = - 20 C to C, 2.7 V V CC 3.6 V T A = -40 C to C, 2.7 V V CC 3.6 V (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40 C to C) Value Min Typ Max Unit Remarks When trimming* MHz T A = - 40 C to C When not trimming Frequency stability time t CRWT μs * 2 *1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency/temperature trimming. *2: Frequency stable time is time to stable of the frequency of the High-speed CR. clock after the trim value is set. After setting the trim value, the period when the frequency stability time passes can use the High-speed CR clock as a source clock. Built-in Low-speed CR Parameter Symbol Conditions (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40 C to C) Value Unit Remarks Min Typ Max Clock frequency F CRL khz Document Number: Rev. *D Page 78 of 131

80 Operating Conditions of Main and USB PLL (In the case of using main clock for input of PLL) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40 C to C) Parameter Symbol Value Min Typ Max Unit Remarks PLL oscillation stabilization wait time* 1 (LOCK UP time) t LOCK μs PLL input clock frequency F PLLI 4-16 MHz PLL multiplication rate multiplier PLL macro oscillation clock frequency F PLLO MHz Main PLL clock frequency* 2 F CLKPLL MHz USB clock frequency* 3 F CLKSPLL MHz After the M frequency division *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see "Chapter 2-1: Clock" in "FM3 Family Peripheral Manual". *3: For more information about USB clock, see "Chapter 2-2: USB Clock Generation" in "FM3 Family Peripheral Manual Communication Macro Part" Operating Conditions of Main PLL (In the case of using built-in high-speed CR for input clock of Main PLL) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40 C to C) Parameter Symbol Value Min Typ Max Unit Remarks PLL oscillation stabilization wait time* 1 (LOCK UP time) t LOCK μs PLL input clock frequency F PLLI MHz PLL multiplication rate multiplier PLL macro oscillation clock frequency F PLLO MHz Main PLL clock frequency* 2 F CLKPLL MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see "Chapter 2-1: Clock" in "FM3 Family Peripheral Manual". Note: Make sure to input to the main PLL source clock, the high-speed CR clock (CLKHC) that the frequency/temperature has been trimmed. Document Number: Rev. *D Page 79 of 131

81 Main PLL connection Main clock (CLKMO) High-speed CR clock (CLKHC) K divider PLL input clock Main PLL PLL macro oscillation clock M divider Main PLL clock (CLKPLL) N divider USB PLL connection Main clock (CLKMO) K divider PLL input clock USB PLL PLL macro oscillation clock M divider USB clock N divider Document Number: Rev. *D Page 80 of 131

82 Reset Characteristics (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40 C to C) Parameter Symbol Pin name Conditions Min Value Max Unit Remarks Reset input time t INITX INITX ns Power-on Reset Timing (VSS = 0V, TA = - 40 C to C) Parameter Symbol Pin name Conditions Value Min Typ Max Unit Remarks Power supply shut down time t OFF ms *1 Power ramp rate dv/dt VCC V CC: 0.2 V to 2.70 V mv/ /µs *2 Time until releasing power-on reset t PRT ms *1: Vcc must be held below 0.2 V for minimum period of toff. Improper initialization may occur if this condition is not met. *2: This dv/dt characteristic is applied at the power-on of cold start (toff > 1ms). Note: If toff cannot be satisfied designs must assert external reset (INTX) at power-up and at any brownout event per V V CC V DH 0.2V dv/dt 0.2V 0.2V tprt toff RST CPU Operation RST Active release start Glossary VDH : detection voltage of Low Voltage detection reset. See Low-Voltage Detection Characteristics Document Number: Rev. *D Page 81 of 131

83 xternal Bus Timing xternal bus clock output characteristics (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40 C to C) Value Parameter Symbol Pin name Conditions Unit Min Max V CC 4.5 V - 50 MHz Output frequency t CYCL MCLKOUT* V CC < 4.5 V - 32 MHz *: The external bus clock (MCLKOUT) is a divided clock of HCLK. For more information about setting of clock divider, see "Chapter 12: xternal Bus Interface" in "FM3 Family Peripheral Manual". When external bus clock is not output, this characteristic does not give any effect on external bus operation. MCLKOUT xternal bus signal input/output characteristics (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40 C to C) Parameter Symbol Conditions Value Unit Remarks Signal input characteristics Signal output characteristics V IH 0.8 V CC V V IL 0.2 V CC V - V OH 0.8 V CC V V OL 0.2 V CC V signal VIH VIL VIH VIL Output signal VOH VOL VOH VOL Document Number: Rev. *D Page 82 of 131

84 Separate Bus Access Asynchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40 C to C) Parameter Symbol Pin name Conditions Value Min Max Unit MOX V CC 4.5 V t Min pulse width OW MOX V CC < 4.5 V MCLK n-3 - ns MCSX Address output MCSX[7:0], V CC 4.5 V t CSL AV delay time MAD[24:0] V CC < 4.5 V ns MOX MOX, V CC 4.5 V MCLK m+9 t OH - AX 0 Address hold time MAD[24:0] V CC < 4.5 V MCLK m+12 ns MCSX V CC 4.5 V MCLK m-9 MCLK m+9 t CSL - OL MOX delay time MOX, V CC < 4.5 V MCLK m-12 MCLK m+12 ns MOX MCSX[7:0] V CC 4.5 V MCLK m+9 t MCSX time OH - CSH 0 V CC < 4.5 V MCLK m+12 ns MCSX MCSX, V CC 4.5 V MCLK m-9 MCLK m+9 t CSL - RDQML MDQM delay time MDQM[1:0] V CC < 4.5 V MCLK m-12 MCLK m+12 ns Data set up MOX, V CC 4.5 V 20 - t DS - O MOX time MADATA[15:0] V CC < 4.5 V 38 - ns MOX MOX, V CC 4.5 V t DH - O Data hold time MADATA[15:0] V CC < 4.5 V 0 - ns MWX V CC 4.5 V t WW MWX Min pulse width V CC < 4.5 V MCLK n-3 - ns MWX Address output MWX, V CC 4.5 V MCLK m+9 t WH - AX 0 delay time MAD[24:0] V CC < 4.5 V MCLK m+12 ns MCSX V CC 4.5 V MCLK n-9 MCLK n+9 t CSL - WL MWX delay time MWX, V CC < 4.5 V MCLK n-12 MCLK n+12 ns MWX MCSX[7:0] V CC 4.5 V MCLK m+9 t MCSX delay time WH - CSH 0 V CC < 4.5 V MCLK m+12 ns MCSX MCSX, V CC 4.5 V MCLK n-9 MCLK n+9 t CSL-WDQML MDQM delay time MDQM[1:0] V CC < 4.5 V MCLK n-12 MCLK n+12 ns MCSX MCSX, V CC 4.5 V MCLK-9 MCLK+9 t CSL-DV Data output time MADATA[15:0] V CC < 4.5 V MCLK-12 MCLK+12 ns MWX MWX, V CC 4.5 V t WH - DX Data hold time MADATA[15:0] V CC < 4.5 V 0 MCLK m+12 ns Note: When the external load capacitance CL = 30 pf (m = 0 to 15, n = 1 to 16). Document Number: Rev. *D Page 83 of 131

85 t CYCL MCLK t OH-CSH t WH-CSH MCSX[7:0] MAD[24:0] t CSL-AV t OH-AX Address t CSL-AV Address t WH-AX t CSL-OL MOX tcsl-rdqml t OW t CSL-WDQML MDQM[1:0] t CSL-WL t WW MWX MADATA[15:0] t DS-O RD t DH-O Invalid WD t WH-DX t CSL-DV Document Number: Rev. *D Page 84 of 131

86 Separate Bus Access Synchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40 C to C) Parameter Symbol Pin name Conditions Value Min Max Unit Address delay time t AV MCLK, V CC 4.5 V MAD[24:0] V CC < 4.5 V 1 12 ns MCSX delay time t CSL V CC 4.5 V 9 1 MCLK, V CC < 4.5 V 12 ns t CSH MCSX[7:0] V CC 4.5 V 9 1 V CC < 4.5 V 12 ns MOX delay time t RL V CC 4.5 V 9 1 MCLK, V CC < 4.5 V 12 ns t RH MOX V CC 4.5 V 9 1 V CC < 4.5 V 12 ns Data set up MCLK, V CC 4.5 V 19 t MCLK time DS MADATA[15:0] V CC < 4.5 V 37 - ns MCLK MCLK, V CC 4.5 V t Data hold time DH MADATA[15:0] V CC < 4.5 V 0 - ns MWX delay time t WL V CC 4.5 V 9 1 MCLK, V CC < 4.5 V 12 ns t WH MWX V CC 4.5 V 9 1 V CC < 4.5 V 12 ns V CC 4.5 V 9 t DQML 1 MDQM[1:0] MCLK, V CC < 4.5 V 12 ns delay time MDQM[1:0] V CC 4.5 V 9 t DQMH 1 V CC < 4.5 V 12 ns MCLK MCLK, V CC 4.5 V MCLK+18 t Data output time ODS MCLK+1 MADATA[15:0] V CC < 4.5 V MCLK+24 ns MCLK MCLK, V CC 4.5 V 18 T Data hold time OD 1 MADATA[15:0] V CC < 4.5 V 24 ns Note: When the external load capacitance CL = 30 pf. t CYCL MCLK MCSX[7:0] t CSL t CSH MAD[24:0] t AV Address t AV Address t RL t RH MOX t DQML t DQMH t DQML t DQMH MDQM[1:0] t WL t WH MWX MADATA[15:0] t DS RD t DH Invalid WD t OD t ODS Document Number: Rev. *D Page 85 of 131

87 Multiplexed Bus Access Asynchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40 C to C) Value Parameter Symbol Pin name Conditions Min Max Multiplexed V CC 4.5 V +10 t address delay time AL-CHMADV 0 MAL, V CC < 4.5 V +20 Multiplexed MADATA[15:0] V CC 4.5 V MCLK n+0 MCLK n+12 t address hold time CHMADH V CC < 4.5 V MCLK n+0 MCLK n+20 Unit ns ns Note: When the external load capacitance CL = 30 pf (m = 0 to 15, n = 1 to 16). MCLK MCSX[7:0] MAL MAD [24:0] MOX MDQM [1:0] MWX MADATA[15:0] Document Number: Rev. *D Page 86 of 131

88 Multiplexed Bus Access Synchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40 C to C) Value Parameter Symbol Pin name Conditions Unit Min Max V CC 4.5 V 9 ns t CHAL 1 MCLK, V CC < 4.5 V 12 ns MAL delay time AL V CC 4.5 V 9 ns t CHAH 1 V CC < 4.5 V 12 ns MCLK Multiplexed Address delay time MCLK Multiplexed Data output time t CHMADV t CHMADX MCLK, MADATA[15:0] V CC 4.5 V V CC < 4.5 V V CC 4.5 V V CC < 4.5 V 1 t OD ns 1 t OD ns Remarks Note: When the external load capacitance CL = 30 pf. MCLK MCSX[7:0] MAL MAD [24:0] MOX MDQM [1:0] MWX MADATA[15:0] Document Number: Rev. *D Page 87 of 131

89 NAND Flash Memory Mode MNRX Min pulse width Data setup MNRX time MNRX Data hold time (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40 C to C) Parameter Symbol Pin name Conditions Value Min Max Unit t NRW MNRX V CC 4.5 V V CC < 4.5 V MCLK n-3 - ns t DS NR MNRX, V CC 4.5 V 20 - MADATA[15:0] V CC < 4.5 V 38 - ns t DH NR MNRX, MADATA[15:0] V CC 4.5 V V CC < 4.5 V 0 - ns t ALH - NWL MNAL, V CC 4.5 V MCLK m-9 MCLK m+9 MNWX V CC < 4.5 V MCLK m-12 MCLK m+12 ns t ALL - NWL MNAL, V CC 4.5 V MCLK m-9 MCLK m+9 MNWX V CC < 4.5 V MCLK m-12 MCLK m+12 ns t CLH - NWL MNCL, V CC 4.5 V MCLK m-9 MCLK m+9 MNWX V CC < 4.5 V MCLK m-12 MCLK m+12 ns t NWH - CLL MNCL, V CC 4.5 V MCLK m+9 0 MNWX V CC < 4.5 V MCLK m+12 ns t NWW MNWX V CC 4.5 V V CC < 4.5 V MCLK n-3 - ns t NWL DV MNWX, V CC 4.5 V MADATA[15:0] V CC < 4.5 V ns t NWH DX MNWX, V CC 4.5 V MCLK m+11 0 MADATA[15:0] V CC < 4.5 V MCLK m+12 ns MNAL MNWX delay time MNAL MNWX delay time MNCL MNWX delay time MNWX MNCL delay time MNWX Min pulse width MNWX Data output time MNWX Data hold time Note: When the external load capacitance CL = 30 pf (m=0 to 15, n=1 to 16). NAND Flash Memory Read MCLK MNRX MADATA[15:0] Read Document Number: Rev. *D Page 88 of 131

90 NAND Flash Memory Address Write MCLK MNAL MNCL MNWX MADATA[15:0] Write NAND Flash Memory Command Write MCLK MNAL MNCL MNWX MADATA[15:0] Write Document Number: Rev. *D Page 89 of 131

91 xternal Ready Timing MCLK MRDY input setup time Parameter Symbol Pin name Conditions t RDYI MCLK, MRDY V CC 4.5 V 19 V CC < 4.5 V 37 (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40 C to C) Min Value Max - ns Unit Remarks When RDY is input MCLK Original MOX MWX Over 2cycles t RDYI MRDY When RDY is released MCLK 2 cycles xtended MOX MWX t RDYI MRDY 0.5 VCC Document Number: Rev. *D Page 90 of 131

92 Base Timer Timing Timer input timing Parameter Symbol Pin name Conditions pulse width t TIWH, t TIWL TIOAn/TIOBn (when using as CK, TIN) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40 C to C) Min Value Max - 2t CYCP - ns Unit Remarks CK t TIWH t TIWL TIN V IHS V IHS V ILS V ILS Trigger input timing pulse width Parameter Symbol Pin name Conditions t TRGH, t TRGL TIOAn/TIOBn (when using as TGIN) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40 C to C) Min Value Max - 2t CYCP - ns Unit Remarks t TRGH t TRGL TGIN V IHS V IHS V ILS V ILS Note: tcycp indicates the APB bus clock cycle time. About the APB bus number which the Base Timer is connected to, see 8. Block Diagram in this datasheet. Document Number: Rev. *D Page 91 of 131

93 CSIO/UART Timing CSIO (SPI = 0, SCINV = 0) Parameter Symbol Pin name Conditions (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40 C to C) VCC < 4.5 V VCC 4.5 V Min Max Min Max Baud Rate Mbps Serial clock cycle time t SCYC SCKx 4t CYCP - 4t CYCP - ns SCK SOT delay time t SLOVI SCKx, SOTx ns SIN SCK setup time t IVSHI SCKx, Master mode SINx ns SCK SIN hold time t SHIXI SCKx, SINx ns Serial clock "L" pulse width t SLSH SCKx 2t CYCP t CYCP ns Serial clock "H" pulse width t SHSL SCKx t CYCP t CYCP ns SCK SOT delay time t SLOV SCKx, SOTx ns SIN SCK setup time t IVSH SCKx, SINx Slave mode ns SCK SIN hold time t SHIX SCKx, SINx ns SCK falling time tf SCKx ns SCK rising time tr SCKx ns Unit Notes: The above characteristics apply to CLK synchronous mode. tcycp indicates the APB bus clock cycle time. About the APB bus number which Multi-function Serial is connected to, see "8. Block Diagram" in this datasheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. When the external load capacitance CL = 30pF. Document Number: Rev. *D Page 92 of 131

94 tscyc VOH SCK VOL VOL t SLOVI SOT VOH VOL SIN VIH VIL tivshi tshixi VIH VIL Master mode tslsh tshsl SCK VIH tf VIL t SLOV VIL VIH tr VIH SOT VOH VOL SIN tivsh VIH VIL tshix VIH VIL Slave mode Document Number: Rev. *D Page 93 of 131

95 CSIO (SPI = 0, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40 C to C) Parameter Symbol Pin VCC < 4.5 V VCC 4.5 V Conditions name Min Max Min Max Unit Baud Rate Mbps Serial clock cycle time t SCYC SCKx 4t CYCP - 4t CYCP - ns SCK SOT delay time t SHOVI SCKx, SOTx ns SIN SCK setup time t IVSLI SCKx, Master mode SINx ns SCK SIN hold time t SLIXI SCKx, SINx ns Serial clock "L" pulse width t SLSH SCKx 2t CYCP t CYCP ns Serial clock "H" pulse width t SHSL SCKx t CYCP t CYCP ns SCK SOT delay time t SHOV SCKx, SOTx ns SIN SCK setup time t IVSL SCKx, SINx Slave mode ns SCK SIN hold time t SLIX SCKx, SINx ns SCK falling time tf SCKx ns SCK rising time tr SCKx ns Notes: The above characteristics apply to CLK synchronous mode. tcycp indicates the APB bus clock cycle time. About the APB bus number which Multi-function serial is connected to, see 8. Block Diagram in this datasheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. When the external load capacitance CL = 30 pf. Document Number: Rev. *D Page 94 of 131

96 tscyc SCK VOH VOH VOL SOT t SHOVI VOH VOL SIN VIH VIL tivsli tslixi VIH VIL Master mode tshsl tslsh SCK tr VIL VIH t SHOV tf VIH VIL VIL SOT VOH VOL tivsl tslix SIN VIH VIH VIL VIL Slave mode Document Number: Rev. *D Page 95 of 131

97 CSIO (SPI = 1, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40 C to C) Parameter Symbol Pin VCC < 4.5 V VCC 4.5 V Conditions name Min Max Min Max Unit Baud Rate Mbps Serial clock cycle time t SCYC SCKx 4t CYCP - 4t CYCP - ns SCK SOT delay time t SHOVI SCKx, SOTx ns SIN SCK setup time t IVSLI SCKx, SINx Master mode ns SCK SIN hold time t SLIXI SCKx, SINx ns SOT SCK delay time t SOVLI SCKx, SOTx 2t CYCP t CYCP ns Serial clock "L" pulse width t SLSH SCKx 2t CYCP t CYCP ns Serial clock "H" pulse width t SHSL SCKx t CYCP t CYCP ns SCK SOT delay time t SHOV SCKx, SOTx ns SIN SCK setup time t IVSL SCKx, SINx Slave mode ns SCK SIN hold time t SLIX SCKx, SINx ns SCK falling time tf SCKx ns SCK rising time tr SCKx ns Notes: The above characteristics apply to CLK synchronous mode. tcycp indicates the APB bus clock cycle time. About the APB bus number which Multi-function serial is connected to, see 8. Block Diagram in this datasheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. When the external load capacitance CL = 30 pf. Document Number: Rev. *D Page 96 of 131

98 tscyc VOH SCK tsovli VOL tshovi VOL VOH VOH SOT VOL VOL tivsli tslixi SIN VIH VIL VIH VIL Master mode tslsh tshsl SCK VIH VIH VIH VIL VIL SOT * VOH VOL tf tr tshov VOH VOL tivsl tslix SIN VIH VIL VIH VIL *: Changes when writing to TDR register Slave mode Document Number: Rev. *D Page 97 of 131

99 CSIO (SPI = 1, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40 C to C) Parameter Symbol Pin VCC < 4.5 V VCC 4.5 V Conditions name Min Max Min Max Unit Baud Rate Mbps Serial clock cycle time t SCYC SCKx 4t CYCP - 4t CYCP - ns SCK SOT delay time t SLOVI SCKx, SOTx ns SIN SCK setup time t IVSHI SCKx, SINx Master mode ns SCK SIN hold time t SHIXI SCKx, SINx ns SOT SCK delay time t SOVHI SCKx, SOTx 2t CYCP t CYCP ns Serial clock "L" pulse width t SLSH SCKx 2t CYCP t CYCP ns Serial clock "H" pulse width t SHSL SCKx t CYCP t CYCP ns SCK SOT delay time t SLOV SCKx, SOTx ns SIN SCK setup time t IVSH SCKx, SINx Slave mode ns SCK SIN hold time t SHIX SCKx, SINx ns SCK falling time tf SCKx ns SCK rising time tr SCKx ns Notes: The above characteristics apply to CLK synchronous mode. tcycp indicates the APB bus clock cycle time. About the APB bus number which Multi-function serial is connected to, see 8. Block Diagram in this datasheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. When the external load capacitance CL = 30 pf. Document Number: Rev. *D Page 98 of 131

100 tscyc SCK VOH VOL VOH tsovhi tslovi SOT VOH VOL VOH VOL tivshi tshixi SIN VIH VIL VIH VIL Master mode tr t SHSL t SLSH SCK SOT SIN V OH V OL V IH V IL t IVSH V IL V IH t SHIX V IH tf V IL V IH V IL t SLOV V OH V OL V IL V IH Slave mode UART external clock input (XT = 1) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40 C to C) Value Parameter Symbol Conditions Unit Min Max Serial clock "L" pulse width t SLSH t CYCP ns Serial clock "H" pulse width t SHSL t CYCP ns C L = 30 pf SCK falling time tf - 5 ns SCK rising time tr - 5 ns Remarks SCK tr t SHSL V IH V IH V IH V I L V IL V I L tf t SLSH Document Number: Rev. *D Page 99 of 131

101 xternal Timing Parameter Symbol Pin name Conditions (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40 C to C) Value Unit Remarks Min Max pulse width t INH, t INL ADTG A/D converter trigger input FRCKx - 2t CYCP* 1 - ns Free-run timer input clock ICxx capture DTTIxX - 2t CYCP* 1 - ns Waveform generator INTxx *2 2t CYCP + 100* 1 - ns xternal interrupt, * ns NMI WKUPx * ns Deep standby wake up *1: tcycp indicates the APB bus clock cycle time. About the APB bus number which the A/D converter, Multi-function Timer, xternal interrupt are connected to, see 8. Block Diagram in this datasheet. *2: When in RUN mode, in SLP mode. *3: When in STOP mode, in TIMR mode. *4: When in Deep Standby RTC mode, in Deep Standby STOP mode. Document Number: Rev. *D Page 100 of 131

102 Quadrature Position/Revolution Counter timing Parameter Symbol Conditions AIN pin "H" width t AHL - AIN pin "L" width t ALL - BIN pin "H" width t BHL - BIN pin "L" width t BLL - Time from AIN pin "H" level to BIN rise t AUBU PC_Mode2 or PC_Mode3 Time from BIN pin "H" level to AIN fall t BUAD PC_Mode2 or PC_Mode3 Time from AIN pin "L" level to BIN fall t ADBD PC_Mode2 or PC_Mode3 Time from BIN pin "L" level to AIN rise t BDAU PC_Mode2 or PC_Mode3 Time from BIN pin "H" level to AIN rise t BUAU PC_Mode2 or PC_Mode3 Time from AIN pin "H" level to BIN fall t AUBD PC_Mode2 or PC_Mode3 Time from BIN pin "L" level to AIN fall t BDAD PC_Mode2 or PC_Mode3 Time from AIN pin "L" level to BIN rise t ADBU PC_Mode2 or PC_Mode3 ZIN pin "H" width t ZHL QCR:CGSC="0" ZIN pin "L" width t ZLL QCR:CGSC="0" Time from determined ZIN level to AIN/BIN rise and fall t ZAB QCR:CGSC="1" Time from AIN/BIN rise and fall time to determined ZIN level t ABZ QCR:CGSC="1" (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40 C to C) Value Min Max Unit 2t CYCP* - ns *: tcycp indicates the APB bus clock cycle time. About the APB bus number which the Quadrature Position/Revolution Counter is connected to, see 8. Block Diagram in this datasheet. tahl tall AIN taubu tbuad tadbd tbdau BIN tbhl tbll Document Number: Rev. *D Page 101 of 131

103 tbhl tbll BIN tbuau taubd tbdad tadbu AIN tahl tall ZIN ZIN AIN/BIN Document Number: Rev. *D Page 102 of 131

104 I 2 C Timing (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40 C to C) Parameter Symbol Conditions Standard-mode Fast-mode V Max Min Max Unit SCL clock frequency F SCL khz (Repeated) START condition hold time t HDSTA μs SDA SCL SCLclock "L" width t LOW μs SCLclock "H" width t HIGH μs (Repeated) START condition setup time SCL SDA Data hold time SCL SDA Data setup time SDA SCL STOP condition setup time SCL SDA Bus free time between "STOP condition" and "START condition" t SUSTA μs t HDDAT C L = 30 pf, R = (Vp/I OL)* * * 3 μs t SUDAT ns t SUSTO μs t BUF μs Noise filter t SP - 2 t CYCP* 4-2 t CYCP* 4 - ns *1: R and CL represent the pull-up resistor and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up resistor and IOL indicates VOL guaranteed current. *2: The maximum thddat must satisfy that it does not extend at least "L" period (tlow) of device's SCL signal. *3: Fast-mode I 2 C bus device can be used on Standard-mode I 2 C bus system as long as the device satisfies the requirement of "tsudat 250 ns". *4: tcycp is the APB bus clock cycle time. About the APB bus number that I 2 C is connected to, see "8. Block Diagram" in this datasheet. To use Standard-mode, set the APB bus clock at 2 MHz or more. To use Fast-mode, set the APB bus clock at 8 MHz or more. Remarks SDA SCL Document Number: Rev. *D Page 103 of 131

105 TM Timing Data hold Parameter Symbol Pin name Conditions t TMH TRACCLK, TRACD[3:0] (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40 C to C) Value Min Max V CC 4.5 V 2 10 V CC < 4.5 V 2 15 Unit ns Remarks TRACCLK frequency TRACCLK clock cycle 1/ t TRAC t TRAC TRACCLK V CC 4.5 V - 40 MHz V CC < 4.5 V - 20 MHz V CC 4.5 V 25 - ns V CC < 4.5 V 50 - ns Note: When the external load capacitance CL = 30 pf. HCLK TRACCLK TRACD[3:0] Document Number: Rev. *D Page 104 of 131

106 JTAG Timing Parameter Symbol Pin name Conditions TMS, TDI setup time TMS, TDI hold time TDO delay time t JTAGS t JTAGH t JTAGD TCK, TMS, TDI TCK, TMS, TDI TCK, TDO V CC 4.5 V V CC < 4.5 V V CC 4.5 V V CC < 4.5 V (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40 C to C) Value Min Max 15 - ns 15 - ns V CC 4.5 V - 25 V CC < 4.5 V - 45 Unit ns Remarks Note: When the external load capacitance CL = 30 pf. TCK TMS/TDI TDO Document Number: Rev. *D Page 105 of 131

107 bit A/D Converter lectrical characteristics for the A/D converter (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40 C to C) Parameter Symbol Pin Value name Min Typ Max Unit Resolution bit Integral Nonlinearity ± 1.5 ± 4.5 LSB Differential Nonlinearity ± 2.2 ± 2.5 LSB Zero transition voltage V ZT ANxx - ± 6 ± 15 mv Full-scale transition voltage V FST ANxx - AVRH ± 5 AVRH ± 15 mv Conversion time * μs Sampling time* 2 Ts μs Compare clock cycle* 3 Tcck ns State transition time to operation permission Tstt μs Analog input capacity C AIN pf Remarks AVRH = 2.7 V to 5.5 V 1.62 AV CC 4.5 V Analog input resistor R AIN kω 2.35 AV CC < 4.5 V Interchannel disparity LSB Analog port input leak current - ANxx μa Analog input voltage - ANxx AVRL - AVRH V Reference voltage - AVRH AV CC V - AVRL AV SS - AV SS V *1: The conversion time is the value of sampling time (Ts) + compare time (Tc). The condition of the minimum conversion time is when the value of sampling time: 300ns, the value of compare time: 700 ns (AVCC 4.5 V). nsure that it satisfies the value of the sampling time (Ts) and compare clock cycle (Tcck). For setting of the sampling time and compare clock cycle, see "Chapter 1-1: A/D Converter" in "FM3 Family Peripheral Manual Analog Macro Part". The register setting of the A/D Converter are reflected in the operation according to the APB bus clock timing. The sampling clock and compare clock is generated from the Base clock (HCLK). About the APB bus number which the A/D Converter is connected to, see "8. Block Diagram" in this datasheet. *2: A necessary sampling time changes by external impedance. nsure that it sets the sampling time to satisfy (quation 1). *3: The compare time (Tc) is the value of (quation 2). Document Number: Rev. *D Page 106 of 131

108 Analog signal source Rext ANxx Analog input pin RAIN Comparator CAIN (quation 1) TS ( RAIN + Rext ) CAIN 9 Ts: Sampling time RAIN: resistor of A/D = 1.62 kω ch.0 to ch.7 at 4.5 V < AVCC < 5.5 V resistor of A/D = 1.58 kω ch.8 to ch.15 at 4.5 V < AVCC < 5.5 V resistor of A/D = 1.56 kω ch.16 to ch.23 at 4.5 V < AVCC < 5.5 V resistor of A/D = 2.35 kω ch.0 to ch.7 at 2.7 V < AVCC < 4.5 V resistor of A/D = 2.3 kω ch.8 to ch.15 at 2.7 V < AVCC < 4.5 V resistor of A/D = 2.25 kω ch.16 to ch.23 at 2.7 V < AVCC < 4.5 V CAIN: capacity of A/D = 9.5 pf at 2.7 V < AVCC < 5.5 V Rext: Output impedance of external circuit (quation 2) Tc = Tcck 14 Tc: Compare time Tcck: Compare clock cycle Document Number: Rev. *D Page 107 of 131

109 Digital output Digital output Definition of 12-bit A/D Converter Terms Resolution: Integral Nonlinearity: Analog variation that is recognized by an A/D converter. Deviation of the line between the zero-transition point (0b b ) and the full-scale transition point (0b b ) from the actual conversion characteristics. Differential Nonlinearity: Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB. 0xFFF 0xFF 0xFFD 0x004 0x003 0x002 0x001 Integral Nonlinearity Actual conversion characteristics {1 LSB(N-1) + VZT} (Actuallymeasured value) Actual conversion characteristics Ideal characteristics VZT VNT VFST (Actually-measured value) (Actually-measured value) 0x(N+1) 0xN 0x(N-1) 0x(N-2) Differential Nonlinearity Actual conversion characteristics Ideal characteristics VNT V(N+1)T (Actually-measured value) (Actually-measured value) Actual conversion characteristics AVRL AVRH AVRL AVRH Analog input Analog input Integral Nonlinearity of digital output N = VNT - {1LSB (N - 1) + VZT} 1LSB [LSB] Differential Nonlinearity of digital output N = V(N + 1) T - VNT 1LSB - 1 [LSB] 1LSB = VFST VZT 4094 N: A/D converter digital output value. VZT: Voltage at which the digital output changes from 0x000 to 0x001. VFST: Voltage at which the digital output changes from 0xFF to 0xFFF. VNT: Voltage at which the digital output changes from 0x(N 1) to 0xN. Document Number: Rev. *D Page 108 of 131

110 bit D/A Converter lectrical Characteristics for the D/A Converter (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40 C to C) Value Parameter Symbol Pin name Unit Remarks Min Typ Max Resolution bit tc μs Load 20 pf Conversion time tc μs Load 100 pf Integral Nonlinearity* 1 INL LSB Differential Nonlinearity* 1, * 2 DNL LSB DAx mv Code is 0x000 Output Voltage offset V OFF mv Code is 0x3FF kω D/A operation Analog output impedance R O MΩ D/A stop Output undefined period t R ns *1: No-load *2: Generates the max current by the COD about 0x200 Document Number: Rev. *D Page 109 of 131

111 Minimum differential input sensitivity [V] 12.7 USB Characteristics characteristics Output characteristics Parameter "H" level voltage Symbol V IH (VCC = 2.7V to 5.5V, USBVCC = 3.0V to 3.6V, VSS = 0V, TA = - 40 C to C) Pin name UDP0, UDM0 Conditions Min Value Max Unit USBV CC V *1 "L" level voltage V IL - V SS V *1 Differential input sensitivity V DI V *2 Different common mode range V CM V *2 Output "H" level voltage Output "L" level voltage V OH V OL xternal pull-down resistor = 15 kω xternal pull-up resistor = 1.5 kω V * V *3 Crossover voltage V CRS V *4 Rising time t FR Full-Speed 4 20 ns *5 Falling time t FF Full-Speed 4 20 ns *5 Rising/falling time matching t FRFM Full-Speed % *5 Output impedance Z DRV Full-Speed Ω *6 Rising time t LR Low-Speed ns *7 Falling time t LF Low-Speed ns *7 Rising/falling time matching t LRFM Low-Speed % *7 *1: The switching threshold voltage of the Single-nd-Receiver of USB I/O buffer is set as within VIL (Max) = 0.8 V, VIH (Min) = 2.0 V (TTL input standard). There are some hysteresis to lower noise sensitivity. *2: Use the differential-receiver to receive the USB differential data signal. The Differential-Receiver has 200 mv of differential input sensitivity when the differential data input is within 0.8 V to 2.5 V to the local ground reference level. The voltage range above is said to be the common mode input voltage range. Remarks Common mode input voltage [V] Document Number: Rev. *D Page 110 of 131

112 *3: The output drive capability of the driver is below 0.3 V at Low-State (VOL) (to 3.6 V and 1.5 kω load), and 2.8 V or above (to ground and 15 kω load) at High-State (VOH). *4: The cross voltage of the external differential output signal (D + /D ) of USB I/O buffer is within 1.3 V to 2.0 V. VCRS specified range *5: They indicate rising time (Trise) and falling time (Tfall) of the full-speed differential data signal. They are defined by the time between 10% and 90% of the output signal voltage. For full-speed buffer, Tr/Tf ratio is regulated as within ± 10% to minimize RFI emission. Rising time Falling time Document Number: Rev. *D Page 111 of 131

113 *6: USB Full-speed connection is performed via twist pair cable shield with 90 Ω ± 15% characteristic impedance (Differential Mode). USB standard defines that output impedance of USB driver must be in range from 28 Ω to 44 Ω. So, discrete series resistor (Rs) addition is defined in order to satisfy the above definition and keep balance. When using this USB I/O, use it with 25 Ω to 30 Ω (recommendation value 27 Ω) Series resistor Rs. 28Ω to 44Ω quiv. Imped. 28Ω to 44Ω quiv. Imped. Mount it as external resistor. Rs series resistor 25Ω to 30Ω Series resistor of 27Ω (recommendation value) must be added. And, use "resistance with an uncertainty of 5% by 24 sequence". *7: They indicate rising time (Trise) and falling time (Tfall) of the low-speed differential data signal. They are defined by the time between 10% and 90% of the output signal voltage. Rising time Falling time See Low-Speed Load (Compliance Load) for conditions of the external load. Document Number: Rev. *D Page 112 of 131

114 Low-Speed Load (Upstream Port Load) - Reference 1 CL = 50pF to 150pF CL = 50pF to 150pF Low-Speed Load (Downstream Port Load) - Reference 2 CL = 200pF to 600pF CL = 200pF to 600pF Low-Speed Load (Compliance Load) CL = 200pF to 450pF CL = 200pF to 450pF Document Number: Rev. *D Page 113 of 131