32-bit ARM Cortex -M4F FM4 Microcontroller

Transcription

1 32-bit ARM Cortex -M4F FM4 Microcontroller Devices in the S6E2D5 Series are highly integrated 32-bit microcontrollers with high performance and competitive cost. This series is based on the ARM Cortex-M4F Processor with on-chip Flash memory and SRAM. The series has peripheral functions such as graphics engine, display controller, motor control timers, ADCs, and Communication nterfaces (USB, CAN, UART, CSO, 2 C, LN). The products that are described in this data sheet are TYPE4-M4 category products. See the FM4 Family Peripheral Manual Main Part ( ). Features 32-bit ARM Cortex-M4F Core Processor version: r0p1 Up to 160 MHz frequency operation Built-in FPU Supports DSP instructions Memory Protection Unit (MPU): improves the reliability of an embedded system ntegrated Nested Vectored nterrupt Controller (NVC): 1 NM (non-maskable interrupt) and 128 peripheral interrupts and 16 priority levels 24-bit system timer (Sys Tick): System timer for OS task management On-Chip Memories Flash memory This series has on-chip flash memory with these features: 384 Kbytes Built-in Flash Accelerator System with 16 Kbytes trace buffer memory Security function for code protection Notes: The read access to flash memory can be achieved without wait-cycle up to operation frequency of 72 MHz. Even at the operation frequency more than 72 MHz, an equivalent access to flash memory can be obtained by Flash Accelerator System. SRAM This is composed of two independent SRAMs (SRAM0 and SRAM2). SRAM0 is connected to -code bus and D-code bus of Cortex-M4F core. SRAM2 is connected to the system bus of Cortex-M4F core. SRAM0: 32 Kbytes SRAM2: 4 Kbytes VRAM This series is equipped with a SRAM for GDC. Max 512 Kbytes VFLASH S6E2D55GJA is equipped with a Flash for GDC. 2 Mbytes External Bus nterface Supports SRAM, NOR, NAND Flash and SDRAM devices Up to two chip selects CS0 and CS8 (CS8 is only for SDRAM) 8-/16-bit data width Up to 25-bit address bit Maximum area size : Up to 256 Mbytes Supports address/data multiplexing Supports external RDY function Supports the scramble function Possible to set the validity/invalidity of the scramble function for the external areas 0x6000_0000 to 0x7FFF_FFFF in 4 Mbytes units. Possible to set two kinds of the scramble key. Note: t is necessary to prepare the dedicated software library to use the scramble function. USB nterface (One channel) A USB interface is composed of device and host. USB device USB2.0 Full-Speed supported Max 6 EndPoint supported EndPoint 0 is for control transfer EndPoint 1, 2 can be selected for bulk-transfer, interrupttransfer or isochronous-transfer EndPoint 3 to 5 can select bulk-transfer or interrupttransfer EndPoint 1 to 5 comprise the double buffer The size of each endpoint is as follows. Endpoint 0, 2 to 5: 64 bytes EndPoint 1: 256 bytes USB host USB2.0 Full-Speed / Low-Speed supported Bulk-transfer, interrupt-transfer and isochronous-transfer support USB device connected/disconnected automatically detect n/out token handshake packet automatically accepted Max 256-byte packet-length supported Wake-up function supported Cypress Semiconductor Corporation 198 Champion Court San Jose, CA Document Number: Rev.*C Revised February 21, 2017

2 CAN-FD nterface (One channel) Compatible with CAN Specification 2.0A/B Maximum transfer rate: 5 Mbps Message buffer for receiver: Up to 192 messages Message buffer for transmitter: Up to 32 messages CAN with flexible data rate (non-so CAN FD) Notes: CAN FD cannot communicate between non-so CAN FD and SO CAN FD, because non-so CAN FD and SO CAN FD are different frame format. About the problem of "non-so CAN FD", see the White Paper from CiA(CAN in Automation). Multi-function Serial nterface (Max eight channels) 64 bytes with FFO (the FFO step numbers vary depending on the settings of the communication mode or bit length.) Operation mode is selectable from the following for each channel. UART CSO LN 2 C UART Full-duplex double buffer Selection with or without parity supported Built-in dedicated baud rate generator External clock available as a serial clock Various error detect functions available (parity errors, framing errors, and overrun errors) CSO Full-duplex double buffer Built-in dedicated baud rate generator Overrun error detect function available Serial chip select function (ch.6 and ch.7 only) Supports High-speed SP (ch.6 only) Data length 5 to 16-bit LN LN protocol Rev.2.1 supported Full-duplex double buffer Master/Slave mode supported LN break field generation (can change to 13 to 16-bit length) LN break delimiter generation (can change to 1 to 4-bit length) Various error detect functions available (parity errors, framing errors, and overrun errors) 2 C Standard mode (Max 100 kbps) / Fast mode (Max 400 kbps) supported Fast mode Plus (Fm+) (Max 1000 kbps, only for ch.4=ch.a) supported DMA Controller (Eight channels) The DMA controller has an independent bus for the CPU, so the CPU and the DMA controller can process simultaneously. 8 independently configured and operated channels Transfer can be started by software or requested from the built-in peripherals Transfer address area: 32-bit (4 Gbytes) Transfer mode: Block transfer/burst transfer/demand transfer Transfer data type: bytes/half-word/word Transfer block count: 1 to 16 Number of transfers: 1 to DSTC (Descriptor System Data Transfer Controller) (128 channels) The DSTC can transfer data at high-speed without going via the CPU. The DSTC adopts the descriptor system and, following the specified contents of the descriptor that has already been constructed on the memory, can directly access the memory/peripheral device and performs the data transfer operation. t supports the software activation, the hardware activation, and the chain activation functions. A/D Converter (Max 24 channels) 12-bit A/D Converter Successive Approximation type Built-in 2 units Conversion time: V Priority conversion available (priority at two levels) Scanning conversion mode Built-in FFO for conversion data storage (for SCAN conversion: 16 steps, for priority conversion: four steps) Base Timer (Max eight channels) Operation mode is selectable from the followings for each channel. 16-bit PWM timer 16-bit PPG timer 16-/32-bit reload timer 16-/32-bit PWC timer General-Purpose /O Port This series can use its pins as general-purpose /O ports when they are not used for external bus or peripherals. Moreover, the port relocate function is built in. t can set to which /O port the peripheral function can be allocated. Capable of pull-up control per pin Capable of reading pin level directly Built-in port relocate function Up to 98 general-purpose /O 120-pin package Some /O pins are 5V tolerant. See "4. Pin Descriptions" and "5. /O Circuit Type" for the corresponding pins. Document Number: Rev.*C Page 2 of 182

3 Multi-Function Timer (One unit) The multi-function timer is composed of the following blocks. Minimum resolution : 6.25 ns 16-bit free-run timer 3ch. nput capture 4ch. Output compare 6ch. A/D activation compare 6ch. Waveform generator 3ch. 16-bit PPG timer 3ch. The following functions can be used to achieve motor control. PWM signal output function DC chopper waveform output function Dead time function nput capture function A/D converter activate function DTF (motor emergency stop) interrupt function Real-Time Clock (RTC) The real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 00 to 99. nterrupt function with specifying date and time (Year/Month/Day/Hour/Minute) is available. This function is also available by specifying only Year, Month, Day, Hour or Minute. Timer interrupt function after set time or each set time. Capable of rewriting the time with continuing the time count. Leap year automatic count is available. Quadrature Position/Revolution Counter (QPRC) (One channel) The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position encoder. Moreover, it is possible to use up/down counter. The detection edge of the three external event pins AN, BN and ZN is configurable. 16-bit position counter 16-bit revolution counter Two 16-bit compare registers Dual Timer (32-/16-bit Down Counter) The dual timer consists of two programmable 32-/16-bit down counters. Operation mode is selectable from the followings for each channel. Free-running Periodic (=Reload) One-shot Watch Counter The watch counter is used for wake up from the low-power consumption mode. t is possible to select the main clock, sub clock, built-in High-speed CR clock or built-in Low-speed CR clock as the clock source. nterval timer: up to 64 s Sub Clock: khz External nterrupt Controller Unit External interrupt pin: Max 16 pins nclude one non-maskable interrupt (NM) Watchdog Timer (Two channels) A watchdog timer can generate interrupts or a reset when a time-out value is reached. This series consists of two different watchdogs, a hardware watchdog and a software watchdog. The hardware watchdog timer is clocked by low-speed internal CR oscillator. Therefore, the hardware watchdog is active in any power saving mode except RTC mode and stop mode. CRC (Cyclic Redundancy Check) Accelerator The CRC accelerator helps verify data transmission or storage integrity. CCTT CRC16 and EEE CRC32 are supported. CCTT CRC16 Generator Polynomial: 0x1021 EEE CRC32 Generator Polynomial: 0x04C11DB7 PRGCRC (Programmable Cyclic Redundancy Check) Accelerator The CRC accelerator helps verify data transmission or storage integrity. CCTT CRC16, EEE CRC32 and a generating polynominal are supported. CCTT CRC16 Generator Polynomial: 0x1021 EEE CRC32 Generator Polynomial: 0x04C11DB7 Generating polynominal 2 S nterface (TX x two channels, RX x two channels) Support three transfer protocols 2 S Left Justified DSP mode Master/Slave Mode selectable RX only, TX only or TX and RX simultaneous operation selectable Word length is programmable from 7 bits to 32 bits RX/TX FFO integrated (RX: 66 words x 32 bits, TX: 66 words x 32 bits) DMA, interrupts, or polling based data transfer supported Document Number: Rev.*C Page 3 of 182

4 GDC Unit Controller for external graphics display Accelerator for 2D block image transfer (blit) operations Embedded SRAM video memory High-Speed Quad SP (Serial Peripheral nterface for external memory extensions) SDRAM interface for external memory extensions HB (Hyper Bus nterface) interface for external memory extensions Maximum core system clock frequency : 160 MHz Clock and Reset Clocks Five clock sources (two external oscillators, two internal CR oscillator, and Main PLL) that are dynamically selectable. Main clock: 4 MHz to 20 MHz Sub Clock : khz High-speed internal CR Clock: 4 MHz Low-speed internal CR Clock: 100 khz Main PLL Clock Resets Reset requests from NTX pin Power on reset Software reset Watchdog timers reset Low voltage detector reset Clock supervisor reset Clock Super Visor (CSV) Clocks generated by internal CR oscillators are used to supervise abnormality of the external clocks. External OSC clock failure (clock stop) is detected, reset is asserted. External OSC frequency anomaly is detected, interrupt or reset is asserted. Low-Voltage Detector (LVD) This Series include 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the voltage has been set, Low-Voltage Detector generates an interrupt or reset. LVD1: error reporting via interrupt LVD2: auto-reset operation Low-Power Consumption Mode Six low-power consumption modes are supported. Sleep Timer RTC Stop Deep standby RTC (selectable from with/without RAM retention) Deep standby Stop (selectable from with/without RAM retention) Peripheral Clock Gating The system can reduce the current consumption of the total system with gating the operation clocks of peripheral functions not used. VBAT The consumption power during the RTC operation can be reduced by supplying the power supply independent from the RTC (calendar circuit)/32 khz oscillation circuit. The following circuits can also be used. RTC 32 khz oscillation circuit Power-on circuit Back up register : 32 bytes Port circuit Debug Serial Wire Debug Port (SWJ-DP) Embedded Trace Macrocells (ETM) provide comprehensive debug and trace facilities. Unique D Unique value of the device (41-bit) is set. Power Supply Two Power Supplies Power supply: VCC= 2.7 V to 3.6 V (when USB or GDC unit is not used) = 3.0 V to 3.6 V (when USB or GDC unit is used) Power supply for VBAT: VBAT = 1.65 V to 3.6 V Document Number: Rev.*C Page 4 of 182

5 Table of Contents Features Product Lineup Packages Pin Assignment Pin Descriptions /O Circuit Type Handling Precautions Precautions for Product Design Precautions for Package Mounting Precautions for Use Environment Handling Devices Block Diagram Memory Size Memory Map Pin Status in Each CPU State Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions DC Characteristics Current Rating Pin Characteristics AC Characteristics Main Clock nput Characteristics Sub Clock nput Characteristics Built-in CR Oscillation Characteristics Operating Conditions of Main PLL (n the Case of Using Main Clock for nput Clock of PLL) Operating Conditions of USB/ 2 S/GDC PLL (n the Case of Using Main Clock for nput Clock of PLL) Operating Conditions of Main PLL (n the Case of Using Built-in High-Speed CR Clock for nput Clock of Main PLL) Reset nput Characteristics Power-on Reset Timing GPO Output Characteristics External Bus Timing Base Timer nput Timing CSO Timing External nput Timing Quadrature Position/Revolution Counter Timing C Timing ETM Timing JTAG Timing S Timing GDC:Panel Output Timing GDC: SDRAM-F Timing GDC: High-Speed Quad SP Timing GDC: HyperBus /F Timing bit A/D Converter USB Characteristics Document Number: Rev.*C Page 5 of 182

6 12.7 Low-Voltage Detection Characteristics Low-Voltage Detection Reset nterrupt of Low-Voltage Detection MainFlash Memory Write/Erase Characteristics VFLASH Memory Write/Erase Characteristics Standby Recovery Time Recovery Cause: nterrupt/wkup Recovery Cause: Reset Ordering nformation Package Dimensions Errata Part Numbers Affected Qualification Status Errata Summary Major Changes Document History Sales, Solutions, and Legal nformation Document Number: Rev.*C Page 6 of 182

7 1. Product Lineup Memory Size Product Name S6E2D55G0A S6E2D55J0A S6E2D55GJA On-chip Flash memory 384 Kbytes SRAM 36 Kbytes On-chip SRAM SRAM0 32 Kbytes SRAM2 4 Kbytes VRAM for GDC 512 Kbytes VFLASH for GDC - 2 Mbytes Function Product Name S6E2D55G0A S6E2D55J0A S6E2D55GJA Pin count 120/ CPU Cortex-M4F, MPU, NVC 128ch. Freq. 160 MHz Power supply voltage range 2.7 V to 3.6 V USB2.0 (Device/Host) 1ch. CAN-FD (non-so CAN FD) 1ch. DMAC 8ch. DSTC 128ch. Graphics Display controller 1 unit GDC High-Speed Quad SP 1ch. (VFLASH only) unit Hyper Bus nterface 1 unit - SDRAM-F - 1ch. - External Bus nterface Addr:25-bit (Max), Data: 8-/16-bit, CS:2 (Max) SRAM, NOR Flash, NAND Flash, SDRAM Multi-function Serial nterface (UART/CSO/LN/ 2 C) 8ch. (Max) Base Timer (PWC/Reload timer/pwm/ppg) 8ch. (Max) A/D activation compare 6ch. nput capture 4ch. Free-run timer 3ch. Output compare 6ch. 1 unit Waveform generator 3ch. PPG 3ch. 2 S 2 units QPRC 1ch. Dual Timer 1 unit Real-Time Clock 1 unit Watch Counter 1 unit CRC Accelerator Yes(Fixed, Programmable) Watchdog Timer 1ch. (SW) + 1ch. (HW) External nterrupts 16 pins (Max)+ NM 1 /O ports 98 pins (Max) 154 pins (Max) 90 pins (Max) 12-bit A/D converter 24ch. (2 units) CSV (Clock Super Visor) Yes LVD (Low-Voltage Detector) 2ch. Built-in CR High-speed 4 MHz Low-speed 100 khz Debug Function SWJ-DP/ETM Unique D Yes MF Timer Document Number: Rev.*C Page 7 of 182

8 Notes: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. t is necessary to use the port relocate function of the /O port according to your function use. See Built-in CR Oscillation Characteristics for the accuracy of the built-in CR. 2. Packages Package Product Name S6E2D55G0A S6E2D55J0A S6E2D55GJA LQFP: LQM120 (0.5 mm pitch) - LQFP: LQP176 (0.5 mm pitch) - - FBGA: FDJ161 (0.5 mm pitch) - - Ex-LQFP(TEQFP): LEM120 (0.5 mm pitch) - - : Supported Note: See 14. Package Dimensions for detailed information on each package. Document Number: Rev.*C Page 8 of 182

9 3. Pin Assignment LQM120 / LEM120 (TOP VEW) VSS P81/UDP0 P80/UDM0 VCC P60/SN4_0/NT15_1/WKUP3/MALE_0 P61/UHCONX0/SOT4_0/TX2_0/RTCCO_0/SUBOUT_0/MDQM0_0 P62/SCK4_0/RX2_0/NT14_1/MDQM1_0 P63/ADTG_3/RTS4_0/PNL_PD0 P64/CTS4_0/PNL_PD1 P65/PNL_PD2 P66/SN3_1/NT13_1/PNL_PD3 P67/SOT3_1/PNL_PD4/MSDCKE_0 P68/SCK3_1/PNL_PD5/MSDCLK_0 VSS P0E/WKUP2/PNL_PD6/MCSX8_0 P0D/PNL_PD7/MSDWEX_0 P0C/SCK5_1/PNL_PD8/MAD11_0 P0B/SOT5_1/TOB7_1/PNL_PD9/MAD12_0 P0A/SN5_1/TOA7_1/NT12_1/PNL_PD10/MAD13_0 P09/SCK2_1/PNL_PD11/MAD14_0 P08/SOT2_1/PNL_PD12/MAD15_0 P07/SN2_1/NT11_1/PNL_PD13/MAD16_0 P06/TX2_2/PNL_PD14/MAD17_0 P05/RX2_2/NT10_1/PNL_PD15/MAD18_0 P04/TDO/SWO P03/TMS/SWDO P02/TD/MAD24_0 P01/TCK/SWCLK P00/TRSTX VCC VCC 1 90 VSS P3B/TOA0_1/NT04_1/AN0_1/2SMCLK0_0/RTO00_0/MAD10_ P97/AN23/PNL_PD16/MCASX_0 P3C/SCS70_0/TOA1_1/NT05_1/BN0_1/2SDO0_0/RTO01_0/MAD09_ P96/AN22/PNL_TSG5/PNL_PD17/MRASX_0 P3D/SN7_0/TOA2_1/NT06_1/ZN0_1/2SWS0_0/RTO02_0/MAD08_ P95/AN21/SCK1_1/PNL_TSG6/PNL_PD18/MAD19_0 P3E/SOT7_0/TOA3_1/NT07_1/2SD0_0/RTO03_0/MAD07_ P94/AN20/SOT1_1/TRACED3/PNL_TSG7/PNL_PD19/MAD20_0 P3F/SCK7_0/TOA4_1/2SCK0_0/RTO04_0/MAD06_ P93/AN19/SN1_1/TRACED2/NT09_1/PNL_TSG8/PNL_PD20/MNREX_0/MAD21_0 P7C/TOA5_1/RTO05_0/MWEX_ P92/AN18/SCK0_1/TRACED1/PNL_TSG9/PNL_PD21/MNWEX_0/MAD22_0 P7B/ADTG_2/MOEX_0/GE_HBCSX P91/AN17/SOT0_1/TRACED0/PNL_TSG10/PNL_PD22/MNCLE_0/MAD23_0 P33/SN6_0/NT00_ P90/AN16/SN0_1/TRACECLK/NT08_1/PNL_TSG11/PNL_PD23/MNALE_0/MCLKOUT_0 P34/SOT6_0/FRCK0_ P1F/AN15/SCK6_1/TOB7_0/MADATA15_0 P35/SCK6_0/C03_ P1E/AN14/SOT6_1/TOA7_0/RTO05_1/MADATA14_0 P36/SCS60_0/NT01_1/C02_ P1D/AN13/SN6_1/TOB6_0/NT15_0/RTO04_1/MADATA13_0 VCC P1C/AN12/SCS60_1/TOA6_0/NT14_0/RTO03_1/MADATA12_0 120pin Package VSS P1B/AN11/SCK5_0/TOB5_0/ZN0_2/RTO02_1/MADATA11_0 P37/RX2_1/NT02_1/GE_HBRESETX/C01_ P1A/AN10/SOT5_0/TOA5_0/BN0_2/RTO01_1/MADATA10_0 P38/TX2_1/NT03_1/GE_HBNTX/C00_ P19/AN09/SN5_0/TOB4_0/NT13_0/AN0_2/RTO00_1/MADATA09_0 P39/ADTG_0/GE_HBRSTOX/DTT0X_ P18/AN08/SCK3_0/TOA4_0/C03_1/MADATA08_0 P3A/GE_HBWPX P17/AN07/SOT3_0/TOB3_0/C02_1/MADATA07_0 P7A/GE_HBRWDS P16/AN06/SN3_0/TOA3_0/NT12_0/C01_1/MADATA06_0 P70/GE_SPCK/GE_HBCK P15/AN05/SCK2_0/TOB2_0/NT11_0/C00_1/MADATA05_0 P71/GE_SPDQ0/GE_HBCSX P14/AN04/SOT2_0/TOA2_0/DTT0X_1/MADATA04_0 P72/NT00_0/GE_SPDQ3/GE_HBDQ P13/AN03/SN2_0/TOB1_0/NT10_0/FRCK0_1/MADATA03_0 P73/NT01_0/GE_SPCSX0/GE_HBDQ P12/AN02/SCK1_0/TOA1_0/ZN0_0/MADATA02_0 P74/NT02_0/GE_SPDQ1/GE_HBDQ P11/AN01/SOT1_0/TOB0_0/BN0_0/MADATA01_0 P75/NT03_0/GE_SPDQ2/GE_HBDQ P10/AN00/SN1_0/TOA0_0/NT09_0/AN0_0/MADATA00_0 P76/NT04_0/GE_HBDQ AVRH P77/NT05_0/GE_HBDQ AVRL P78/NT06_0/GE_HBDQ AVSS P79/NT07_0/GE_HBDQ AVCC VCC VCC VSS P20/NMX/WKUP0 P21/2SMCLK1_0/MAD05_0 P22/SN0_0/NT08_0/2SDO1_0/CROUT_0/MAD04_0 P23/SOT0_0/TOA6_1/2SWS1_0/MAD03_0 P24/SCK0_0/TOB6_1/2SD1_0/MAD02_0 P25/2SCK1_0/MAD01_0 C VSS VCC P26/RTCCO_1/SUBOUT_1/MAD00_0 P27/ADTG_1/CROUT_1/MRDY_0 P50/WKUP1/MCSX0_0 P51/TOB0_1/PNL_TSG4/PNL_PWE P52/TOB1_1/PNL_DCLK P53/TOB2_1/PNL_TSG2/PNL_DEN P54/TOB3_1/PNL_TSG3/PNL_LE P55/TOB4_1/PNL_TSG0/PNL_LH_SYNC P56/TOB5_1/PNL_TSG1/PNL_FV_SYNC NTX P46/X0A P47/X1A VBATVCC P48/VREGCTL P49/VWAKEUP PE0/MD1 MD0 PE2/X0 PE3/X1 VSS Note: The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: Rev.*C Page 9 of 182

10 LQM120 (S6E2D55GJA) (TOP VEW) VSS P81/UDP0 P80/UDM0 VCC P60/SN4_0/NT15_1/WKUP3/MALE_0 P61/UHCONX0/SOT4_0/TX2_0/RTCCO_0/SUBOUT_0/MDQM0_0 P62/SCK4_0/RX2_0/NT14_1/MDQM1_0 P63/ADTG_3/RTS4_0/PNL_PD0 P64/CTS4_0/PNL_PD1 P65/PNL_PD2 P66/SN3_1/NT13_1/PNL_PD3 P67/SOT3_1/PNL_PD4/MSDCKE_0 P68/SCK3_1/PNL_PD5/MSDCLK_0 VSS P0E/WKUP2/PNL_PD6/MCSX8_0 P0D/PNL_PD7/MSDWEX_0 P0C/SCK5_1/PNL_PD8/MAD11_0 P0B/SOT5_1/TOB7_1/PNL_PD9/MAD12_0 P0A/SN5_1/TOA7_1/NT12_1/PNL_PD10/MAD13_0 P09/SCK2_1/PNL_PD11/MAD14_0 P08/SOT2_1/PNL_PD12/MAD15_0 P07/SN2_1/NT11_1/PNL_PD13/MAD16_0 P06/TX2_2/PNL_PD14/MAD17_0 P05/RX2_2/NT10_1/PNL_PD15/MAD18_0 P04/TDO/SWO P03/TMS/SWDO P02/TD/MAD24_0 P01/TCK/SWCLK P00/TRSTX VCC VCC 1 90 VSS P3B/TOA0_1/NT04_1/AN0_1/2SMCLK0_0/RTO00_0/MAD10_ P97/AN23/PNL_PD16/MCASX_0 P3C/SCS70_0/TOA1_1/NT05_1/BN0_1/2SDO0_0/RTO01_0/MAD09_ P96/AN22/PNL_TSG5/PNL_PD17/MRASX_0 P3D/SN7_0/TOA2_1/NT06_1/ZN0_1/2SWS0_0/RTO02_0/MAD08_ P95/AN21/SCK1_1/PNL_TSG6/PNL_PD18/MAD19_0 P3E/SOT7_0/TOA3_1/NT07_1/2SD0_0/RTO03_0/MAD07_ P94/AN20/SOT1_1/TRACED3/PNL_TSG7/PNL_PD19/MAD20_0 P3F/SCK7_0/TOA4_1/2SCK0_0/RTO04_0/MAD06_ P93/AN19/SN1_1/TRACED2/NT09_1/PNL_TSG8/PNL_PD20/MNREX_0/MAD21_0 P7C/TOA5_1/RTO05_0/MWEX_ P92/AN18/SCK0_1/TRACED1/PNL_TSG9/PNL_PD21/MNWEX_0/MAD22_0 P7B/ADTG_2/MOEX_ P91/AN17/SOT0_1/TRACED0/PNL_TSG10/PNL_PD22/MNCLE_0/MAD23_0 P33/SN6_0/NT00_ P90/AN16/SN0_1/TRACECLK/NT08_1/PNL_TSG11/PNL_PD23/MNALE_0/MCLKOUT_0 P34/SOT6_0/FRCK0_ P1F/AN15/SCK6_1/TOB7_0/MADATA15_0 P35/SCK6_0/C03_ P1E/AN14/SOT6_1/TOA7_0/RTO05_1/MADATA14_0 P36/SCS60_0/NT01_1/C02_ P1D/AN13/SN6_1/TOB6_0/NT15_0/RTO04_1/MADATA13_0 VCC P1C/AN12/SCS60_1/TOA6_0/NT14_0/RTO03_1/MADATA12_0 120pin Package VSS P1B/AN11/SCK5_0/TOB5_0/ZN0_2/RTO02_1/MADATA11_0 P37/RX2_1/NT02_1/C01_ P1A/AN10/SOT5_0/TOA5_0/BN0_2/RTO01_1/MADATA10_0 P38/TX2_1/NT03_1/C00_ P19/AN09/SN5_0/TOB4_0/NT13_0/AN0_2/RTO00_1/MADATA09_0 P39/ADTG_0/DTT0X_ P18/AN08/SCK3_0/TOA4_0/C03_1/MADATA08_0 P3A P17/AN07/SOT3_0/TOB3_0/C02_1/MADATA07_0 (N.C.) P16/AN06/SN3_0/TOA3_0/NT12_0/C01_1/MADATA06_0 (N.C.) P15/AN05/SCK2_0/TOB2_0/NT11_0/C00_1/MADATA05_0 (N.C.) P14/AN04/SOT2_0/TOA2_0/DTT0X_1/MADATA04_0 VCC P13/AN03/SN2_0/TOB1_0/NT10_0/FRCK0_1/MADATA03_0 (DNU0)* P12/AN02/SCK1_0/TOA1_0/ZN0_0/MADATA02_0 (DNU1)* P11/AN01/SOT1_0/TOB0_0/BN0_0/MADATA01_0 (N.C.) P10/AN00/SN1_0/TOA0_0/NT09_0/AN0_0/MADATA00_0 (N.C.) AVRH P77/NT05_ AVRL P78/NT06_ AVSS P79/NT07_ AVCC VCC VCC VSS P20/NMX/WKUP0 P21/2SMCLK1_0/MAD05_0 P22/SN0_0/NT08_0/2SDO1_0/CROUT_0/MAD04_0 P23/SOT0_0/TOA6_1/2SWS1_0/MAD03_0 P24/SCK0_0/TOB6_1/2SD1_0/MAD02_0 P25/2SCK1_0/MAD01_0 C VSS VCC P26/RTCCO_1/SUBOUT_1/MAD00_0 P27/ADTG_1/CROUT_1/MRDY_0 P50/WKUP1/MCSX0_0 P51/TOB0_1/PNL_TSG4/PNL_PWE P52/TOB1_1/PNL_DCLK P53/TOB2_1/PNL_TSG2/PNL_DEN P54/TOB3_1/PNL_TSG3/PNL_LE P55/TOB4_1/PNL_TSG0/PNL_LH_SYNC P56/TOB5_1/PNL_TSG1/PNL_FV_SYNC NTX P46/X0A P47/X1A VBATVCC P48/VREGCTL P49/VWAKEUP PE0/MD1 MD0 PE2/X0 PE3/X1 VSS *1: The DNU0 / 1 (23 pin / 24 pin), please pull up and short-circuit on the board. For more information, please refer to the 7. Handling Devices. (N.C.): Do not connect anything. Note: The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: Rev.*C Page 10 of 182

11 LQP176 (TOP VEW) VSS P81/UDP0 P80/UDM0 VCC P60/SN4_0/NT15_1/WKUP3/MALE_0 P61/UHCONX0/SOT4_0/TX2_0/RTCCO_0/SUBOUT_0/MDQM0_0 P62/SCK4_0/RX2_0/NT14_1/MDQM1_0 PDD/GE_SDCSX PDC/GE_SDCASX PDB/GE_SDRASX PDA/GE_SDWEX P63/ADTG_3/RTS4_0/PNL_PD0 P64/CTS4_0/PNL_PD1 P65/PNL_PD2 P66/SN3_1/NT13_1/PNL_PD3 P67/SOT3_1/PNL_PD4/MSDCKE_0 P68/SCK3_1/PNL_PD5/MSDCLK_0 VSS P0E/WKUP2/PNL_PD6/MCSX8_0 P0D/PNL_PD7/MSDWEX_0 P0C/SCK5_1/PNL_PD8/MAD11_0 P0B/SOT5_1/TOB7_1/PNL_PD9/MAD12_0 P0A/SN5_1/TOA7_1/NT12_1/PNL_PD10/MAD13_0 P09/SCK2_1/PNL_PD11/MAD14_0 P08/SOT2_1/PNL_PD12/MAD15_0 P07/SN2_1/NT11_1/PNL_PD13/MAD16_0 P06/TX2_2/PNL_PD14/MAD17_0 P05/RX2_2/NT10_1/PNL_PD15/MAD18_0 PD9/GE_SDDQM0 PD8/GE_SDDQM1 PD7/GE_SDDQM2 PD6/GE_SDDQM3 PD5/GE_SDA0 P04/TDO/SWO P03/TMS/SWDO P02/TD/MAD24_0 P01/TCK/SWCLK P00/TRSTX PD4/GE_SDA1 PD3/GE_SDA2 PD2/GE_SDA3 PD1/GE_SDA4 PD0/GE_SDA5 VCC VCC VSS PA0/GE_SDCKE P97/AN23/PNL_PD16/MCASX_0 PA1/GE_SDCLK P96/AN22/PNL_TSG5/PNL_PD17/MRASX_0 PA2/GE_SDDQ PCD/GE_SDA6 PA3/GE_SDDQ PCC/GE_SDA7 P3B/TOA0_1/NT04_1/AN0_1/2SMCLK0_0/RTO00_0/MAD10_ PCB/GE_SDA8 P3C/SCS70_0/TOA1_1/NT05_1/BN0_1/2SDO0_0/RTO01_0/MAD09_ PCA/GE_SDA9 P3D/SN7_0/TOA2_1/NT06_1/ZN0_1/2SWS0_0/RTO02_0/MAD08_ P95/AN21/SCK1_1/PNL_TSG6/PNL_PD18/MAD19_0 P3E/SOT7_0/TOA3_1/NT07_1/2SD0_0/RTO03_0/MAD07_ P94/AN20/SOT1_1/TRACED3/PNL_TSG7/PNL_PD19/MAD20_0 P3F/SCK7_0/TOA4_1/2SCK0_0/RTO04_0/MAD06_ P93/AN19/SN1_1/TRACED2/NT09_1/PNL_TSG8/PNL_PD20/MNREX_0/MAD21_0 P7C/TOA5_1/RTO05_0/MWEX_ P92/AN18/SCK0_1/TRACED1/PNL_TSG9/PNL_PD21/MNWEX_0/MAD22_0 P7B/ADTG_2/MOEX_0/GE_HBCSX P91/AN17/SOT0_1/TRACED0/PNL_TSG10/PNL_PD22/MNCLE_0/MAD23_0 PA8/GE_SDDQ P90/AN16/SN0_1/TRACECLK/NT08_1/PNL_TSG11/PNL_PD23/MNALE_0/MCLKOUT_0 PA9/GE_SDDQ P1F/AN15/SCK6_1/TOB7_0/MADATA15_0 PAA/GE_SDDQ P1E/AN14/SOT6_1/TOA7_0/RTO05_1/MADATA14_0 PAB/GE_SDDQ P1D/AN13/SN6_1/TOB6_0/NT15_0/RTO04_1/MADATA13_0 PAC/GE_SDDQ P1C/AN12/SCS60_1/TOA6_0/NT14_0/RTO03_1/MADATA12_0 PAD/GE_SDDQ PC9/GE_SDA10 P33/SN6_0/NT00_ PC8/GE_SDA11 P34/SOT6_0/FRCK0_ PC7/GE_SDBA0 P35/SCK6_0/C03_ PC6/GE_SDBA1 P36/SCS60_0/NT01_1/C02_ P1B/AN11/SCK5_0/TOB5_0/ZN0_2/RTO02_1/MADATA11_0 VCC P1A/AN10/SOT5_0/TOA5_0/BN0_2/RTO01_1/MADATA10_0 VSS P19/AN09/SN5_0/TOB4_0/NT13_0/AN0_2/RTO00_1/MADATA09_0 P37/RX2_1/NT02_1/GE_HBRESETX/C01_ P18/AN08/SCK3_0/TOA4_0/C03_1/MADATA08_0 P38/TX2_1/NT03_1/GE_HBNTX/C00_ P17/AN07/SOT3_0/TOB3_0/C02_1/MADATA07_0 P39/ADTG_0/GE_HBRSTOX/DTT0X_ P16/AN06/SN3_0/TOA3_0/NT12_0/C01_1/MADATA06_0 P3A/GE_HBWPX P15/AN05/SCK2_0/TOB2_0/NT11_0/C00_1/MADATA05_0 PA4/GE_SDDQ P14/AN04/SOT2_0/TOA2_0/DTT0X_1/MADATA04_0 PA5/GE_SDDQ P13/AN03/SN2_0/TOB1_0/NT10_0/FRCK0_1/MADATA03_0 PA6/GE_SDDQ P12/AN02/SCK1_0/TOA1_0/ZN0_0/MADATA02_0 PA7/GE_SDDQ P11/AN01/SOT1_0/TOB0_0/BN0_0/MADATA01_0 P7A/GE_HBRWDS P10/AN00/SN1_0/TOA0_0/NT09_0/AN0_0/MADATA00_0 P70/GE_SPCK/GE_HBCK PC5/GE_SDDQ0 P71/GE_SPDQ0/GE_HBCSX PC4/GE_SDDQ1 P72/NT00_0/GE_SPDQ3/GE_HBDQ PC3/GE_SDDQ2 P73/NT01_0/GE_SPCSX0/GE_HBDQ PC2/GE_SDDQ3 P74/NT02_0/GE_SPDQ1/GE_HBDQ PC1/GE_SDDQ4 P75/NT03_0/GE_SPDQ2/GE_HBDQ PC0/GE_SDDQ5 P76/NT04_0/GE_HBDQ AVRH P77/NT05_0/GE_HBDQ AVRL P78/NT06_0/GE_HBDQ AVSS P79/NT07_0/GE_HBDQ AVCC VCC VCC VSS P20/NMX/WKUP0 PB0/GE_SDDQ19 PB1/GE_SDDQ18 PB2/GE_SDDQ17 PB3/GE_SDDQ16 P21/2SMCLK1_0/MAD05_0 P22/SN0_0/NT08_0/2SDO1_0/CROUT_0/MAD04_ P23/SOT0_0/TOA6_1/2SWS1_0/MAD03_0 P24/SCK0_0/TOB6_1/2SD1_0/MAD02_0 P25/2SCK1_0/MAD01_0 PB4/GE_SDDQ15 PB5/GE_SDDQ14 PB6/GE_SDDQ13 PB7/GE_SDDQ C 176pin Package VSS VCC P26/RTCCO_1/SUBOUT_1/MAD00_0 P27/ADTG_1/CROUT_1/MRDY_0 P50/WKUP1/MCSX0_0 P51/TOB0_1/PNL_TSG4/PNL_PWE P52/TOB1_1/PNL_DCLK P53/TOB2_1/PNL_TSG2/PNL_DEN P54/TOB3_1/PNL_TSG3/PNL_LE P55/TOB4_1/PNL_TSG0/PNL_LH_SYNC P56/TOB5_1/PNL_TSG1/PNL_FV_SYNC PB8/GE_SDDQ11 PB9/GE_SDDQ10 PBA/GE_SDDQ9 PBB/GE_SDDQ8 PBC/GE_SDDQ7 PBD/GE_SDDQ6 NTX P46/X0A P47/X1A VBATVCC P48/VREGCTL P49/VWAKEUP PE0/MD1 MD0 PE2/X0 PE3/X1 VSS Note: The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: Rev.*C Page 11 of 182

12 FDJ 161 (TOP VEW) A VSS UDP0 UDM0 VCC VSS P66 VSS P0C P09 VSS TCK VCC VSS B VSS P60 P61 P62 P64 P67 P0E P0B P08 TDO TMS TRSTX VSS C VCC P3C P3B P63 P65 P68 P0D P0A P07 P05 TD P96 P97 D P3F P3E P3D P7C VSS VSS VSS VSS P06 P92 P93 P94 P95 E P35 P34 P33 P7B VSS VSS VSS VSS VSS P1E P1F P90 P91 F P39 P38 P37 P36 VSS VSS VSS P1A P1B P1C P1D G VCC P7A P3A VSS VSS VSS P16 P17 P18 P19 H VSS P72 P73 VSS VSS VSS P12 P13 P14 P15 J P70 P74 P75 VSS VSS VSS VSS VSS VSS VSS P11 AVRH AVRL K P71 P76 P77 VSS P24 VSS P50 P52 P54 VSS P10 AVSS AVCC L VCC P78 P79 P22 P25 VSS P51 P53 P55 P56 P48 P49 VCC M VSS P20 P21 P23 P26 VSS VSS NTX VBAT VSS MD0 MD1 VSS N VSS C VSS VCC P27 VSS X0A VSS X1A VSS X0 X1 VSS Note: The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Document Number: Rev.*C Page 12 of 182

13 4. Pin Descriptions List of Pin Functions The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin No. LQFP176 LQFP120 LQFP120 Ex-LQFP120 (S6E2D55GJA) FBGA161 Pin name /O circuit type C1 VCC C C D3 PA0 GE_SDCKE PA1 GE_SDCLK PA2 GE_SDDQ31 PA3 GE_SDDQ30 P3B TOA0_1 NT04_1 AN0_1 2SMCLK0_0 RTO00_0 (PPG00_0) MAD10_0 P3C SCS70_0 TOA1_1 NT05_1 BN0_1 2SDO0_0 RTO01_0 (PPG00_0) MAD09_0 P3D SN7_0 TOA2_1 NT06_1 ZN0_1 2SWS0_0 RTO02_0 (PPG02_0) MAD08_0 K K L L G G G Pin type K K K Document Number: Rev.*C Page 13 of 182

14 Pin No. LQFP176 LQFP120 LQFP120 Ex-LQFP120 (S6E2D55GJA) FBGA161 Pin name P3E /O circuit type Pin type SOT7_0 (SDA7_0) TOA3_ D2 NT07_1 G K 2SD0_0 RTO03_0 (PPG02_0) MAD07_0 P3F SCK7_0 (SCL7_0) D1 TOA4_1 2SCK0_0 G RTO04_0 (PPG04_0) MAD06_0 P7C TOA5_ D4 RTO05_0 (PPG04_0) G MWEX_0 P7B E4 ADTG_2 GE_HBCSX1 K MOEX_0 P7B ADTG_2 K MOEX_ PA8 GE_SDDQ29 L PA9 GE_SDDQ28 L PAA GE_SDDQ27 L PAB GE_SDDQ26 L PAC GE_SDDQ25 L PAD GE_SDDQ24 L Document Number: Rev.*C Page 14 of 182

15 Pin No. LQFP176 LQFP120 LQFP120 Ex-LQFP120 (S6E2D55GJA) FBGA E E E F4 Pin name P33 SN6_0 NT00_1 P34 SOT6_0 (SDA6_0) FRCK0_0 P35 SCK6_0 (SCL6_0) C03_0 P36 SCS60_0 NT01_1 C02_0 /O circuit type G1 VCC H1 VSS F F P37 RX2_1 GE_HBRESETX NT02_1 C01_0 P37 RX2_1 NT02_1 C01_0 P38 TX2_1 GE_HBNTX NT03_1 C00_0 P38 TX2_1 NT03_1 C00_0 D D D D D D D D Pin type K K K K K K Document Number: Rev.*C Page 15 of 182

16 Pin No. LQFP176 LQFP120 LQFP120 Ex-LQFP120 (S6E2D55GJA) FBGA F G3 Pin name P39 ADTG_0 GE_HBRSTOX DTT0X_0 P39 ADTG_0 DTT0X_0 P3A GE_HBWPX /O circuit type P3A E G2 PA4 GE_SDDQ23 PA5 GE_SDDQ22 PA6 GE_SDDQ21 PA7 GE_SDDQ20 P7A GE_HBRWDS (N.C.) J1 P70 GE_SPCK GE_HBCK (N.C.) K1 P71 GE_SPDQ0 GE_HBCSX (N.C.) H2 P72 GE_SPDQ3 GE_HBDQ0 NT00_ VCC H3 P73 GE_SPCSX0 GE_HBDQ1 NT01_ (DNU0) J2 P74 GE_SPDQ1 GE_HBDQ2 NT02_0 E E E L L L L K K K K K K Pin type K K K Document Number: Rev.*C Page 16 of 182

17 Pin No. LQFP176 LQFP120 LQFP120 Ex-LQFP120 (S6E2D55GJA) FBGA161 Pin name /O circuit type (DNU1) J3 P75 GE_SPDQ2 GE_HBDQ3 NT03_ (N.C.) K2 P76 GE_HBDQ4 NT04_ (N.C.) K L L P77 GE_HBDQ5 NT05_0 P77 NT05_0 P78 GE_HBDQ6 NT06_0 P78 NT06_0 P79 GE_HBDQ7 NT07_0 P79 NT07_ L1 VCC M1 VSS M P20 NMX WKUP0 PB0 GE_SDDQ19 PB1 GE_SDDQ18 PB2 GE_SDDQ17 PB3 GE_SDDQ16 K K K K K K K K L L L L Pin type K K K K K K K K F Document Number: Rev.*C Page 17 of 182

18 Pin No. LQFP176 LQFP120 LQFP120 Ex-LQFP120 (S6E2D55GJA) FBGA M L M K L Pin name P21 2SMCLK1_0 MAD05_0 P22 CROUT_0 SN0_0 NT08_0 2SDO1_0 MAD04_0 P23 SOT0_0 (SDA0_0) TOA6_1 2SWS1_0 MAD03_0 P24 SCK0_0 (SCL0_0) TOB6_1 2SD1_0 MAD02_0 P25 2SCK1_0 MAD01_0 PB4 GE_SDDQ15 PB5 GE_SDDQ14 PB6 GE_SDDQ13 PB7 GE_SDDQ12 /O circuit type N2 C N3 VSS N4 VCC M N5 P26 RTCCO_1 SUBOUT_1 MAD00_0 P27 ADTG_1 CROUT_1 MRDY_0 E E E E E L L L L E E Pin type K Document Number: Rev.*C Page 18 of 182

19 Pin No. LQFP176 LQFP120 LQFP120 Ex-LQFP120 (S6E2D55GJA) FBGA K L K L K L L Pin name P50 WKUP1 MCSX0_0 P51 TOB0_1 PNL_PWE PNL_TSG4 P52 TOB1_1 PNL_DCLK P53 TOB2_1 PNL_DEN PNL_TSG2 P54 TOB3_1 PNL_LE PNL_TSG3 P55 TOB4_1 PNL_LH_SYNC PNL_TSG0 P56 TOB5_1 PNL_FV_SYNC PNL_TSG1 PB8 GE_SDDQ11 PB9 GE_SDDQ10 PBA GE_SDDQ9 PBB GE_SDDQ8 PBC GE_SDDQ7 PBD GE_SDDQ6 /O circuit type M8 NTX B C N N9 P46 X0A P47 X1A D E D E E E E L L L L L L P Q Pin type P S T Document Number: Rev.*C Page 19 of 182

20 Pin No. LQFP176 LQFP120 LQFP120 Ex-LQFP120 (S6E2D55GJA) FBGA161 Pin name /O circuit type M9 VBAT L L M12 P48 VREGCTL P49 VWAKEUP M11 MD0 J D N N M13 VSS L13 VCC K13 AVCC K12 AVSS J13 AVRL J12 AVRH K11 PE0 MD1 PE2 X0 PE3 X1 PC0 GE_SDDQ5 PC1 GE_SDDQ4 PC2 GE_SDDQ3 PC3 GE_SDDQ2 PC4 GE_SDDQ1 PC5 GE_SDDQ0 P10 AN00 SN1_0 TOA0_0 NT09_0 AN0_0 MADATA00_0 O O C A A L L L L L L F Pin type U U E A B M Document Number: Rev.*C Page 20 of 182

21 Pin No. LQFP176 LQFP120 LQFP120 Ex-LQFP120 (S6E2D55GJA) FBGA161 Pin name /O circuit type Pin type P11 AN01 SOT1_ J11 (SDA1_0) F L TOB0_0 BN0_0 MADATA01_0 P12 AN02 SCK1_ H10 (SCL1_0) F L TOA1_0 ZN0_0 MADATA02_0 P13 AN03 SN2_ H11 TOB1_0 F M NT10_0 FRCK0_1 MADATA03_0 P14 AN04 SOT2_ H12 (SDA2_0) F L TOA2_0 DTT0X_1 MADATA04_0 P15 AN05 SCK2_ H13 (SCL2_0) TOB2_0 F M NT11_0 C00_1 MADATA05_0 P16 AN06 SN3_ G10 TOA3_0 F M NT12_0 C01_1 MADATA06_0 Document Number: Rev.*C Page 21 of 182

22 Pin No. LQFP176 LQFP120 LQFP120 Ex-LQFP120 (S6E2D55GJA) FBGA161 Pin name /O circuit type Pin type P17 AN07 SOT3_ G11 (SDA3_0) F L TOB3_0 C02_1 MADATA07_0 P18 AN08 SCK3_ G12 (SCL3_0) F L TOA4_0 C03_1 MADATA08_0 P19 AN09 SN5_0 TOB4_ G13 NT13_0 F M AN0_2 RTO00_1 (PPG00_1) MADATA09_0 P1A AN10 SOT5_0 (SDA5_0) F10 TOA5_0 F L BN0_2 RTO01_1 (PPG00_1) MADATA10_0 P1B AN11 SCK5_0 (SCL5_0) F11 TOB5_0 F L ZN0_2 RTO02_1 (PPG02_1) MADATA11_ PC6 GE_SDBA1 K Document Number: Rev.*C Page 22 of 182

23 Pin No. LQFP176 LQFP120 LQFP120 Ex-LQFP120 (S6E2D55GJA) FBGA161 Pin name /O circuit type Pin type PC7 GE_SDBA0 K PC8 GE_SDA11 K PC9 GE_SDA10 K P1C AN12 SCS60_ F12 TOA6_0 NT14_0 F M RTO03_1 (PPG02_1) MADATA12_0 P1D AN13 SN6_ F13 TOB6_0 NT15_0 F M RTO04_1 (PPG04_1) MADATA13_0 P1E AN14 SOT6_ E10 (SDA6_1) TOA7_0 F L RTO05_1 (PPG04_1) MADATA14_0 P1F AN E11 SCK6_1 (SCL6_1) F L TOB7_0 MADATA15_0 Document Number: Rev.*C Page 23 of 182

24 Pin No. LQFP176 LQFP120 LQFP120 Ex-LQFP120 (S6E2D55GJA) FBGA161 Pin name /O circuit type Pin type P90 AN16 SN0_1 NT08_ E12 PNL_PD23 F O PNL_TSG11 MCLKOUT_0 MNALE_0 TRACECLK P91 AN17 SOT0_1 (SDA0_1) E13 PNL_PD22 F N PNL_TSG10 MAD23_0 MNCLE_0 TRACED0 P92 AN18 SCK0_1 (SCL0_1) D10 PNL_PD21 F N PNL_TSG9 MAD22_0 MNWEX_0 TRACED1 P93 AN19 SN1_1 NT09_ D11 PNL_PD20 F O PNL_TSG8 MAD21_0 MNREX_0 TRACED2 P94 AN20 SOT1_ D12 (SDA1_1) PNL_PD19 F N PNL_TSG7 MAD20_0 TRACED3 Document Number: Rev.*C Page 24 of 182

25 Pin No. LQFP176 LQFP120 LQFP120 Ex-LQFP120 (S6E2D55GJA) FBGA D C C13 Pin name P95 AN21 SCK1_1 (SCL1_1) PNL_PD18 PNL_TSG6 MAD19_0 PCA GE_SDA9 PCB GE_SDA8 PCC GE_SDA7 PCD GE_SDA6 P96 AN22 PNL_PD17 PNL_TSG5 MRASX_0 P97 AN23 PNL_PD16 MCASX_0 /O circuit type B13 VSS A12 VCC B A11 PD0 GE_SDA5 PD1 GE_SDA4 PD2 GE_SDA3 PD3 GE_SDA2 PD4 GE_SDA1 P00 TRSTX P01 TCK SWCLK F K K K K F F K K K K K E E Pin type L L L G G Document Number: Rev.*C Page 25 of 182

26 Pin No. LQFP176 LQFP120 LQFP120 Ex-LQFP120 (S6E2D55GJA) FBGA161 Pin name /O circuit type Pin type P C11 TD E H MAD24_0 P B11 TMS E G SWDO P B10 TDO E G SWO PD5 GE_SDA0 K PD6 GE_SDDQM3 K PD7 GE_SDDQM2 K PD8 GE_SDDQM1 K PD9 GE_SDDQM0 K P05 RX2_ C10 NT10_1 E K PNL_PD15 MAD18_0 P D9 TX2_2 PNL_PD14 E MAD17_0 P07 SN2_ C9 NT11_1 E K PNL_PD13 MAD16_0 P08 SOT2_ B9 (SDA2_1) E PNL_PD12 MAD15_0 P09 SCK2_ A9 (SCL2_1) E PNL_PD11 MAD14_0 Document Number: Rev.*C Page 26 of 182

27 Pin No. LQFP176 LQFP120 LQFP120 Ex-LQFP120 (S6E2D55GJA) FBGA C B A C B7 Pin name /O circuit type Document Number: Rev.*C Page 27 of 182 P0A SN5_1 TOA7_1 NT12_1 PNL_PD10 MAD13_0 P0B SOT5_1 (SDA5_1) TOB7_1 PNL_PD9 MAD12_0 P0C SCK5_1 (SCL5_1) PNL_PD8 MAD11_0 P0D PNL_PD7 MSDWEX_0 P0E WKUP2 PNL_PD6 MCSX8_ A7 VSS C B A C B5 P68 SCK3_1 (SCL3_1) PNL_PD5 MSDCLK_0 P67 SOT3_1 (SDA3_1) PNL_PD4 MSDCKE_0 P66 SN3_1 NT13_1 PNL_PD3 P65 PNL_PD2 P64 CTS4_0 PNL_PD1 E E E D D D D E E E Pin type K P K

28 Pin No. LQFP176 LQFP120 LQFP120 Ex-LQFP120 (S6E2D55GJA) FBGA C B B B2 Pin name P63 ADTG_3 RTS4_0 PNL_PD0 PDA GE_SDWEX PDB GE_SDRASX PDC GE_SDCASX PDD GE_SDCSX P62 RX2_0 SCK4_0 (SCL4_0) NT14_1 MDQM1_0 P61 UHCONX0 RTCCO_0 SUBOUT_0 TX2_0 SOT4_0 (SDA4_0) MDQM0_0 P60 WKUP3 SN4_0 NT15_1 MALE_0 /O circuit type A4 VCC A A2 P80 UDM0 P81 UDP B1 VSS - - E K K K K N N H H Pin type K Q R R Document Number: Rev.*C Page 28 of 182

29 Pin No. LQFP176 LQFP120 LQFP120 Ex-LQFP120 (S6E2D55GJA) FBGA161 A1, A5, A10, A13, D5, D6, D7, D8, E5, E6, E7, E8, E9, F5, F6, F9, G4, G5, G9, H4, H5, H9, J4, J5, J6, J7, J8, J9, J10, K4, K6, K10, L6, M6, M7, M10, N1, N6, N8, N10, N13 Pin name /O circuit type Pin type VSS - - Document Number: Rev.*C Page 29 of 182

30 Signal Description The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin No. Module Pin Name Function LQFP176 LQFP120 Ex-LQFP120 LQFP120 (S6E2D55GJ A) FBGA161 ADC Base Timer 0 Base Timer 1 ADTG_ F1 ADTG_ N5 A/D converter external trigger pin ADTG_ E4 ADTG_ C4 AN K11 AN J11 AN H10 AN H11 AN H12 AN H13 AN G10 AN G11 AN G12 AN G13 AN F10 AN11 A/D converter analog pin F11 AN12 ANxx describes ADC ch.xx F12 AN F13 AN E10 AN E11 AN E12 AN E13 AN D10 AN D11 AN D12 AN D13 AN C12 AN C13 TOA0_ K11 Base Timer ch.0 TOA Pin TOA0_ C3 TOB0_ J11 Base Timer ch.0 TOB Pin TOB0_ L7 TOA1_ H10 Base Timer ch.1 TOA Pin TOA1_ C2 TOB1_ H11 Base Timer ch.1 TOB Pin TOB1_ K8 Document Number: Rev.*C Page 30 of 182

31 Pin No. Module Pin Name Function LQFP176 LQFP120 Ex-LQFP120 LQFP120 (S6E2D55GJ A) FBGA161 Base Timer 2 Base Timer 3 Base Timer 4 Base Timer 5 Base Timer 6 Base Timer 7 CAN (CAN-FD) Debugger TOA2_ H12 Base Timer ch.2 TOA Pin TOA2_ D3 TOB2_ H13 Base Timer ch.2 TOB Pin TOB2_ L8 TOA3_ G10 Base Timer ch.3 TOA Pin TOA3_ D2 TOB3_ G11 Base Timer ch.3 TOB Pin TOB3_ K9 TOA4_ G12 Base Timer ch.4 TOA Pin TOA4_ D1 TOB4_ G13 Base Timer ch.4 TOB Pin TOB4_ L9 TOA5_ F10 Base Timer ch.5 TOA Pin TOA5_ D4 TOB5_ F11 Base Timer ch.5 TOB Pin TOB5_ L10 TOA6_ F12 Base Timer ch.6 TOA Pin TOA6_ M4 TOB6_ F13 Base Timer ch.6 TOB Pin TOB6_ K5 TOA7_ E10 Base Timer ch.7 TOA Pin TOA7_ C8 TOB7_ E11 Base Timer ch.7 TOB Pin TOB7_ B8 TX2_ B3 TX2_1 CAN-FD interface TX output pin F2 TX2_ D9 RX2_ B4 RX2_1 CAN-FD interface RX pin F3 RX2_ C10 SWCLK Serial wire debug interface clock pin A11 SWDO Serial wire debug interface data / output pin B11 SWO Serial wire viewer output pin B10 TCK JTAG test clock pin A11 TD JTAG test data pin C11 TDO JTAG debug data output pin B10 TMS JTAG test mode output pin B11 TRACECLK Trace CLK output pin of ETM E12 TRACED E13 TRACED D10 Trace data output pin of ETM TRACED D11 TRACED D12 TRSTX JTAG test reset nput pin B12 Document Number: Rev.*C Page 31 of 182

32 Pin No. Module Pin Name Function LQFP176 LQFP120 Ex-LQFP120 LQFP120 (S6E2D55GJ A) FBGA161 External Bus MAD00_ M5 MAD01_ L5 MAD02_ K5 MAD03_ M4 MAD04_ L4 MAD05_ M3 MAD06_ D1 MAD07_ D2 MAD08_ D3 MAD09_ C2 MAD10_ C3 MAD11_ A8 MAD12_0 External bus interface address bus B8 MAD13_ C8 MAD14_ A9 MAD15_ B9 MAD16_ C9 MAD17_ D9 MAD18_ C10 MAD19_ D13 MAD20_ D12 MAD21_ D11 MAD22_ D10 MAD23_ E13 MAD24_ C11 MCSX0_ K7 External bus interface chip select output pin MCSX8_ B7 MADATA00_ K11 MADATA01_ J11 MADATA02_ H10 MADATA03_ H11 MADATA04_ H12 MADATA05_ H13 MADATA06_ G10 MADATA07_ G11 External bus interface data bus MADATA08_ G12 MADATA09_ G13 MADATA10_ F10 MADATA11_ F11 MADATA12_ F12 MADATA13_ F13 MADATA14_ E10 MADATA15_ E11 Document Number: Rev.*C Page 32 of 182

33 Pin No. Module Pin Name Function LQFP176 LQFP120 Ex-LQFP120 LQFP120 (S6E2D55GJ A) FBGA161 External Bus External nterrupt MDQM0_ B3 External bus interface byte mask signal output pin MDQM1_ B4 MALE_0 External bus interface Address Latch enable output signal for multiplex B2 MRDY_0 External bus interface external RDY signal N5 MCLKOUT_0 External bus interface external clock output pin E12 MNALE_0 MNCLE_0 MNREX_0 MNWEX_0 MOEX_0 MWEX_0 External bus interface ALE signal to control NAND Flash output pin External bus interface CLE signal to control NAND Flash output pin External bus interface read enable signal to control NAND Flash output pin External bus interface write enable signal to control NAND Flash output pin External bus interface read enable signal for SRAM External bus interface write enable signal for SRAM E E D D E D4 MSDCLK_0 SDRAM interface SDRAM clock output pin C6 MSDCKE_0 SDRAM interface SDRAM clock enable pin B6 MRASX_0 SDRAM interface SDRAM row active strobe pin C12 MCASX_0 SDRAM interface SDRAM column active strobe pin C13 MSDWEX_0 SDRAM interface SDRAM write enable pin C7 NT00_ H2 External interrupt request 00 pin NT00_ E3 NT01_ H3 External interrupt request 01 pin NT01_ F4 NT02_ J2 External interrupt request 02 pin NT02_ F3 NT03_ J3 External interrupt request 03 pin NT03_ F2 NT04_ K2 External interrupt request 04 pin NT04_ C3 NT05_ K3 External interrupt request 05 pin NT05_ C2 NT06_ L2 External interrupt request 06 pin NT06_ D3 NT07_ L3 External interrupt request 07 pin NT07_ D2 NT08_ L4 External interrupt request 08 pin NT08_ E12 NT09_ K11 External interrupt request 09 pin NT09_ D11 Document Number: Rev.*C Page 33 of 182

34 Pin No. Module Pin Name Function LQFP176 LQFP120 Ex-LQFP120 LQFP120 (S6E2D55GJ A) FBGA161 External nterrupt GPO NT10_ H11 External interrupt request 10 pin NT10_ C10 NT11_ H13 External interrupt request 11 pin NT11_ C9 NT12_ G10 External interrupt request 12 pin NT12_ C8 NT13_ G13 External interrupt request 13 pin NT13_ A6 NT14_ F12 External interrupt request 14 pin NT14_ B4 NT15_ F13 External interrupt request 15 pin NT15_ B2 NMX Non-Maskable nterrupt pin M2 P B12 P A11 P C11 P B11 P B10 P C10 P D9 P07 General-purpose /O port C9 P B9 P A9 P0A C8 P0B B8 P0C A8 P0D C7 P0E B7 P K11 P J11 P H10 P H11 P H12 P H13 P G10 P G11 General-purpose /O port 1 P G12 P G13 P1A F10 P1B F11 P1C F12 P1D F13 P1E E10 P1F E11 Document Number: Rev.*C Page 34 of 182

35 Pin No. Module Pin Name Function LQFP176 LQFP120 Ex-LQFP120 LQFP120 (S6E2D55GJ A) FBGA161 GPO P M2 P M3 P L4 P M4 General-purpose /O port 2 P K5 P L5 P M5 P N5 P E3 P E2 P E1 P F4 P F3 P F2 P39 General-purpose /O port F1 P3A G3 P3B C3 P3C C2 P3D D3 P3E D2 P3F D1 P N7 P N9 General-purpose /O port 4 P L11 P L12 P K7 P L7 P K8 P53 General-purpose /O port L8 P K9 P L9 P L10 P B2 P B3 P B4 P C4 P64 General-purpose /O port B5 P C5 P A6 P B6 P C6 Document Number: Rev.*C Page 35 of 182

36 Pin No. Module Pin Name Function LQFP176 LQFP120 Ex-LQFP120 LQFP120 (S6E2D55GJ A) FBGA161 GPO P J1 P K1 P H2 P H3 P J2 P J3 P76 General-purpose /O port K2 P K3 P L2 P L3 P7A G2 P7B E4 P7C D4 P A3 General-purpose /O port 8 P A2 P E12 P E13 P D10 P D11 General-purpose /O port 9 P D12 P D13 P C12 P C13 PA PA PA PA PA PA PA General-purpose /O port A PA PA PA PAA PAB PAC PAD Document Number: Rev.*C Page 36 of 182

37 Pin No. Module Pin Name Function LQFP176 LQFP120 Ex-LQFP120 LQFP120 (S6E2D55GJ A) FBGA161 GPO PB PB PB PB PB PB PB General-purpose /O port B PB PB PB PBA PBB PBC PBD PC PC PC PC PC PC PC General-purpose /O port C PC PC PC PCA PCB PCC PCD PD PD PD PD PD PD PD General-purpose /O port D PD PD PD PDA PDB PDC PDD Document Number: Rev.*C Page 37 of 182

38 Pin No. Module Pin Name Function LQFP176 LQFP120 Ex-LQFP120 LQFP120 (S6E2D55GJ A) FBGA161 GPO Multifunction serial 0 Multifunction serial 1 Multifunction serial 2 Multifunction serial 3 PE M12 PE2 General-purpose /O port E N11 PE N12 SN0_ L4 Multi-function serial interface ch.0 pin SN0_ E12 SOT0_0 (SDA0_0) SOT0_1 (SDA0_1) SCK0_0 (SCL0_0) SCK0_1 (SCL0_1) Multi-function serial interface ch.0 output pin. This pin operates as SOT0 when it is used in a UART/CSO/LN (operation modes 0 to 3) and as SDA0 when it is used in an 2 C (operation mode 4). Multi-function serial interface ch.0 clock /O pin. This pin operates as SCK0 when it is used in a CSO (operation mode 2) and as SCL0 when it is used in an 2 C (operation mode 4) M E K D10 SN1_ K11 Multi-function serial interface ch.1 pin SN1_ D11 SOT1_0 (SDA1_0) SOT1_1 (SDA1_1) SCK1_0 (SCL1_0) SCK1_1 (SCL1_1) Multi-function serial interface ch.1 output pin. This pin operates as SOT1 when it is used in a UART/CSO/LN(operation modes 0 to 3) and as SDA1 when it is used in an 2 C (operation mode 4). Multi-function serial interface ch.1 clock /O pin. This pin operates as SCK1 when it is used in a CSO (operation mode 2) and as SCL1 when it is used in an 2 C (operation mode 4) J D H D13 SN2_ H11 Multi-function serial interface ch.2 pin SN2_ C9 SOT2_0 (SDA2_0) SOT2_1 (SDA2_1) SCK2_0 (SCL2_0) SCK2_1 (SCL2_1) Multi-function serial interface ch.2 output pin. This pin operates as SOT2 when it is used in a UART/CSO/LN (operation mode 0 to 3) and as SDA2 when it is used in an 2 C (operation mode 4). Multi-function serial interface ch.2 clock /O Pin. This pin operates as SCK2 when it is used in a CSO (operation mode 2) and as SCL2 when it is used in an 2 C (operation mode 4) H B H A9 SN3_ G10 Multi-function serial interface ch.3 pin SN3_ A6 SOT3_0 (SDA3_0) SOT3_1 (SDA3_1) SCK3_0 (SCL3_0) SCK3_1 (SCL3_1) Multi-function serial interface ch.3 output pin. This pin operates as SOT3 when it is used in a UART/CSO/LN (operation modes 0 to 3) and as SDA3 when it is used in an 2 C (operation mode 4). Multi-function serial interface ch.3 clock /O pin. This pin operates as SCK3 when it is used in a CSO (operation mode 2) and as SCL3 when it is used in an 2 C (operation mode 4) G B G C6 Document Number: Rev.*C Page 38 of 182

39 Pin No. Module Pin Name Function LQFP176 LQFP120 Ex-LQFP120 LQFP120 (S6E2D55GJ A) FBGA161 Multifunction serial 4 Multifunction serial 5 Multifunction serial 6 SN4_0 Multi-function serial interface ch.4 pin B2 SOT4_0 (SDA4_0) SCK4_0 (SCL4_0) Multi-function serial interface ch.4 output pin. This pin operates as SOT4 when it is used in a UART/CSO/LN (operation modes 0 to 3) and as SDA4 when it is used in an 2 C (operation mode 4). Multi-function serial interface ch.4 clock /O pin. This pin operates as SCK4 when it is used in a CSO (operation mode 2) and as SCL4 when it is used in an 2 C (operation mode 4) B B4 CTS4_0 Multi-function serial interface ch.4 CTS pin B5 RTS4_0 Multi-function serial interface ch.4 RTS output pin C4 SN5_ G13 Multi-function serial interface ch.5 pin SN5_ C8 SOT5_0 (SDA5_0) SOT5_1 (SDA5_1) SCK5_0 (SCL5_0) SCK5_1 (SCL5_1) Multi-function serial interface ch.5 output pin. This pin operates as SOT5 when it is used in a UART/CSO/LN (operation modes 0 to 3) and as SDA5 when it is used in an 2 C (operation mode 4). Multi-function serial interface ch.5 clock /O pin. This pin operates as SCK5 when it is used in a CSO (operation mode 2) and as SCL5 when it is used in an 2 C (operation mode 4) F B F A8 SN6_ E3 Multi-function serial interface ch.6 pin SN6_ F13 SOT6_0 (SDA6_0) SOT6_1 (SDA6_1) SCK6_0 (SCL6_0) SCK6_1 (SCL6_1) Multi-function serial interface ch.6 output pin. This pin operates as SOT6 when it is used in a UART/CSO/LN (operation modes 0 to 3) and as SDA6 when it is used in an 2 C (operation mode 4). Multi-function serial interface ch.6 clock /O pin. This pin operates as SCK6 when it is used in a CSO (operation mode 2) and as SCL6 when it is used in an 2 C (operation mode 4) E E E E11 SCS60_0 Multi-function serial interface ch.6 chip select F4 SCS60_1 /output pin F12 Document Number: Rev.*C Page 39 of 182

40 Pin No. Module Pin Name Function LQFP176 LQFP120 Ex-LQFP120 LQFP120 (S6E2D55GJ A) FBGA161 Multifunction serial 7 Multi-function Timer 0 SN7_0 Multi-function serial interface ch.7 pin D3 SOT7_0 (SDA7_0) SCK7_0 (SCL7_0) SCS70_0 Multi-function serial interface ch.7 output pin. This pin operates as SOT7 when it is used in a UART/CSO/LN (operation modes 0 to 3) and as SDA7 when it is used in an 2 C (operation mode 4). Multi-function serial interface ch.7 clock /O pin. This pin operates as SCK7 when it is used in a CSO (operation mode 2) and as SCL7 when it is used in an 2 C (operation mode 4). Multi-function serial interface ch.7 chip select 0 /output pin D D C2 DTT0X_0 nput signal controlling wave form generator F1 DTT0X_1 outputs RTO00 to RTO05 of Multi-function timer H12 FRCK0_ E2 16-bit free-run timer ch.0 external clock pin FRCK0_ H11 C00_ F2 C00_ H13 C01_ F3 C01_1 16-bit capture pin of Multi-function timer G10 0. C02_0 Cxx describes channel number F4 C02_ G11 C03_ E1 C03_ G12 RTO00_0 (PPG00_0) RTO00_1 (PPG00_1) RTO01_0 (PPG00_0) RTO01_1 (PPG00_1) RTO02_0 (PPG02_0) RTO02_1 (PPG02_1) RTO03_0 (PPG02_0) RTO03_1 (PPG02_1) Wave form generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output modes. Wave form generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output modes. Wave form generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output modes. Wave form generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output modes C G C F D F D F12 Document Number: Rev.*C Page 40 of 182

41 Pin No. Module Pin Name Function LQFP176 LQFP120 Ex-LQFP120 LQFP120 (S6E2D55GJ A) FBGA161 Multi-function Timer 0 Quadrature Position/ Revolution Counter 0 Real-time clock USB0 Low-Power Consumption Mode VBAT RTO04_0 (PPG04_0) RTO04_1 (PPG04_1) RTO05_0 (PPG04_0) RTO05_1 (PPG04_1) Wave form generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output modes. Wave form generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output modes D F D E10 AN0_ K11 AN0_1 QPRC ch.0 AN pin C3 AN0_ G13 BN0_ J11 BN0_1 QPRC ch.0 BN pin C2 BN0_ F10 ZN0_ H10 ZN0_1 QPRC ch.0 ZN pin D3 ZN0_ F11 RTCCO_ B3 0.5 seconds pulse output pin of Real-time clock RTCCO_ M5 SUBOUT_ B3 Sub clock output pin SUBOUT_ M5 UDM0 USB ch.0 device/host D pin A3 UDP0 USB ch.0 device/host D + pin A2 UHCONX0 USB ch.0 external pull-up control pin B3 WKUP0 Deep standby mode return signal pin M2 WKUP1 Deep standby mode return signal pin K7 WKUP2 Deep standby mode return signal pin B7 WKUP3 Deep standby mode return signal pin B2 VREGCTL On-board regulator control pin L11 VWAKEUP The return signal pin from a hibernation L12 Document Number: Rev.*C Page 41 of 182

42 Pin No. Module Pin Name Function LQFP176 LQFP120 Ex-LQFP120 LQFP120 (S6E2D55GJ A) FBGA161 2 S 0 2 S 1 GDC High-Speed Quad SP GDC HyperBus /F 2SMCLK0_0 2 S ch.0 external clock pin C3 2SDO0_0 2 S ch.0 serial transition data output pin C2 2SWS0_0 2 S ch.0 frame synchronization signal pin D3 2SD0_0 2 S ch.0 serial received data pin D2 2SCK0_0 2 S ch.0 bit clock pin D1 2SMCLK1_0 2 S ch.1 external clock pin M3 2SDO1_0 2 S ch.1 serial transition data output pin L4 2SWS1_0 2 S ch.1 frame synchronization signal pin M4 2SD1_0 2 S ch.1 serial received data pin K5 2SCK1_0 2 S ch.1 bit clock pin L5 GE_SPCK SP clock output pin J1 GE_SPDQ K1 GE_SPDQ J2 SP data / output pin GE_SPDQ J3 GE_SPDQ H2 GE_SPCSX0 SP chip select output pin H3 GE_HBCK HB clock output pin J1 GE_HBDQ H2 GE_HBDQ H3 GE_HBDQ J2 GE_HBDQ J3 HB data / output pin GE_HBDQ K2 GE_HBDQ K3 GE_HBDQ L2 GE_HBDQ L3 GE_HBCSX K1 HB chip select output pin GE_HBCSX E4 GE_HBRWDS HB RWDS / output pin G2 GE_HBRESETX HB hardware reset output pin F3 GE_HBNTX HB interrupt pin F2 GE_HBRSTOX HB reset pin F1 GE_HBWPX HB write protect output pin G3 Document Number: Rev.*C Page 42 of 182

43 Pin No. Module Pin Name Function LQFP176 LQFP120 Ex-LQFP120 LQFP120 (S6E2D55GJ A) FBGA161 GDC Panel PNL_DCLK GDC clock output pin K8 PNL_DEN GDC data enable output pin (blanking signal) L8 PNL_PWE GDC power enable control output pin L7 PNL_LE GDC line end output pin K9 PNL_LH_SYNC GDC horizontal synchronization output pin L9 PNL_FV_SYNC GDC vertical synchronization output pin L10 PNL_PD C4 PNL_PD B5 PNL_PD C5 PNL_PD A6 PNL_PD B6 PNL_PD C6 PNL_PD B7 PNL_PD C7 PNL_PD A8 PNL_PD B8 PNL_PD C8 PNL_PD A9 GDC panel data output pin PNL_PD B9 PNL_PD C9 PNL_PD D9 PNL_PD C10 PNL_PD C13 PNL_PD C12 PNL_PD D13 PNL_PD D12 PNL_PD D11 PNL_PD D10 PNL_PD E13 PNL_PD E12 PNL_TSG L9 PNL_TSG L10 PNL_TSG L8 PNL_TSG3 GDC timing generator for panel control K9 PNL_TSG L7 PNL_TSG5 PNL_TSG signals are customized synchronization C12 signals for direct interfacing to the column and row PNL_TSG6 drivers of most panel types D13 PNL_TSG7 For more information, refer to Peripheral Manual D12 PNL_TSG8 (GDC Core part) D11 PNL_TSG D10 PNL_TSG E13 PNL_TSG E12 Document Number: Rev.*C Page 43 of 182

44 Pin No. Module Pin Name Function LQFP176 LQFP120 Ex-LQFP120 LQFP120 (S6E2D55GJ A) FBGA161 GDC SDRAM-F (176 pin only) GE_SDA GE_SDA GE_SDA GE_SDA GE_SDA GE_SDA SDRAM-F address output pin GE_SDA GE_SDA GE_SDA GE_SDA GE_SDA GE_SDA GE_SDBA SDRAM-F bank address output pin GE_SDBA GE_SDCASX SDRAM-F column active output pin GE_SDRASX SDRAM-F row active output pin GE_SDWEX SDRAM-F write enable output pin GE_SDCKE SDRAM-F clock enable output pin GE_SDCLK SDRAM-F clock output pin GE_SDCSX SDRAM-F chip select output pin GE_SDDQ GE_SDDQ GE_SDDQ GE_SDDQ GE_SDDQ GE_SDDQ GE_SDDQ GE_SDDQ GE_SDDQ GE_SDDQ GE_SDDQ GE_SDDQ SDRAM-F data / output pin GE_SDDQ GE_SDDQ GE_SDDQ GE_SDDQ GE_SDDQ GE_SDDQ GE_SDDQ GE_SDDQ GE_SDDQ GE_SDDQ GE_SDDQ GE_SDDQ Document Number: Rev.*C Page 44 of 182

45 Pin No. Module Pin Name Function LQFP176 LQFP120 Ex-LQFP120 LQFP120 (S6E2D55GJ A) FBGA161 GDC SDRAM-F (176 pin only) Reset GE_SDDQ GE_SDDQ GE_SDDQ GE_SDDQ SDRAM-F data / output pin GE_SDDQ GE_SDDQ GE_SDDQ GE_SDDQ GE_SDDQM GE_SDDQM SDRAM-F / output mask pin GE_SDDQM GE_SDDQM NTX External Reset nput pin. A reset is valid when NTX = L M8 MD1 Mode 1 pin. During serial programming to Flash memory, MD1 = L must be M12 Mode Mode 0 pin. MD0 During normal operation, MD0 = L must be. During serial programming to Flash memory, MD M11 = H must be C G L1 Power VCC Power supply Pin N L A A H M N3 GND VSS GND Pin M B A B1 X0 Main clock (oscillation) pin N11 X0A Sub clock (oscillation) pin N7 Clock X1 Main clock (oscillation) /O pin N12 X1A Sub clock (oscillation) /O pin N9 CROUT_ L4 Built-in High-speed CR-osc clock output port CROUT_ N5 Analog Power AVCC A/D converter analog power supply pin K13 AVRL A/D converter analog reference voltage pin J13 AVRH A/D converter analog reference voltage pin J12 Document Number: Rev.*C Page 45 of 182

46 Pin No. Module Pin Name Function LQFP176 LQFP120 Ex-LQFP120 LQFP120 (S6E2D55GJ A) FBGA161 VBAT Power Analog GND VBAT VBAT power supply pin. Backup power supply (battery etc.) and system power supply M9 AVSS A/D converter GND pin K12 C Pin C Power supply stabilization capacity pin N2 Note: While this device contains a Test Access Port (TAP) based on the EEE JTAG standard, it is not fully compliant to all requirements of that standard. This device may contain a 32-bit device D that is the same as the 32-bit device D in other devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP controller. Document Number: Rev.*C Page 46 of 182

47 5. /O Circuit Type Type Circuit Remarks Pull-up resistor P-ch P-ch Digital output X1 N-ch Digital output R t is possible to select the main Pull-up resistor control oscillation / GPO function A Feedback resistor Digital Standby mode control Clock When the main oscillation is selected. Oscillation feedback resistor : Approximately 1 MΩ With Standby mode control When the GPO is selected. CMOS level output. Standby mode control CMOS level hysteresis With pull-up resistor control Digital With standby mode control Pull-up resistor R Pull-up resistor Standby mode control : Approximately 80 kω OH = -2 ma, OL = 2 ma X0 P-ch P-ch Digital output N-ch Digital output Pull-up resistor control B Pull-up resistor CMOS level hysteresis Pull-up resistor : Approximately 80 kω Digital Document Number: Rev.*C Page 47 of 182

48 Type Circuit Remarks C N-ch Digital Digital output Open drain output CMOS level hysteresis D R P-ch P-ch N-ch Digital output Digital output Pull-up resistor control CMOS level output CMOS level hysteresis With pull-up resistor control With standby mode control Pull-up resistor : Approximately 80 kω OH = -4 ma, OL = 4 ma When this pin is used as an 2 C pin, the digital output P-ch transistor is always off. Digital Standby mode control E R P-ch P-ch N-ch Digital output Digital output Pull-up resistor control CMOS level output CMOS level hysteresis With pull-up resistor control With standby mode control Pull-up resistor : Approximately 80 kω OH = -2 ma, OL = 2 ma When this pin is used as an 2 C pin, the digital output P-ch transistor is always off. Digital Standby mode control Document Number: Rev.*C Page 48 of 182

49 Type Circuit Remarks P-ch P-ch Digital output CMOS level output CMOS level hysteresis With control F R N-ch Digital output Pull-up resistor control Digital Standby mode control Analog With pull-up resistor control With standby mode control Pull-up resistor : Approximately 80 kω OH = -2 ma, OL = 2 ma When this pin is used as an 2 C pin, the digital output P-ch transistor is always off. Analog nput control G R P-ch P-ch N-ch Digital output Digital output CMOS level output CMOS level hysteresis With pull-up resistor control With standby mode control Pull-up resistor : Approximately 80 kω OH = -8 ma, OL = 8 ma When this pin is used as an 2 C pin, the digital output P-ch transistor is always off. Pull-up resistor control Digital Standby mode control Document Number: Rev.*C Page 49 of 182

50 Type Circuit Remarks GPO Digital output GPO Digital /output direction GPO Digital GPO Digital circuit control UDP/Pxx UDP output USB Full-speed/Low-speed control t is possible to select the USB /O / GPO function. H UDM/Pxx Differential UDP Differential USB/GPO select UDM When the USB /O is selected. Full-speed, Low-speed control When the GPO is selected. CMOS level output CMOS level hysteresis UDM output With standby mode control USB Digital /output direction OH = ma, OL = 18.5 ma GPO Digital output GPO Digital /output direction GPO Digital GPO Digital circuit control P-ch P-ch Digital output CMOS level output CMOS level hysteresis 5 V tolerant With pull-up resistor control R N-ch Digital output With standby mode control Pull-up resistor : Approximately 80 kω OH = -2 ma, OL = 2 ma Available to control of PZR registers. Pull-up resistor control Digital Standby mode control J Mode CMOS level hysteresis Document Number: Rev.*C Page 50 of 182

51 Type Circuit Remarks K R P-ch P-ch N-ch Digital output Digital output CMOS level output CMOS level hysteresis With pull-up resistor control With standby mode control Pull-up resistor : Approximately 33 kω OH = -11 ma, OL = 11 ma Pull-up resistor control Digital Standby mode control P-ch P-ch Digital output CMOS level output CMOS level hysteresis TTL level hysteresis L R N-ch Digital output Pull-up resistor control Digital (TTL) Digital (CMOS) Standby mode control :SDRAM-F Data nput only With pull-up resistor control With standby mode control Pull-up resistor : Approximately 33 kω OH = -11 ma, OL = 11 ma Document Number: Rev.*C Page 51 of 182

52 Type Circuit Remarks N P-ch R N-ch P-ch N-ch Pull-up resistor control Digital output Digital output Fast mode control CMOS level output CMOS level hysteresis 5 V tolerant With pull-up resistor control With standby mode control Pull-up resistor : Approximately 80 kω OH = -3 ma, OL = 3 ma (GPO) OL = 20 ma (Fast Mode Plus) Available to control of PZR registers. When this pin is used as an 2 C pin, the digital output P-ch transistor is always off Digital Standby mode control O P-ch P-ch N-ch Pull-up resistor control Digital output Digital output CMOS level output CMOS level hysteresis 5 V tolerant With pull-up resistor control Pull-up resistor : Approximately 80 kω OH = -2 ma, OL = 2 ma Available to control of PZR registers. Please refer to the "VBAT domain" setting of the O in the Peripheral Manual main part ( )". R Digital P X0A R Digital Sub OSC/GPO select OSC CMOS level hysteresis Please refer to the "VBAT domain" setting of the O in the Peripheral Manual main part ( )". Document Number: Rev.*C Page 52 of 182

53 Type Circuit Remarks X1A R Digital t is possible to select the sub oscillation / GPO function Q RX Sub OSC/ GPO select OSC When the sub oscillation is selected. Oscillation feedback resistor : Approximately 12 MΩ When the GPO is selected. CMOS level hysteresis Sub OSC enable Please refer to the "VBAT domain" setting of the O in the Peripheral Manual main Clock part ( )". P-ch P-ch Digital output CMOS level output CMOS level hysteresis N-ch Digital output With control Analog R With pull-up resistor control With standby mode control R Pull-up resistor control Digital Pull-up resistor : Approximately 80 kω OH = -4 ma, OL = 4 ma Standby mode control Analog nput control Document Number: Rev.*C Page 53 of 182

54 6. Handling Precautions Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices. 6.1 Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices. Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and /output functions. 1. Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. 2. Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. 3. Handling of Unused nput Pins Unconnected pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin. Document Number: Rev.*C Page 54 of 182

55 Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred ma to flow continuously at the power supply pin. This condition is called latch-up. CAUTON: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: 1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. 2. Be sure that abnormal current flows do not occur during the power-on sequence. Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Precautions Related to Usage of Devices Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTON: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 6.2 Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. n either case, for heat resistance during soldering, you should only mount under Cypress's recommended conditions. For detailed information about mount conditions, contact your sales representative. Lead nsertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. n this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress recommended mounting conditions. f socket mounting is used, differences in surface treatment of the socket contacts and C lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and C leads be verified before mounting. Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended conditions. Document Number: Rev.*C Page 55 of 182

56 Lead-Free Packaging CAUTON: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: 1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. 2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5 C and 30 C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. 3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. 4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust. Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended conditions for baking. Condition: 125 C/24 h Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: 1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. 2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. 3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. 4. Ground all fixtures and instruments, or protect with anti-static measures. 5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies. Document Number: Rev.*C Page 56 of 182

57 6.3 Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: 1. Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. f high humidity levels are anticipated, consider anti-humidity processing. 2. Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. n such cases, use anti-static measures or processing to prevent discharges. 3. Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. f you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. 4. Radiation, ncluding Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. 5. Smoke, Flame CAUTON: Plastic molded devices are flammable, and therefore should not be used near combustible substances. f devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Cypress products in other special environmental conditions should consult with sales representatives. Document Number: Rev.*C Page 57 of 182

58 7. Handling Devices Power Supply Pins n products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with each POWER pins and GND pins of this device at low impedance. t is also advisable that a ceramic capacitor of approximately 0.1 µf be connected as a bypass capacitor between VCC and VSS, between AVCC and AVSS and between AVRH and AVRL near this device. A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed operating range of the VCC power supply voltage. As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient fluctuation rate does not exceed 0.1 V/μs at a momentary fluctuation such as switching the power supply. Crystal Oscillator Circuit Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1, X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as possible. t is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by ground plane as this is expected to produce stable operation. Evaluate oscillation of your using crystal oscillator by your mount board. Sub Crystal Oscillator This series sub oscillator circuit is low gain to keep the low current consumption. The crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation. Surface mount type Size: Load capacitance: Load capacitance: Lead type Load capacitance: Load capacitance: More than 3.2 mm 1.5 mm Approximately 6 pf to 7 pf When the Standard setting (CCS/CCB= ) Approximately 4 pf to 7 pf When the low power setting (CCS/CCB= ) Approximately 6 pf to 7 pf When the Standard setting (CCS/CCB= ) Approximately 4 pf to 7 pf When the low power setting (CCS/CCB= ) Document Number: Rev.*C Page 58 of 182

59 Using an External Clock When using an external clock as an of the main clock, set X0/X1 to the external clock, and the clock to X0. X1(PE3) can be used as a general-purpose /O port. Similarly, when using an external clock as an of the sub clock, set X0A/X1A to the external clock, and the clock to X0A. X1A (P47) can be used as a general-purpose /O port. Example of Using an External Clock Device Can be used as general-purpose /O ports. X0(X0A) X1(PE3), X1A (P47) Set as External clock Handling when Using Multi-Function Serial Pin as 2 C Pin f it is using the multi-function serial pin as 2 C pins, P-ch transistor of digital output is always disabled. However, 2 C pins need to keep the electrical characteristic like other pins and not to connect to the external 2 C bus system with power OFF. C Pin This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. A smoothing capacitor of about 4.7 μf would be recommended for this series. Device C VSS CS GND Mode Pins (MD0) Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. t is because of preventing the device erroneously switching to test mode due to noise. Document Number: Rev.*C Page 59 of 182

60 Notes on Power-on Turn power on/off in the following order or at the same time. The device operates normally after all power on. VBAT only Power-on is possible when VBAT and VCC turns Power-on and Hibernation control is setting and then turns Power-off. About Hibernation control, see Chapter 7-3: VBAT Domain(B) in FM4 Family Peripheral Manual Main Part ( ). Turning on : VBAT VCC AVCC AVRH Turning off : AVRH AVCC VCC VBAT Serial Communication There is a possibility to receive wrong data due to the noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. f an error is detected, retransmit the data. Differences in Features among the Products with Different Memory Sizes and between Flash Products and MASK Products The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between Flash products and MASK products are different because chip layout and memory structures are different. f you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics. Pull-Up Function of 5V Tolerant /O Please do not the signal more than VCC voltage at the time of Pull-Up function use of 5V tolerant /O. Pin Doubled as Debug Function Please use as output only regarding the pin doubled as TDO/TMS/TD/TCK/TRSTX, SWO/SWDO/SWCLK. Don't use as. S6E2D55GJA The following must correspond to S6E2D55GJA. 1. Terminal DNU0 / 1 is short-circuited, and the pull-up of about 10kΩ is done. R Device DNU0 DNU1 2. Please do not connect the open end NC terminal. 3. Please have the following port settings. PFR7: PDOR7: DDR7: bit6=0, bit10=0 bit6=0, bit10=0 bit6=1, bit10=1 See Chapter 12: /O Port in FM4 Family Peripheral Manual Main Part ( ) for the details. 4. Please connect a bypass capacitor as close as possible to GND on the board and VCC in pin number 22. Document Number: Rev.*C Page 60 of 182

61 AHB-APB Bridge:APB2(Max:80MHz) AHB-APB Bridge:APB1(Max:160MHz) AHB-AHB Bridge (Slave) AHB-AHB Bridge (Master) AHB-AHB Bridge (Slave) AHB-APB Bridge:APB0(Max:80MHz) Multi-layer AHB (Max:160MHz) S6E2D5 Series 8. Block Diagram S6E2D55J0A / S6E2D55G0A / S6E2D55GJA TRSTX,TCK, TD,TMS TDO SWJ-DP ETM* SRAM0 32Kbytes TRACEDx, TRACECLK TPU* ROM Table Cortex-M4 FPU MPU NVC Dual-Timer D Sys MainFlash /F Trace Buffer (16Kbytes) Security SRAM2 4Kbytes MainFlash 384Kbytes NTX Watchdog Timer (Software) Clock Reset Generator Watchdog Timer (Hardw are) CSV USB2.0 (Host/Func) DMAC 8ch. PHY UDP0,UDM0 UHCONX0 DSTC 1unit(128ch.) CLK X0 X1 X0A X1A CROUT AVCC,AVSS, AVRH,AVRL ANxx ADTG Main OSC VBAT Domain Sub OSC Source Clock PLL 12bit A/D Converter 24ch. Unit 0 Unit 1 CR 100kHz CR 4MHz CAN PRG-CRC Accelerator 2 S 2units GPO PN-Function-Ctrl MODE-Cntl. TX2,RX2 2SMCLKx, 2SWSx,2SCKx 2SDx 2SDOx P0x, P1x, : PFx MD0,MD1 TOAx TOBx AN0 BN0 ZN0 Base Timer 16bit 16ch./ 32bit 8ch QPRC 1ch. VRAM 512Kbytes External Bus /F MADx MADATAx MCSXx,MDQMx, MOEX,MWEX, MALE,MRDY, MNALE,MNCLE, MNWEX,MNREX, MCLKOUT,MSDWEX, MSDCLK,MSDCKE, MRASX,MCASX C0x FRCK0 DTT0X RTO0x A/D Activation Compare 6ch. 16bit nput Capture 4ch. 16bit Free-run Timer 3ch. 16bit Output Compare 6ch. Waveform Generator 3ch. 16bit PPG 3ch. Multi-function Timer 1unit Graphic Engine core CAN Prescaler GDC Clock Cntl. PLL GDC unit SDRAM /F HyperBus /F HighSpeed Quad SP VFLASH 2Mbytes Panel /F PNL_DCLK, PNL_DEN, PNL_PWE, PNL_LE, PNL_LH_SYNC, PNL_FV_SYNC, PNL_PD[23:0], PNL_TSG[11:0] SDRAM /F GE_SDCLK,GE_SDCKE,GE_SDCSX, GE_SDCASX,GE_SDRASX,GE_SDWEX, GE_SDDQM[3:0],GE_SDBA[1:0], GE_SDA[11:0],GE_SDDQ[31:0] HyperBus /F GE_HBCK, GE_HBDQ[7:0], GE_HBCSX0/1, GE_HBRWDS, GE_HBRESETX, GE_HBNTX, GE_HBRSTOX, GE_HBWPX HighSpeed Quad SP GE_SPCK, GE_SPDQ[3:0], GE_SPCSX0 *S6E2D55GJA Unavailable VBAT VWAKEUP VREGCTL RTCCO,SUBOUT VBAT Domain Real-Time Clock Port Cntl. Peripheral Clock Gating Low -speed CR Prescaler USB Clock Cntl. 2 S Clock Cntl. LVD Cntl. PLL PLL Deep Standby Cntl. *S6E2D55GJA Only Power-On Reset LVD Regulator C WKUPx RQ-Monitor CRC Accelerator Watch Counter External nterrupt Controller 16ch + NM Multi-function Serial /F 8ch. (w ith FFO ch.0 to ch.7) HW flow control(ch.4) NTxx NMX SCKx SNx SOTx CTS4 RTS4 SCSx Document Number: Rev.*C Page 61 of 182

62 9. Memory Size See Memory size in 1. Product Lineup to confirm the memory size. 10. Memory Map Memory Map GDC Area 0xDFFF_FFFF 0xD0A0_6000 0xD0A0_5000 Reserved GDC_HBF 0xD0A0_4000 GDC_HSQSP 0xD0A0_3000 GDC_SDRAMF 0xFFFF_FFFF 0xD0A0_1000 Reserved Reserved 0xD0A0_0000 GDC 0xE010_0000 0xD008_0000 Reserved 0xD000_0000 VRAM Cortex-M4 Private Memory Area for Peripherals 0xE000_0000 0xC000_0000 GDC_HSQSP or GDC_HBF 0xB000_0000 External SDRAM GDC 0xB000_0000 Peripherals Area 0x41FF_FFFF Reserved 0x8000_0000 0x4008_1000 0x4008_0000 Reserved Programable-CRC External Device Area SDRAM 0x4007_0000 CAN-FD 256Mbytes 0x4006_F000 GPO 0x7000_0000 0x4006_E000 Reserved SRAM 0x4006_D000 Reserved /NOR Flash Memory 0x4006_C000 2S /NAND Flash Memory 0x4006_2000 Reserved 0x6000_ Mbytes 0x4006_1000 DSTC 0x4006_0000 DMAC Reserved 0x4005_0000 Reserved 0x4400_0000 0x4004_0000 USB ch.0 32Mbytes 0x4003_F000 EXT-bus /F 0x4200_0000 Bit band alias 0x4003_E000 Reserved 0x4003_D100 GDC Prescaler Peripherals 0x4000_0000 0x4003_D000 2S Prescaler 0x4003_C800 Reserved Reserved 0x2400_0000 0x4003_C100 Peripheral Clock Gating 32Mbytes 0x4003_C000 LowSpeed CR Prescaler 0x2200_0000 Bit band alias 0x4003_B000 RTC/Port Ctrl 0x2004_1000 Reserved 0x4003_A000 Watch Counter SRAM2 0x4003_9000 CRC 0x2004_0000 4Kbytes 0x4003_8000 MFS 0x2000_0000 Reserved 0x4003_7000 CAN Prescaler SRAM0 0x4003_6000 USB Clock Ctrl 0x1FFF_ Kbytes 0x4003_5000 LVD/DS mode 0x4003_2000 Reserved Reserved 0x4003_1000 nt-req.read 0x4003_0000 EXT 0x0040_4000 0x4002_F000 Reserved 0x0040_2000 CR trimming 0x4002_E000 CR Trim 0x0040_0000 Security 0x4002_8000 Reserved 0x4002_7000 A/DC Reserved 0x4002_6000 QPRC 0x4002_5000 Base Timer 0x0006_0000 0x4002_4000 PPG 0x4002_1000 Reserved 0x4002_0000 MFT Unit0 Flash 0x4001_6000 Reserved 384Kbytes 0x4001_5000 Dual Timer 0x4001_3000 Reserved 0x0000_0000 0x4001_2000 SW WDT 0x4001_1000 HW WDT 0x4001_0000 Clock/Reset 0x4000_1000 Reserved 0x4000_0000 Flash /F Document Number: Rev.*C Page 62 of 182

63 Peripheral Address Map Start address End address Bus Peripherals 0x4000_0000 0x4000_0FFF MainFlash /F register AHB 0x4000_1000 0x4000_FFFF Reserved 0x4001_0000 0x4001_0FFF Clock/Reset Control 0x4001_1000 0x4001_1FFF Hardw are Watchdog timer 0x4001_2000 0x4001_2FFF Softw are Watchdog timer APB0 0x4001_3000 0x4001_4FFF Reserved 0x4001_5000 0x4001_5FFF Dual-Timer 0x4001_6000 0x4001_FFFF Reserved 0x4002_0000 0x4002_0FFF Multi-function timer unit0 0x4002_1000 0x4002_3FFF Reserved 0x4002_4000 0x4002_4FFF PPG 0x4002_5000 0x4002_5FFF Base Timer 0x4002_6000 0x4002_6FFF APB1 Quadrature Position/Revolution Counter 0x4002_7000 0x4002_7FFF A/D Converter 0x4002_8000 0x4002_DFFF Reserved 0x4002_E000 0x4002_EFFF nternal CR trimming 0x4002_F000 0x4002_FFFF Reserved 0x4003_0000 0x4003_0FFF External nterrupt Controller 0x4003_1000 0x4003_1FFF nterrupt Request Batch-Read Function 0x4003_2000 0x4003_4FFF Reserved 0x4003_5000 0x4003_57FF Low Voltage Detector 0x4003_5800 0x4003_5FFF Deep standby mode Controller 0x4003_6000 0x4003_6FFF USB clock generator 0x4003_7000 0x4003_7FFF CAN prescaler 0x4003_8000 0x4003_8FFF Multi-function serial nterface 0x4003_9000 0x4003_9FFF CRC APB2 0x4003_A000 0x4003_AFFF Watch Counter 0x4003_B000 0x4003_BFFF RTC/PortCtrl 0x4003_C000 0x4003_C0FF Low -speed CR Prescaler 0x4003_C100 0x4003_C7FF Peripheral Clock Gating 0x4003_C800 0x4003_CFFF Reserved 0x4003_D000 0x4003_D0FF 2 S Prescaler 0x4003_D100 0x4003_DFFF GDC Prescaler 0x4003_E000 0x4003_EFFF Reserved 0x4003_F000 0x4003_FFFF External Memory interface 0x4004_0000 0x4004_FFFF USB ch.0 0x4005_0000 0x4005_FFFF Reserved 0x4006_0000 0x4006_0FFF DMAC register 0x4006_1000 0x4006_1FFF DSTC register 0x4006_2000 0x4006_BFFF Reserved 0x4006_C000 0x4006_CFFF 2 S AHB 0x4006_D000 0x4006_DFFF Reserved 0x4006_E000 0x4006_EFFF Reserved 0x4006_F000 0x4006_FFFF GPO 0x4007_0000 0x4007_FFFF CAN-FD 0x4008_0000 0x4008_0FFF Programmable-CRC 0x4008_1000 0x41FF_FFFF Reserved 0xB000_0000 0xDFFF_FFFF AHB GDC unit Document Number: Rev.*C Page 63 of 182

64 11. Pin Status in Each CPU State The terms used for pin status have the following meanings. NTX=0 NTX=1 SPL=0 SPL=1 This is the period when the NTX pin is the L level. This is the period when the NTX pin is the H level. This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 0. This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 1. nput ndicates that the function can be used. nternal fixed at 0 Hi-Z This is the status that the function cannot be used. nternal is fixed at L. ndicates that the pin drive transistor is disabled and the pin is put in the Hi-Z. Setting disabled ndicates that the setting is disabled. Maintain previous Maintains the that was immediately prior to entering the current mode. f a built-in peripheral function is operating, the output follows the peripheral function. f the pin is being used as a port, that output is maintained. Analog is ndicates that the analog is. Trace output ndicates that the trace function can be used. GPO selected n Deep standby mode, pins switch to the general-purpose /O port. Setting prohibition Prohibition of a setting by specification limitation. Document Number: Rev.*C Page 64 of 182

65 List of Pin Status Pin status Type Function Group Power-on Reset or Low-Voltage Detection State Power Supply Unstable NTX nput State Power Supply Stable Device nternal Reset State Run Mode or Sleep Mode State Power Supply Stable Timer Mode RTC Mode or Stop Mode State Power Supply Stable Deep Standby RTC Mode or Deep Standby Stop Mode State Power Supply Stable Return from Deep Standby Mode State Power Supply Stable A B GPO selected Main crystal oscillator pin/ External main clock selected GPO selected External main clock selected NTX=0 NTX=1 NTX=1 NTX=1 NTX=1 NTX=1 SPL=0 SPL=1 SPL=0 SPL=1 - Setting disabled nput Setting disabled Setting disabled Setting disabled nput Setting disabled Setting disabled Setting disabled nput Setting disabled Setting disabled Maintain previous nput Maintain previous Maintain previous Maintain previous nput Maintain previous Maintain previous Hi-Z / nternal fixed at 0 nput Hi-Z / nternal fixed at 0 Hi-Z / nternal fixed at 0 GPO selected nternal fixed at 0 nput GPO selected nternal fixed at 0 Maintain previous Hi-Z / nternal fixed at 0 nput Hi-Z / nternal fixed at 0 Hi-Z / nternal fixed at 0 GPO selected nput GPO selected Maintain previous Main crystal oscillator output pin Hi-Z / nternal fixed at 0/ or nput enable Hi-Z / nternal fixed at 0 Hi-Z / nternal fixed at 0 Maintain previous / When oscillation stops* 1,Hi-Z / nternal fixed at 0 C NTX pin Pull-up / Pull-up / Pull-up / Pull-up / Pull-up / Pull-up / Pull-up / Pull-up / Pull-up / D Mode pin nput nput nput nput nput nput nput nput nput Document Number: Rev.*C Page 65 of 182

66 Pin status Type Function Group Power-on Reset or Low-Voltage Detection State Power Supply Unstable NTX nput State Power Supply Stable Device nternal Reset State Run Mode or Sleep Mode State Power Supply Stable Timer Mode RTC Mode or Stop Mode State Power Supply Stable Deep Standby RTC Mode or Deep Standby Stop Mode State Power Supply Stable Return from Deep Standby Mode State Power Supply Stable E F G H Mode pin GPO selected NMX selected Resource other than above selected GPO selected JTAG selected GPO selected JTAG selected Resource other than above selected GPO selected Resource selected GPO selected NTX=0 NTX=1 NTX=1 NTX=1 NTX=1 NTX=1 SPL=0 SPL=1 SPL=0 SPL=1 - nput Setting disabled Setting disabled Hi-Z Hi-Z Setting disabled Hi-Z Setting disabled Hi-Z nput Setting disabled Setting disabled Hi-Z / Pull-up / nput Setting disabled Pull-up / nput Setting disabled Hi-Z / nput Setting disabled Setting disabled Hi-Z / Pull-up / nput Setting disabled Pull-up / nput Setting disabled Hi-Z / nput Maintain previous Maintain previous Maintain previous Maintain previous Maintain previous nput Maintain previous Maintain previous Maintain previous Maintain previous Maintain previous nput Hi-Z / Maintain previous Hi-Z / nternal fixed at 0 Maintain previous Hi-Z / nternal fixed at 0 Maintain previous Hi-Z / nternal fixed at 0 Hi-Z / nternal fixed at 0 nput GPO selected WKUP Maintain previous GPO selected nternal fixed at 0 Maintain previous GPO selected nternal fixed at 0 GPO selected nternal fixed at 0 nput Hi-Z / Hi-Z / WKUP Maintain previous Hi-Z / nternal fixed at 0 Maintain previous Hi-Z / nternal fixed at 0 Hi-Z / nternal fixed at 0 nput GPO selected Maintain previous GPO selected Maintain previous GPO selected Maintain previous GPO selected GPO selected Document Number: Rev.*C Page 66 of 182

67 Pin status Type Function Group Power-on Reset or Low-Voltage Detection State Power Supply Unstable NTX nput State Power Supply Stable Device nternal Reset State Run Mode or Sleep Mode State Power Supply Stable Timer Mode RTC Mode or Stop Mode State Power Supply Stable Deep Standby RTC Mode or Deep Standby Stop Mode State Power Supply Stable Return from Deep Standby Mode State Power Supply Stable K L External interrupt selected Resource other than above selected GPO selected Analog selected Resource other than above selected GPO selected NTX=0 NTX=1 NTX=1 NTX=1 NTX=1 NTX=1 SPL=0 SPL=1 SPL=0 SPL=1 - Setting disabled Hi-Z Hi-Z Setting disabled Setting disabled Hi-Z / Hi-Z / nternal fixed at 0 / Analog Setting disabled Setting disabled Hi-Z / Hi-Z / nternal fixed at 0 / Analog Setting disabled Maintain previous Hi-Z / nternal fixed at 0 / Analog Maintain previous Maintain previous Hi-Z / nternal fixed at 0 / Analog Maintain previous Maintain previous Hi-Z / nternal fixed at 0 Hi-Z / nternal fixed at 0 / Analog Hi-Z / nternal fixed at 0 GPO selected nternal fixed at 0 Hi-Z / nternal fixed at 0 / Analog GPO selected nternal fixed at 0 Hi-Z / nternal fixed at 0 Hi-Z / nternal fixed at 0 / Analog Hi-Z / nternal fixed at 0 GPO selected Hi-Z / nternal fixed at 0 / Analog GPO selected Document Number: Rev.*C Page 67 of 182

68 Pin status Type Function Group Power-on Reset or Low-Voltage Detection State Power Supply Unstable NTX nput State Power Supply Stable Device nternal Reset State Run Mode or Sleep Mode State Power Supply Stable Timer Mode RTC Mode or Stop Mode State Power Supply Stable Deep Standby RTC Mode or Deep Standby Stop Mode State Power Supply Stable Return from Deep Standby Mode State Power Supply Stable M N Analog selected External interrupt selected Resource other than above selected GPO selected Analog selected Trace selected Resource other than above selected GPO selected NTX=0 NTX=1 NTX=1 NTX=1 NTX=1 NTX=1 SPL=0 SPL=1 SPL=0 SPL=1 - Hi-Z Setting disabled Hi-Z Setting disabled Hi-Z / nternal fixed at 0 / Analog Setting disabled Hi-Z / nternal fixed at 0 / Analog Setting disabled Hi-Z / nternal fixed at 0 / Analog Setting disabled Hi-Z / nternal fixed at 0 / Analog Setting disabled Hi-Z / nternal fixed at 0 / Analog Maintain previous Hi-Z / nternal fixed at 0 / Analog Maintain previous Hi-Z / nternal fixed at 0 / Analog Maintain previous Hi-Z / nternal fixed at 0 / Analog Maintain previous Hi-Z / nternal fixed at 0 / Analog Maintain previous Hi-Z / nternal fixed at 0 Hi-Z / nternal fixed at 0 / Analog Trace output Hi-Z / nternal fixed at 0 Hi-Z / nternal fixed at 0 / Analog GPO selected nternal fixed at 0 Hi-Z / nternal fixed at 0 / Analog GPO selected nternal fixed at 0 Hi-Z / nternal fixed at 0 / Analog Hi-Z / nternal fixed at 0 Hi-Z / nternal fixed at 0 / Analog Hi-Z / nternal fixed at 0 Hi-Z / nternal fixed at 0 / Analog GPO selected Hi-Z / nternal fixed at 0 / Analog GPO selected Document Number: Rev.*C Page 68 of 182

69 Pin status Type Function Group Power-on Reset or Low-Voltage Detection State Power Supply Unstable NTX nput State Power Supply Stable Device nternal Reset State Run Mode or Sleep Mode State Power Supply Stable Timer Mode RTC Mode or Stop Mode State Power Supply Stable Deep Standby RTC Mode or Deep Standby Stop Mode State Power Supply Stable Return from Deep Standby Mode State Power Supply Stable O P Analog selected Trace selected External interrupt selected Resource other than above selected GPO selected WKUP Resource other than above selected GPO selected NTX=0 NTX=1 NTX=1 NTX=1 NTX=1 NTX=1 SPL=0 SPL=1 SPL=0 SPL=1 - Hi-Z Setting disabled Setting disabled Hi-Z / nternal fixed at 0 / Analog Setting disabled Setting disabled Hi-Z / nternal fixed at 0 / Analog Setting disabled Setting disabled Hi-Z / nternal fixed at 0 / Analog Maintain previous Maintain previous Hi-Z / nternal fixed at 0 / Analog Maintain previous Maintain previous Hi-Z / nternal fixed at 0 / Analog Trace output Maintain previous Hi-Z / nternal fixed at 0 Maintain previous Hi-Z / nternal fixed at 0 Hi-Z / nternal fixed at 0 / Analog GPO selected nternal fixed at 0 WKUP GPO selected nternal fixed at 0 Hi-Z / nternal fixed at 0 / Analog Hi-Z / nternal fixed at 0 Hi-Z / WKUP Hi-Z / nternal fixed at 0 Hi-Z / nternal fixed at 0 / Analog GPO selected GPO selected Document Number: Rev.*C Page 69 of 182

70 Pin status Type Function Group Power-on Reset or Low-Voltage Detection State Power Supply Unstable NTX nput State Power Supply Stable Device nternal Reset State Run Mode or Sleep Mode State Power Supply Stable Timer Mode RTC Mode or Stop Mode State Power Supply Stable Deep Standby RTC Mode or Deep Standby Stop Mode State Power Supply Stable Return from Deep Standby Mode State Power Supply Stable Q WKUP External interrupt selected Resource other than above selected GPO selected GPO selected NTX=0 NTX=1 NTX=1 NTX=1 NTX=1 NTX=1 SPL=0 SPL=1 SPL=0 SPL=1 - Setting disabled Hi-Z Hi-Z Setting disabled Hi-Z / Hi-Z / Setting disabled Hi-Z / Hi-Z / Maintain previous Maintain previous Maintain previous Maintain previous Maintain previous Hi-Z / nternal fixed at 0 Hi-Z / nternal fixed at 0 WKUP GPO selected nternal fixed at 0 GPO selected nternal fixed at 0 Hi-Z / WKUP Hi-Z / nternal fixed at 0 Hi-Z / nternal fixed at 0 WKUP GPO selected GPO selected R USB /O pin Setting disabled Setting disabled Setting disabled Hi-Z at transmission/ nternal fixed at 0 at reception Hi-Z at transmission/ nternal fixed at 0 at reception Hi-Z / Hi-Z / Hi-Z / Hi-Z / *1: Oscillation is stopped at Sub timer mode, low-speed CR timer mode, RTC mode, Stop mode, Deep standby RTC mode, and Deep standby Stop mode. Document Number: Rev.*C Page 70 of 182

71 VBAT Pin Status Type S T U List of VBAT Domain Pin Status Function Group GPO selected Sub crystal oscillator pin / External sub clock selected GPO selected External sub clock selected Sub crystal oscillator output pin Resource selected GPO selected Power-on Reset*1 Power Supply Unstable NTX nput State Device nternal Reset State Power Supply Stable Run Mode or Sleep Mode State Power Supply Stable Timer Mode RTC Mode or Stop Mode State Power Supply Stable Deep Standby RTC Mode or Deep Standby Stop Mode State Power Supply Stable Return from Deep Standby Mode State Power Supply Stable VBAT RTC Mode State Power Supply Stable NTX=0 NTX=1 NTX=1 NTX=1 NTX=1 NTX=1 - - SPL=0 SPL=1 SPL=0 SPL= nternal nternal Setting nput nput nput nput nput nput Setting disabled fixed fixed prohibition - at 0 at 0 nput Setting disabled Setting disabled Hi-Z/ nternal fixed at 0 or Hi-Z nput nternal fixed at 0 Maintain previous Maintain previous Maintain previous nput nternal fixed at 0 Maintain previous Maintain previous Maintain previous *1: When VBAT and VCC power on. nput nput Maintain previous Maintain previous Maintain previous nput nput Maintain previous Maintain previous / When oscillation stops, Hi-Z*2 Maintain previous nput nput Maintain previous Maintain previous / When oscillation stops, Hi-Z*2 Maintain previous nput nput Maintain previous Maintain previous / When oscillation stops, Hi-Z*2 Maintain previous nput nput Maintain previous Maintain previous / When oscillation stops, Hi-Z*2 Maintain previous nput nput Maintain previous Maintain previous Maintain previous Maintain previous Setting prohibition Maintain previous Maintain previous Maintain previous *2: When the SOSCNTL bit in the WTOSCCNT register is 0, Sub crystal oscillator output pin is maintain previous. When the SOSCNTL bit in the WTOSCCNT register is 1, Oscillation is stopped at Stop mode and Deep standby Stop mode Return from VBAT RTC Mode State Power Supply Sable Maintain previous - Maintain previous Maintain previous Maintain previous Document Number: Rev.*C Page 71 of 182

72 12. Electrical Characteristics 12.1 Absolute Maximum Ratings Parameter Symbol Min Rating Max Power supply voltage * 1, * 2 VCC VSS VSS V Power supply voltage (VBAT) * 1, * 3 VBAT VSS VSS V Analog power supply voltage * 1, * 4 AVCC VSS VSS V Analog reference voltage * 1, * 4 AVRH VSS VSS V VCC nput voltage * 1 VSS V ( 4.6 V) V VSS VSS V 5 V tolerant Analog pin voltage * 1 VA VSS AVCC ( 4.6 V) V Output voltage * 1 VO VSS VCC ( 4.6 V) V 10 ma 2 ma type 20 ma 4 ma type L level maximum output current * 5 OL - 20 ma 8 ma type 20 ma 11 ma type 22.4 ma 2 C Fm+ 2 ma 2 ma type 4 ma 4 ma type L level average output current * 6 OLAV - 8 ma 8 ma type 11 ma 11 ma type 20 ma 2 C Fm+ L level total maximum output current OL ma L level total average output current * 7 OLAV - 50 ma - 10 ma 2 ma type H level maximum output current * 5 OH ma 4 ma type - 20 ma 8 ma type - 20 ma 11 ma type - 2 ma 2 ma type H level average output current * 6 OHAV - -4 ma 4 ma type - 8 ma 8 ma type - 11 ma 11 ma type H level total maximum output current OH ma H level total average output current * 7 OHAV ma Power consumption PD mw Storage temperature TSTG C *1: These parameters are based on the condition that VSS = AVSS = 0.0 V. *2: VCC must not drop below VSS V. *3: VBAT must not drop below VSS V. *4: Ensure that the voltage does not exceed VCC V, for example, when the power is turned on. Unit Remarks *5: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *6: The average output current is defined as the average current value flowing through any one of the corresponding pins for a 100 ms period. *7: The total average output current is defined as the average current value flowing through all of corresponding pins for a 100 ms. WARNNG: Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings. Document Number: Rev.*C Page 72 of 182

73 12.2 Recommended Operating Conditions Parameter Symbol Conditions Value Min Max Unit Remarks Power supply voltage VCC *1 V 2.7 *5 3.6 *2 Power supply voltage (VBAT) VBAT V Analog power supply voltage AVCC V AVCC = VCC Analog reference voltage AVRH - *4 AVCC V AVRL - AVss AVss V Smoothing capacitor CS μf for built-in regulator *6 Operating Junction temperature TJ C temperature Ambient temperature TA *3 C *1: When using the GDC part. When P81/UDP0 and P80/UDM0 pins are used as USB (UDP0, UDM0). *2: When P81/UDP0 and P80/UDM0 pins are used as GPO (P81, P80). *3: The maximum temperature of the ambient temperature (TA) can guarantee a range that does not exceed the junction temperature (TJ). The calculation formula of the ambient temperature (TA) is shown below. TA(Max) = TJ(Max) - Pd(Max) θja Pd: θja: Power dissipation (W) Package thermal resistance ( C/W) Pd (Max) = VCC CC (Max) + Σ (OL VOL) + Σ ((VCC-VOH) (- OH)) OL: OH: VOL: VOH: L level output current H level output current L level output voltage H level output voltage *4: The minimum value of Analog reference voltage depends on the value of compare clock cycle (tcck). See bit A/D Converter for the details. *5: n between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction execution and low voltage detection function by built-in High-speed CR(including Main PLL is used) or built-in Low-speed CR is possible to operate only. *6: See "C pin" in "7. Handling Devices" for the connection of the smoothing capacitor. Document Number: Rev.*C Page 73 of 182

74 Package thermal resistance and maximum permissible power for each package are shown below. The operation is guaranteed maximum permissible power or less for semiconductor devices. Table 12-1 Table for Package Thermal Resistance and Maximum Permissible Power Package LQFP: LQM120 (0.5 mm pitch) LQFP: LQM120 * 1 (0.5 mm pitch) LQFP: LQP176 (0.5 mm pitch) FBGA: FDJ161 (0.5 mm pitch) Ex-LQFP: LEM120 (0.5 mm pitch) Printed Circuit Board Thermal Resistance θja ( C/W) Maximum Permissible Power (mw) TA= +85 C TA= +105 C 4 layers layers layers layers layers 18* *1: When S6E2D55GJA product. *2: This is a case where the connection process was carried out back exposed die pad foundation. Please connect directly to GND back exposed die pad. Notes: 1. The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. 2. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. 3. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. 4. Users considering application outside the listed conditions are advised to contact their representatives beforehand. Document Number: Rev.*C Page 74 of 182

75 Calculation Method of Power Dissipation (Pd) The power dissipation is shown in the following formula. Pd = VCC CC + Σ (OL VOL) + Σ ((VCC-VOH) (-OH)) OL: OH: VOL: VOH: L level output current H level output current L level output voltage H level output voltage CC is a current consumed in device. t can be analyzed as follows. CC = CC(NT) + ΣCC(O) CC(NT): Current consumed in internal logic and memory, etc. through regulator ΣCC(O): Sum of current (/O switching current) consumed in output pin For CC (NT), it can be anticipated by "(1) Current Rating" in "3. DC Characteristics" (This rating value does not include CC (O) for a value at pin fixed). For cc (O), it depends on system used by customers. The calculation formula is shown below. CC(O) = (CNT + CEXT) VCC fsw CNT: Pin internal load capacitance CEXT: External load capacitance of output pin fsw: Pin switching frequency Parameter Symbol Conditions Capacitance Value Pin internal load capacitance CNT 2 ma type 1.93 pf 4 ma type 3.45 pf 8 ma type 3.42 pf Calculate CC (Max) as follows when the power dissipation can be evaluated by yourself. (1) Measure current value CC (Typ) at normal temperature (+25 C). (2) Add maximum leak current value CC (leak_max) at operating on a value in (1). CC(Max) = CC(Typ) + CC(leak_max) Parameter Symbol Conditions Current Value Maximum leak current at operating Note: VFLASH of current is not included CC(leak_max) TJ = +125 C TJ = +105 C TJ = +85 C 66.8 ma 33.7 ma 22.8 ma Document Number: Rev.*C Page 75 of 182

76 Current Explanation Diagram CC A VCC Pd = VCC CC + Σ(OL VOL)+Σ((VCC-VOH) (-OH)) CC = CC(NT)+ΣCC(O) Chip CC(NT) ΣCC(O) Regulator A OL V VOL Flash RAM Logic CC(O) VOH V A CEXT OH Document Number: Rev.*C Page 76 of 182

77 12.3 DC Characteristics Current Rating Table 12-2 Typical and Maximum Current Consumption in Normal Operation (PLL), Code Running from Flash Memory (Flash Accelerator Mode and Trace Buffer Function Enabled) Parameter Power supply current Symbol CC *1: TA=+25 C, VCC=3.3 V Pin Name VCC *2: TJ=+125 C, VCC=3.6 V *3: When all ports are fixed. Conditions Normal operation *6,*7 (PLL) Normal operation, *6,*7 (PLL) *5 Frequency* 4 (MHz) *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2 *5 Value Typ* 1 Max* 2 Unit 160 MHz ma 144 MHz ma 120 MHz ma 100 MHz ma 80 MHz ma 60 MHz ma 40 MHz ma 20 MHz ma 8 MHz ma 4 MHz ma 160 MHz ma 144 MHz ma 120 MHz ma 100 MHz ma 80 MHz ma 60 MHz ma 40 MHz ma 20 MHz ma 8 MHz 7 74 ma 4 MHz 6 73 ma *5: When operating flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 1) *6: Data access is nothing to main flash memory and VFLASH memory *7: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit) Remarks *3 When all peripheral clocks are ON GDC clock 160 MHz *3 When all peripheral clocks are OFF Document Number: Rev.*C Page 77 of 182

78 Table 12-3 Typical and Maximum Current Consumption in Normal Operation (PLL), Code with Data Accessing Running from Flash Memory (Flash Accelerator Mode and Trace Buffer Function Disabled) Parameter Power supply current Symbol CC *1: TA=+25 C, VCC=3.3 V Pin Name VCC *2: TJ=+125 C, VCC=3.6 V *3: When all ports are fixed. Conditions Normal operation *6,*7,*8 (PLL) Normal operation *6,*7,*8 (PLL) *5 *5 Frequency* 4 (MHz) Value Typ* 1 Max* 2 Unit 160 MHz ma 144 MHz ma 120 MHz ma 100 MHz ma 80 MHz ma 60 MHz ma 40 MHz ma 20 MHz ma 8 MHz ma 4 MHz ma 160 MHz ma 144 MHz ma 120 MHz ma 100 MHz ma 80 MHz ma 60 MHz ma 40 MHz ma 20 MHz ma 8 MHz ma 4 MHz 9 79 ma *4: Frequency is a value of HCLK. PCLK0=PCLK2=HCLK/2, PCLK1=HCLK Remarks *3 When all peripheral clocks are ON GDC clock 160 MHz *3 When all peripheral clocks are OFF *5: When not operating flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 0) *6: With data access to a main flash memory. *7: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit) *8: Data access is nothing to VFLASH memory Document Number: Rev.*C Page 78 of 182

79 Table 12-4 Typical and Maximum Current Consumption in Normal Operation (PLL), Code with Data Accessing Running from Flash Memory (Flash 0 Wait-cycle Mode and Read Access 0 Wait) Parameter Power supply current Symbol CC *1: TA=+25 C, VCC=3.3 V Pin Name VCC *2: TJ=+125 C, VCC=3.6 V *3: When all ports are fixed. Conditions Normal operation, *6,*7,*8 (PLL) *5 Frequency* 4 (MHz) *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK *5 Value Typ* 1 Max* 2 Unit 72 MHz ma 60 MHz ma 48 MHz ma 36 MHz ma 24 MHz ma 12 MHz ma 8 MHz ma 4 MHz ma 72 MHz ma 60 MHz ma 48 MHz ma 36 MHz ma 24 MHz ma 12 MHz ma 8 MHz ma 4 MHz ma Remarks *3 When all peripheral clocks are ON GDC clock 160 MHz *3 When all peripheral clocks are OFF *5: When operating flash 0 wait-cycle mode and read access 0 wait (FRWTR.RWT = 00, FSYNDN.SD = 000) *6: With data access to a main flash memory. *7: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit) *8: Data access is nothing to VFLASH memory Document Number: Rev.*C Page 79 of 182

80 Table 12-5 Typical and Maximum Current Consumption in Normal Operation (other than PLL), Code with Data Accessing Running from Flash Memory (Flash 0 Wait-cycle Mode and Read Access 0 Wait) Parameter Power supply current Symbol CC *1: TA=+25 C, VCC=3.3 V Pin Name VCC *2: TJ=+125 C, VCC=3.6 V *3: When all ports are fixed. Conditions Normal operation, *6,*8 (built-in Highspeed CR) Normal operation, *6,*7,*8 (Sub oscillation) Normal operation, *6,*8 (built-in Low-speed CR) Frequency* 4 (MHz) *5 4 MHz *5 32 khz *5 100 khz *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2 Value Typ* 1 Max* 2 Unit ma ma ma ma ma ma Remarks *3 When all peripheral clocks are ON GDC clock 160 MHz *3 When all peripheral clocks are OFF *3 When all peripheral clocks are ON *3 When all peripheral clocks are OFF *3 When all peripheral clocks are ON *3 When all peripheral clocks are OFF *5: When operating flash 0 wait-cycle mode and read access 0 wait (FRWTR.RWT = 00, FSYNDN.SD = 000) *6: With data access to a main flash memory. *7: When using the crystal oscillator of 32 khz (including the current consumption of the oscillation circuit) *8: Data access is nothing to VFLASH memory Document Number: Rev.*C Page 80 of 182

81 Table 12-6 Typical and Maximum Current Consumption in Sleep Operation (PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK/2 Parameter Power supply current Symbol CCS *1: TA=+25 C, VCC=3.3 V Pin Name VCC *2: TJ=+125 C, VCC=3.6 V *3: When all ports are fixed. Conditions Sleep *5,*6 operation (PLL) Sleep *5,*6 operation (PLL) *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2 Frequency* 4 Value (MHz) Typ* 1 Max* 2 Unit 160 MHz ma 144 MHz ma 120 MHz ma 100 MHz ma 80 MHz ma 60 MHz ma 40 MHz ma 20 MHz ma 8 MHz ma 4 MHz ma 160 MHz ma 144 MHz ma 120 MHz ma 100 MHz ma 80 MHz ma 60 MHz ma 40 MHz 9 76 ma 20 MHz 6 73 ma 8 MHz 5 72 ma 4 MHz 4 71 ma Remarks *3 When all peripheral clocks are ON GDC clock 160 MHz *3 When all peripheral clocks are OFF *5: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit) *6: Data access is nothing to VFLASH memory Document Number: Rev.*C Page 81 of 182

82 Table 12-7 Typical and Maximum Current Consumption in Sleep Operation (PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK Parameter Power supply current Symbol CCS *1: TA=+25 C, VCC=3.3 V Pin Name VCC *2: TJ=+125 C, VCC=3.6 V *3: When all ports are fixed. Conditions Sleep *5,*6 operation (PLL) *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK Frequency* 4 Value (MHz) Typ* 1 Max* 2 Unit 72 MHz ma 60 MHz ma 48 MHz ma 36 MHz ma 24 MHz ma 12 MHz ma 8 MHz ma 4 MHz ma 72 MHz ma 60 MHz ma 48 MHz ma 36 MHz ma 24 MHz 8 75 ma 12 MHz 7 74 ma 8 MHz 6 73 ma 4 MHz 5 72 ma Remarks *3 When all peripheral clocks are ON GDC clock 160 MHz *3 When all peripheral clocks are OFF *5: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit) *6: Data access is nothing to VFLASH memory Document Number: Rev.*C Page 82 of 182

83 Table 12-8 Typical and Maximum Current Consumption in Sleep Operation (other than PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK/2 Parameter Power supply current Symbol CCS *1: TA=+25 C, VCC=3.3 V Pin Name VCC *2: TJ=+125 C, VCC=3.6 V *3: When all ports are fixed. Conditions Sleep *6 operation (built-in High-speed CR) Sleep *5,*6 operation (Sub oscillation) Sleep *6 operation (built-in Low-speed CR) Frequency* 4 (MHz) 4 MHz 32 khz 100 khz *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2 Value Typ* 1 Max* 2 Unit ma 2 72 ma ma ma ma ma *5: When using the crystal oscillator of 32 khz (including the current consumption of the oscillation circuit) *6: Data access is nothing to VFLASH memory Remarks *3 When all peripheral clocks are ON GDC clock 160 MHz *3 When all peripheral clocks are OFF *3 When all peripheral clocks are ON *3 When all peripheral clocks are OFF *3 When all peripheral clocks are ON *3 When all peripheral clocks are OFF Document Number: Rev.*C Page 83 of 182

84 Table 12-9 Typical and Maximum Current Consumption in Stop Mode, Timer Mode and RTC Mode Parameter Symbol CCH Pin Name Conditions Frequency (MHz) Stop mode - Value Typ* 1 Max* 2 Unit ma ma ma *3, *4 TA=+25 C *3, *4 TA=+85 C *3, *4 TA=+105 C Remarks ma *3, *4 TA=+25 C Timer mode (built-in High-speed CR) 4 MHz ma *3, *4 TA=+85 C ma *3, *4 TA=+105 C Power supply current CCT VCC Timer mode *5 (Sub oscillation) 32 khz ma ma *3, *4 TA=+25 C *3, *4 TA=+85 C ma *3, *4 TA=+105 C Timer mode (built-in Low-speed CR) 100 khz ma ma ma *3, *4 TA=+25 C *3, *4 TA=+85 C *3, *4 TA=+105 C ma *3, *4 TA=+25 C CCR RTC mode (Sub oscillation) 32 khz ma *3, *4 TA=+85 C ma *3, *4 TA=+105 C *1: VCC=3.3 V *2: VCC=3.6 V *3: When all ports are fixed. *4: When LVD is OFF *5: When using the crystal oscillator of 32 khz (including the current consumption of the oscillation circuit) Document Number: Rev.*C Page 84 of 182

85 Table Typical and Maximum Current Consumption in Deep Standby Stop Mode, Deep Standby RTC Mode and VBAT Parameter Power supply current *1: VCC=3.3 V *2: VCC=3.6 V Symbol CCHD CCRD CCVBAT Pin Name VCC VBAT *3: When all ports are fixed. *4: When LVD is OFF *5: When sub oscillation is OFF Conditions Deep Standby Stop mode (When RAM is OFF) Deep Standby Stop mode (When RAM is ON) Deep Standby RTC mode (When RAM is OFF) Deep Standby RTC mode (When RAM is ON) RTC stop *8 RTC *6, *8 operation RTC *7, *8 operation Frequency (MHz) khz - Value Typ* 1 Max* 2 Unit μa μa μa μa μa μa μa μa μa μa μa μa μa μa μa μa μa μa μa μa μa *3, *4 TA=+25 C *3, *4 TA=+85 C *3, *4 TA=+105 C *3, *4 TA=+25 C *3, *4 TA=+85 C *3, *4 TA=+105 C *3, *4 TA=+25 C *3, *4 TA=+85 C *3, *4 TA=+105 C *3, *4 TA=+25 C *3, *4 TA=+85 C *3, *4 TA=+105 C *3, *4, *5 TA=+25 C *3, *4, *5 TA=+85 C *3, *4, *5 TA=+105 C *3, *4 TA=+25 C *3, *4 TA=+85 C *3, *4 TA=+105 C *3, *4 TA=+25 C *3, *4 TA=+85 C *3, *4 TA=+105 C *6: When using the crystal oscillator of 32 khz (including the current consumption of the oscillation circuit) When the Standard setting (CCS/CCB= ) *7: When using the crystal oscillator of 32 khz (including the current consumption of the oscillation circuit) When the low power setting (CCS/CCB= ) *8: n the case of setting RTC after VCC power on Remarks Document Number: Rev.*C Page 85 of 182

86 Table Typical and Maximum Current Consumption in Low-voltage Detection Circuit, Main Flash Memory Write/erase, VFLASH Memory Parameter Low-voltage detection circuit (LVD) power supply current Main flash memory write/erase current VFLASH memory Standby current VFLASH memory Read current VFLASH memory write/erase current Symbol CCLVD Pin name VCC Conditions Value Min Typ Max Unit At operation μa CCFLASH At Write/Erase ma CCVFLASH At Standby μa At Read MHz ma MHz At Write/Erase ma (VCC = 2.7V to 3.6V, VSS = 0V) Remarks For occurrence of interrupt Peripheral Current Dissipation Clock system HCLK PCLK1 Peripheral Unit Frequency (MHz) GPO All ports DMAC DSTC External bus /F CAN-FD 1ch USB 1ch S 1 unit Programmable CRC Base timer 4ch Multi-functional timer/ppg 1unit/4ch Quadrature position/revolution 1ch counter A/DC 1 unit PCLK2 Multi-function serial 1ch ma GECLK GDC unit GDC 1 unit High-Speed Quad SP 1ch HyperBus /F 1 unit SDRAM-F 1ch Unit ma ma ma Remarks TA=+25 C, VCC=3.3 V TA=+25 C, VCC=3.3 V TA=+25 C, VCC=3.3 V TA=+25 C, VCC=3.3 V Document Number: Rev.*C Page 86 of 182

87 Pin Characteristics (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Name Conditions H level voltage (hysteresis ) L level voltage (hysteresis ) H level output voltage L level output voltage nput leak current Pull-up resistor value nput capacitance VHS VLS VOH VOL CMOS hysteresis pin, MD0, MD1 5 V tolerant pin nput pin doubled as 2 C Fm+ TTL Schmitt pin CMOS hysteresis pin, MD0, MD1 5 V tolerant pin nput pin doubled as 2 C Fm+ TTL Schmitt pin Value Min Typ Max Unit - VCC VCC V - VCC VSS V - VCC VSS V VCC+0.3 V - VSS VCC 0.2 V - VSS VCC 0.2 V - VSS - VCC 0.3 V - VSS V 2 ma type OH = - 2 ma VCC VCC V 4 ma type OH = - 4 ma VCC VCC V 8 ma type OH = - 8 ma VCC VCC V 11 ma type OH = - 11 ma VCC VCC V Remarks High-speed O The pin doubled as USB /O OH = ma VCC VCC V The pin doubled as 2 C Fm+ OH = - 3 ma VCC VCC V At GPO 2 ma type OL = 2 ma VSS V 4 ma type OL = 4 ma VSS V 8 ma type OL = 8 ma VSS V 11 ma type OL = 11 ma VSS V The pin doubled as USB /O OL = 10.5 ma VSS V The pin doubled as OL = 3 ma At GPO 2 VSS V C Fm+ OL = 20 ma At 2 C Fm+ L μa RPU CN Pull-up pin Other than VCC, VBAT, VSS, AVCC, AVSS, AVRH kω pf High-speed O Document Number: Rev.*C Page 87 of 182

88 12.4 AC Characteristics Main Clock nput Characteristics Parameter nput frequency Symbol fch Pin Name Conditions Min Value Max Unit MHz (VCC = 2.7V to 3.6V, VSS = 0V) Remarks When crystal oscillator is connected MHz When using external clock X0, nput clock cycle tcylh X ns When using external clock nput clock pulse width - nput clock rising time and falling time nternal operating clock*1 frequency nternal operating clock*1 cycle time tcf, tcr PWH/tCYLH, PWL/tCYLH % When using external clock ns When using external clock fcm MHz Master clock fcc MHz Base clock (HCLK/FCLK) fcp MHz APB0 bus clock*2 fcp MHz APB1 bus clock*2 fcp MHz APB2 bus clock*2 tcycc ns Base clock (HCLK/FCLK) tcycp ns APB0 bus clock*2 tcycp ns APB1 bus clock*2 tcycp ns APB2 bus clock*2 *1: For more information about each internal operating clock, see Chapter 2-1: Clock in FM4 Family Peripheral Manual Main part ( ). *2: For about each APB bus which each peripheral is connected to, see Block Diagram in this data sheet. X0 Document Number: Rev.*C Page 88 of 182

89 Sub Clock nput Characteristics Parameter nput frequency Symbol 1/tCYLL Pin Name Conditions Value Min Typ Max X0A, X1A khz nput clock cycle tcyll μs nput clock pulse width - (VBAT = 1.65V to 3.6V, VSS = 0V) Unit khz PWH/tCYLL, PWL/tCYLL % *: For more information about crystal oscillator, see Sub crystal oscillator in 9. Handling Devices. Remarks When crystal oscillator is connected * When using external clock When using external clock When using external clock t CYLL X0A 0.8 VBAT 0.8 VBAT 0.8 VBAT 0.2 VBAT 0.2 VBAT P WH P WL Built-in CR Oscillation Characteristics Built-in High-speed CR Parameter Symbol Conditions Value Min Typ Max (VCC = 2.7V to 3.6V, VSS = 0V) Unit Remarks Clock frequency Frequency stabilization time fcrh TJ = - 20 C to C TJ = - 40 C to C TJ = - 40 C to C MHz tcrwt μs *2 When trimming *1 When not trimming *1: n the case of using the values in CR trimming area of Flash memory at shipment for frequency/temperature trimming. *2: This is the time to stabilize the frequency of High-speed CR clock after setting trimming value. This period is able to use High-speed CR clock as source clock. Built-in Low-speed CR (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Condition Value Min Typ Max Unit Remarks Clock frequency fcrl khz Document Number: Rev.*C Page 89 of 182

90 Operating Conditions of Main PLL (n the Case of Using Main Clock for nput Clock of PLL) (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Value Min Typ Max PLL oscillation stabilization wait time* 1 (LOCK UP time) tlock μs PLL clock frequency fpll 4-16 MHz PLL multiplication rate multiplier PLL macro oscillation clock frequency fpllo MHz Main PLL clock frequency* 2 fclkpll MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. Unit Remarks *2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM4 Family Peripheral Manual Main part ( ) Operating Conditions of USB/ 2 S/GDC PLL (n the Case of Using Main Clock for nput Clock of PLL) (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Value Min Typ Max PLL oscillation stabilization wait time*1 (LOCK UP time) tlock μs PLL clock frequency fpll 4-16 MHz Unit Remarks PLL multiplication rate multiplier PLL macro oscillation clock frequency fpllo MHz USB/GDC 384 MHz 2 S USB clock frequency *2 fclkpll MHz After the M frequency division 2 S clock frequency *3 fclkpll MHz After the M frequency division GDC clock frequency *4 fclkpll MHz After divided by GDC part *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about USB clock, see Chapter 2-2: USB Clock Generation in FM4 Family Peripheral Manual Communication Macro part ( ). *3: For more information about 2 S clock, see Chapter 7-1: 2 S Clock Generation in FM4 Family Peripheral Manual Communication Macro part ( ). *4: For more information about GDC clock, see FM4 Family Peripheral Manual GDC part ( ). Document Number: Rev.*C Page 90 of 182

91 Operating Conditions of Main PLL (n the Case of Using Built-in High-Speed CR Clock for nput Clock of Main PLL) (VCC = 2.7V to 3.6V, VSS = 0V) Parameter PLL oscillation stabilization wait time* 1 (LOCK UP time) Symbol Value Min Typ Max Unit tlock μs PLL clock frequency fpll MHz PLL multiplication rate multiplier PLL macro oscillation clock frequency fpllo MHz Main PLL clock frequency*2 fclkpll MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. Remarks *2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM4 Family Peripheral Manual Main part ( ). Note: The High-speed CR clock (CLKHC) should be set with frequency/temperature trimming to act as the source clock of the Main PLL Reset nput Characteristics (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Name conditions Value Reset time tntx NTX ns Min Max Unit Remarks Document Number: Rev.*C Page 91 of 182

92 Power-on Reset Timing (VSS = 0V) Parameter Symbol Pin Name Conditions Value Min Typ Max Unit Remarks Power supply shut down time toff ms *1 Power ramp rate dv/dt VCC VCC: 0.2V to 2.70V mv/µs *2 Time until releasing Power-on reset tprt ms *1: VCC must be held below 0.2V for a minimum period of toff. mproper initialization may occur if this condition is not met. *2: This dv/dt characteristic is applied at the power-on of cold start (toff>1ms). Note: f toff cannot be satisfied designs must assert external reset(ntx) at power-up and at any brownout event per V V CC V DH 0.2V dv/dt 0.2V 0.2V tprt toff nternal RST CPU Operation RST Active release start Glossary VDH: detection voltage of Low Voltage detection reset. See Low-Voltage Detection Characteristics GPO Output Characteristics (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Name Conditions Min Value Max Unit Remarks Output frequency tpcycle Pxx* MHz *: GPO is a target. Pxx t PCYCLE Document Number: Rev.*C Page 92 of 182

93 External Bus Timing External Bus Clock Output Characteristics (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Name Conditions Min Value Max Unit Remarks Output frequency tcycle MCLKOUT* 1-50* 2 MHz *1: The external bus clock (MCLKOUT) is a divided clock of HCLK. For more information about setting of clock divider, see Chapter 14: External Bus nterface in FM4 Family Peripheral Manual Main part ( ). *2: Generate MCLKOUT at setting more than 4 divisions when the AHB bus clock exceeds 100 MHz. 0.8 Vcc 0.8 Vcc MCLKOUT t CYCLE External Bus Signal nput/output Characteristics (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Conditions Value Unit Remarks Signal characteristics Signal output characteristics VH 0.8 VCC V VL 0.2 VCC V - VOH 0.8 VCC V VOL 0.2 VCC V nput signal VH VL VH VL Output signal VOH VOL VOH VOL Document Number: Rev.*C Page 93 of 182

94 Separate Bus Access Asynchronous SRAM Mode (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin name Conditions MOEX Mininum pulse width MCSX Address output delay time MOEX Address hold time MCSX MOEX delay time MOEX MCSX time MCSX MDQM delay time Data setup MOEX time MOEX Data hold time MWEX Mininum pulse width MWEX Address output delay time MCSX MWEX delay time MWEX MCSX delay time MCSX MDQM delay time MCSX Data output time MWEX Data hold time Min Value Max toew MOEX - MCLK n-3 - ns tcsl AV toeh - AX MCSX, MAD[24:0] MOEX, MAD[24:0] Unit ns - 0 MCLK m+9 ns tcsl - OEL MOEX, - MCLK m-9 MCLK m+9 ns toeh - CSH MCSX - 0 MCLK m+9 ns tcsl - RDQML tds - OE tdh - OE MCSX, MDQM[1:0] MOEX, MADATA[15:0] MOEX, MADATA[15:0] - MCLK m-9 MCLK m+9 ns ns ns twew MWEX - MCLK n-3 - ns tweh - AX MWEX, MAD[24:0] - 0 MCLK m+9 ns tcsl - WEL MWEX, - MCLK n-9 MCLK n+9 ns tweh - CSH MCSX - 0 MCLK m+9 ns tcsl-wdqml tcsl-dx tweh - DX MCSX, MDQM[1:0] MCSX, MADATA[15:0] MWEX, MADATA[15:0] - MCLK n-9 MCLK n+9 ns - MCLK-9 MCLK+9 ns - 0 MCLK m+9 ns Remarks Note: When the external load capacitance CL = 30 pf (m=0 to 15, n=1 to 16) Document Number: Rev.*C Page 94 of 182

95 t CYCLE MCLK MCSX t OEH-CSH t WEH-CSH MAD[24:0] t CSL-AV t OEH-AX Address t CSL-AV Address t WEH-AX MOEX MDQM[1:0] t CSL-OEL tcsl-rdqml t OEW t CSL-WDQML t CSL-WEL MWEX t WEW MADATA[15:0] t DS-OE RD t DH-OE nvalid WD t WEH-DX t CSL-DX Document Number: Rev.*C Page 95 of 182

96 Separate Bus Access Synchronous SRAM Mode Parameter Symbol Pin Name Conditions Address delay time MCSX delay time tav MCLK, MAD[24:0] Min Value Max (VCC = 2.7V to 3.6V, VSS = 0V) Unit ns tcsl MCLK, ns tcsh MCSX ns Remarks MOEX delay time Data set up MCLK time MCLK Data hold time MWEX delay time trel MCLK, ns treh MOEX ns tds tdh MCLK, MADATA[15:0] MCLK, MADATA[15:0] ns ns twel MCLK, ns tweh MWEX ns MDQM[1:0] delay time MCLK Data output time MCLK Data hold time tdqml MCLK, ns tdqmh MDQM[1:0] ns tods tod MCLK, MADATA[15:0] MCLK, MADATA[15:0] Note: When the external load capacitance CL = 30 pf - MCLK+1 MCLK+18 ns ns t CYCLE MCLK t CSL t CSH MCSX MAD[24:0] t AV Address t AV Address t REL t REH MOEX MDQM[1:0] t DQML t DQMH t DQML t DQMH MWEX MADATA[15:0] t DS RD t DH nvalid t WEL WD t WEH t OD t ODS Document Number: Rev.*C Page 96 of 182

97 Multiplexed Bus Access Asynchronous SRAM Mode (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Name Conditions Multiplexed address delay time Multiplexed address hold time tale-chmadv Min Value Max MALE, ns tchmadh MAD[24:0] - MCLK n+0 MCLK n+10 ns Note: When the external load capacitance CL = 30 pf (m=0 to 15, n=1 to 16) Unit Remarks MCLK MCSX MALE MAD [24:0] MOEX MDQM [1:0] MWEX MADATA[15:0] Document Number: Rev.*C Page 97 of 182

98 Multiplexed Bus Access Synchronous SRAM Mode (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Name Conditions MALE delay time MCLK Multiplexed address delay time MCLK Multiplexed data output time Note: When the external load capacitance CL = 30 pf Min Value Max Unit tchal MCLK, ns tchah MALE ns tchmadv MCLK, - 1 tod ns tchmadx MADATA[15:0] - 1 tod ns Remarks MCLK MCSX MALE MAD [24:0] MOEX MDQM [1:0] MWEX MADATA[15:0] Document Number: Rev.*C Page 98 of 182

99 NAND Flash Mode (VCC = 2.7V to 3.6V, VSS = 0V) Value Parameter Symbol Pin Name Conditions Unit Min Max MNREX Min pulse width tnrew MNREX - MCLK n-3 - ns Data set up MNREX time MNREX Data hold time MNALE MNWEX delay time MNALE MNWEX delay time MNCLE MNWEX delay time MNWEX MNCLE delay time MNWEX Min pulse width MNWEX Data output time MNWEX Data hold time tds NRE tdh NRE taleh - NWEL talel - NWEL tcleh - NWEL tnweh - CLEL MNREX, MADATA[15:0] MNREX, MADATA[15:0] MNALE, MNWEX MNALE, MNWEX MNCLE, MNWEX MNCLE, MNWEX ns ns - MCLK m-9 MCLK m+9 ns - MCLK m-9 MCLK m+9 ns - MCLK m-9 MCLK m+9 ns - 0 MCLK m+9 ns tnwew MNWEX - MCLK n-3 - ns tnwel DV tnweh DX MNWEX, MADATA[15:0] MNWEX, MADATA[15:0] Note: When the external load capacitance CL = 30 pf (m=0 to 15, n=1 to 16) ns - 0 MCLK m+9 ns Remarks NAND Flash Read MCLK MNREX MADATA[15:0] Read Document Number: Rev.*C Page 99 of 182

100 NAND Flash Address Write MCLK MNALE MNCLE MNWEX MADATA[15:0] Write NAND Flash Command Write MCLK MNALE MNCLE MNWEX MADATA[15:0] Write Document Number: Rev.*C Page 100 of 182

101 External Ready nput Timing (VCC = 2.7V to 3.6V, VSS = 0V) MCLK MRDY setup time Parameter Symbol Pin Name Conditions trdy MCLK, MRDY Min Value Max Unit ns Remarks When RDY is MCLK Original MOEX MWEX Over 2cycles t RDY MRDY When RDY is released MCLK 2 cycles Extended MOEX MWEX trdy MRDY 0.5 V CC Document Number: Rev.*C Page 101 of 182

102 SDRAM Mode (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Name Value Min Unit Max Unit Remarks Output frequency tcycsd MSDCLK MHz Address delay time MSDCLK Data output delay time MSDCLK Data output Hi-Z time MDQM[1:0] delay time MCSX delay time taosd tdosd tdozsd twrosd tmcssd MSDCLK, MAD[15:0] MSDCLK, MADATA[15:0] MSDCLK, MADATA[15:0] MSDCLK, MDQM[1:0] MSDCLK, MCSX8 MRASX delay time trassd MSDCLK, MRASX MCASX delay time tcassd MSDCLK, MCASX MSDWEX delay time tmwesd MSDCLK, MSDWEX MSDCKE delay time tckesd MSDCLK, MSDCKE Data setup time tdssd MSDCLK, MADATA[15:0] Data hold time tdhsd MSDCLK, MADATA[15:0] Note: When the external load capacitance CL = 30 pf ns ns ns ns ns ns ns ns ns ns ns Document Number: Rev.*C Page 102 of 182

103 SDRAM Access t CYCSD MSDCLK MAD[24:0] t AOSD Address MDQM[1:0] t WROSD MCSX t MCSSD MRASX t RASSD MCASX t CASSD MSDWEX t MWESD MSDCKE t CKESD MADATA[15:0] t DSSD RD t DHSD MADATA[15:0] t DOSD WD t DOZSD Document Number: Rev.*C Page 103 of 182

104 Base Timer nput Timing Timer nput Timing (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Name Conditions nput pulse width ttwh, ttwl TOAn/TOBn (when using as ECK, TN) Min Value Max Unit - 2tCYCP - ns Remarks ECK t TWH t TWL TN V HS V HS V LS V LS Trigger nput Timing Parameter Symbol Pin Name Conditions nput pulse width ttrgh, ttrgl TOAn/TOBn (when using as TGN) Min Value (VCC = 2.7V to 3.6V, VSS = 0V) Max Unit - 2tCYCP - ns Remarks t TRGH t TRGL TGN V HS V HS V LS V LS Note: tcycp indicates the APB bus clock cycle time. About the APB bus number which the Base Timer is connected to, see 8. Block Diagram in this data sheet. Document Number: Rev.*C Page 104 of 182

105 CSO Timing Synchronous Serial (SP = 0, SCNV = 0) Parameter Symbol Pin Name Conditions Min Value (VCC = 2.7V to 3.6V, VSS = 0V) Baud rate Mbps Serial clock cycle time tscyc SCKx 4tCYCP - ns SCKx, SCK SOT delay time tslov ns SOTx nternal shift clock SN SCK SCKx, tvsh operation 50 - ns setup time SNx SCK SN hold time tshx SCKx, SNx 0 - ns Serial clock L pulse width tslsh SCKx 2tCYCP ns Serial clock H pulse width tshsl SCKx tcycp ns SCKx, SCK SOT delay time tslove - 50 ns SOTx External shift SN SCK SCKx, tvshe clock 10 - ns setup time SNx operation SCKx, SCK SN hold time tshxe 20 - ns SNx SCK falling time tf SCKx - 5 ns SCK rising time tr SCKx - 5 ns Notes: The above characteristics apply to CLK synchronous mode. tcycp indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. When the external load capacitance CL = 30 pf. Max Unit Document Number: Rev.*C Page 105 of 182

106 tscyc SCK VOL VOH VOL t SLOV SOT VOH VOL SN VH VL tvsh tshx VH VL MS bit = 0 t SLSH t SHSL SCK V H V H V H V L V L t F t SLOVE t R SOT V OH V OL t VSHE t SHXE SN V H V L V H V L MS bit = 1 Document Number: Rev.*C Page 106 of 182

107 Synchronous Serial (SP = 0, SCNV = 1) (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Value Name Conditions Min Max Unit Baud rate Mbps Serial clock cycle time tscyc SCKx 4tCYCP - ns SCKx, SCK SOT delay time tshov ns SOTx nternal shift clock SCKx, SN SCK setup time tvsl operation 50 - ns SNx SCK SN hold time tslx SCKx, SNx 0 - ns Serial clock L pulse width tslsh SCKx 2tCYCP ns Serial clock H pulse width tshsl SCKx tcycp ns SCK SOT delay time tshove SCKx, SOTx - 50 ns SN SCK setup time tvsle SCKx, External shift clock SNx operation 10 - ns SCK SN hold time tslxe SCKx, SNx 20 - ns SCK falling time tf SCKx - 5 ns SCK rising time tr SCKx - 5 ns Notes: The above characteristics apply to CLK synchronous mode. tcycp indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. When the external load capacitance CL = 30 pf. Document Number: Rev.*C Page 107 of 182

108 tscyc SCK VOH VOL VOH t SHOV SOT VOH VOL SN tvsl VH VL MS bit = 0 tslx VH VL t SHSL t SLSH SCK V H V H V L V L V L t R t SHOVE t F SOT V OH V OL SN t VSLE V H V L MS bit = 1 t SLXE V H V L Document Number: Rev.*C Page 108 of 182

109 Synchronous Serial (SP = 1, SCNV = 0) (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Value Name Conditions Min Max Unit Baud rate Mbps Serial clock cycle time tscyc SCKx 4tCYCP - ns SCK SOT delay time tshov SCKx, SOTx ns SN SCK SCKx, tvsl nternal shift clock 50 - ns setup time SNx operation SCKx, SCK SN hold time tslx 0 - ns SNx SOT SCK delay time tsovl SCKx, SOTx 2tCYCP ns Serial clock L pulse width tslsh SCKx 2tCYCP ns Serial clock H pulse width tshsl SCKx tcycp ns SCK SOT delay time tshove SCKx, SOTx - 50 ns SN SCK SCKx, External shift clock tvsle setup time SNx operation 10 - ns SCK SN hold time tslxe SCKx, SNx 20 - ns SCK falling time tf SCKx - 5 ns SCK rising time tr SCKx - 5 ns Notes: The above characteristics apply to CLK synchronous mode. tcycp indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. When the external load capacitance CL = 30 pf. Document Number: Rev.*C Page 109 of 182

110 tscyc VOH SCK tsovl VOL tshov VOL SOT VOH VOL VOH VOL tvsl tslx SN VH VL VH VL MS bit = 0 t SLSH t SHSL SCK V H V H V H V L V L SOT * V OH V OL tf tr t SHOVE V OH V OL t VSLE t SLXE SN V H V L V H V L *: Changes when writing to TDR register MS bit = 1 Document Number: Rev.*C Page 110 of 182

111 Synchronous Serial (SP = 1, SCNV = 1) (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Value name Conditions Min Max Unit Baud rate Mbps Serial clock cycle time tscyc SCKx 4tCYCP - ns SCK SOT delay time tslov SCKx, SOTx ns SCKx, SN SCK setup time tvsh nternal shift clock 50 - ns SNx operation SCKx, SCK SN hold time tshx 0 - ns SNx SOT SCK delay time tsovh SCKx, SOTx 2tCYCP ns Serial clock L pulse width tslsh SCKx 2tCYCP ns Serial clock H pulse width tshsl SCKx tcycp ns SCK SOT delay time tslove SCKx, SOTx - 50 ns SN SCK setup time tvshe SCKx, External shift SNx clock operation 10 - ns SCK SN hold time tshxe SCKx, SNx 20 - ns SCK falling time tf SCKx - 5 ns SCK rising time tr SCKx - 5 ns Notes: The above characteristics apply to CLK synchronous mode. tcycp indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. When the external load capacitance CL = 30 pf. Document Number: Rev.*C Page 111 of 182

112 tscyc SCK VOH VOL VOH tsovh tslov SOT VOH VOL VOH VOL tvsh tshx SN VH VL VH VL MS bit = 0 SCK tr t SHSL t SLSH tf V H V L V H V H V L V L SOT V OH V OL t SLOVE V OH V OL t VSHE t SHXE SN V H V L V H V L MS bit = 1 Document Number: Rev.*C Page 112 of 182

113 When Using Synchronous Serial Chip Select (SCNV = 0, CSLVL=1) (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Conditions Min Value SCS SCK setup time tcss (*1)-50 (*1)+0 ns SCK SCS hold time tcsh nternal shift clock operation (*2)+0 (*2)+50 ns SCS deselect time tcsd (*3)-50+5tCYCP (*3)+50+5tCYCP ns SCS SCK setup time tcsse SCK SCS hold time tcshe 0 - ns SCS deselect time tcsde External shift clock operation 3tCYCP+30 - ns SCS SOT delay time tdse - 40 ns Max Unit 3tCYCP+30 - ns SCS SOT delay time tdee 0 - ns (*1): CSSU bit value serial chip select timing operating clock cycle [ns] (*2): CSHD bit value serial chip select timing operating clock cycle [ns] (*3): CSDS bit value serial chip select timing operating clock cycle [ns] Notes: tcycp indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part ( ). When the external load capacitance CL = 30 pf. Document Number: Rev.*C Page 113 of 182

114 SCS output tcss tcsh tcsd SCK output SOT (SP=0) SOT (SP=1) MS bit = 0 SCS tcsde tcsse tcshe SCK tdee SOT (SP=0) tdse SOT (SP=1) MS bit = 1 Document Number: Rev.*C Page 114 of 182

115 When Using Synchronous Serial Chip Select (SCNV = 1, CSLVL=1) (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Conditions SCS SCK setup time tcss (*1)-50 (*1)+0 ns SCK SCS hold time tcsh nternal shift clock operation (*2)+0 (*2)+50 ns SCS deselect time tcsd (*3)-50+5tCYCP (*3)+50+5tCYCP ns SCS SCK setup time tcsse SCK SCS hold time tcshe 0 - ns SCS deselect time tcsde External shift clock operation 3tCYCP+30 - ns SCS SOT delay time tdse - 40 ns Min Value Max Unit 3tCYCP+30 - ns SCS SOT delay time tdee 0 - ns (*1): CSSU bit value serial chip select timing operating clock cycle [ns] (*2): CSHD bit value serial chip select timing operating clock cycle [ns] (*3): CSDS bit value serial chip select timing operating clock cycle [ns] Notes: tcycp indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part ( ). When the external load capacitance CL = 30 pf. Document Number: Rev.*C Page 115 of 182

116 SCS output tcss tcsh tcsd SCK output SOT (SP=0) SOT (SP=1) MS bit = 0 SCS tcsde tcsse tcshe SCK tdee SOT (SP=0) tdse SOT (SP=1) MS bit = 1 Document Number: Rev.*C Page 116 of 182

117 When Using Synchronous Serial Chip Select (SCNV = 0, CSLVL=0) Parameter Symbol Conditions Min Value (VCC = 2.7V to 3.6V, VSS = 0V) SCS SCK setup time tcss (*1)-50 (*1)+0 ns SCK SCS hold time tcsh nternal shift clock operation (*2)+0 (*2)+50 ns SCS deselect time tcsd (*3)-50+5tCYCP (*3)+50+5tCYCP ns SCS SCK setup time tcsse SCK SCS hold time tcshe 0 - ns SCS deselect time tcsde External shift clock operation 3tCYCP+30 - ns SCS SOT delay time tdse - 40 ns Max Unit 3tCYCP+30 - ns SCS SOT delay time tdee 0 - ns (*1): CSSU bit value serial chip select timing operating clock cycle [ns] (*2): CSHD bit value serial chip select timing operating clock cycle [ns] (*3): CSDS bit value serial chip select timing operating clock cycle [ns] Notes: tcycp indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part ( ). When the external load capacitance CL = 30 pf. Document Number: Rev.*C Page 117 of 182

118 tcsd SCS output tcss tcsh SCK output SOT (SP=0) SOT (SP=1) MS bit = 0 tcsde SCS tcsse tcshe SCK tdee SOT (SP=0) tdse SOT (SP=1) MS bit = 1 Document Number: Rev.*C Page 118 of 182

119 When Using Synchronous Serial Chip Select (SCNV = 1, CSLVL=0) Parameter Symbol Conditions Min Value (VCC = 2.7V to 3.6V, VSS = 0V) SCS SCK setup time tcss (*1)-50 (*1)+0 ns SCK SCS hold time tcsh nternal shift clock operation (*2)+0 (*2)+50 ns SCS deselect time tcsd (*3)-50+5tCYCP (*3)+50+5tCYCP ns SCS SCK setup time tcsse SCK SCS hold time tcshe 0 - ns SCS deselect time tcsde External shift clock operation 3tCYCP+30 - ns SCS SOT delay time tdse - 40 ns Max Unit 3tCYCP+30 - ns SCS SOT delay time tdee 0 - ns (*1): CSSU bit value serial chip select timing operating clock cycle [ns] (*2): CSHD bit value serial chip select timing operating clock cycle [ns] (*3): CSDS bit value serial chip select timing operating clock cycle [ns] Notes: tcycp indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part ( ). When the external load capacitance CL = 30 pf. Document Number: Rev.*C Page 119 of 182

120 tcsd SCS output tcss tcsh SCK output SOT (SP=0) SOT (SP=1) MS bit = 0 SCS tcsse tcshe tcsde SCK tdee SOT (SP=0) tdse SOT (SP=1) MS bit = 1 Document Number: Rev.*C Page 120 of 182

121 High-Speed Synchronous Serial (SP = 0, SCNV = 0) Parameter Symbol Pin Name Conditions Serial clock cycle time tscyc SCKx SCK SOT delay time tslov SCKx, SOTx nternal shift clock operation Min Value (VCC = 2.7V to 3.6V, VSS = 0V) Max Unit 4tCYCP - ns ns SN SCK setup time tvsh SCKx, 14 SNx 12.5* - ns SCK SN hold time tshx SCKx, SNx 5 - ns Serial clock L pulse width tslsh SCKx 2tCYCP ns Serial clock H pulse width tshsl SCKx tcycp ns SCK SOT delay time tslove SCKx, SOTx - 15 ns SN SCK setup time tvshe SCKx, External shift clock SNx operation 5 - ns SCK SN hold time tshxe SCKx, SNx 5 - ns SCK falling time tf SCKx - 5 ns SCK rising time tr SCKx - 5 ns Notes: The above characteristics apply to CLK synchronous mode. tcycp indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. These characteristics only guarantee the following pins. SN6_0, SOT6_0, SCK6_0, SCS60_0 When the external load capacitance CL = 30 pf. (For *, when CL = 10 pf) Document Number: Rev.*C Page 121 of 182

122 tscyc SCK VOL VOH VOL t SLOV SOT VOH VOL SN VH VL tvsh tshx VH VL MS bit = 0 t SLSH t SHSL SCK V H VL V L V H V H t F t SLOVE t R SOT V OH V OL t VSHE t SHXE SN V H V L V H V L MS bit = 1 Document Number: Rev.*C Page 122 of 182

123 High-Speed Synchronous Serial (SP = 0, SCNV = 1) Parameter Symbol Pin Name Conditions Serial clock cycle time tscyc SCKx SCK SOT delay time tshov SCKx, SOTx nternal shift clock operation Min (VCC = 2.7V to 3.6V, VSS = 0V) Value Max Unit 4tCYCP - ns ns SN SCK setup time tvsl SCKx, 14 SNx 12.5* - ns SCK SN hold time tslx SCKx, SNx 5 - ns Serial clock L pulse width tslsh SCKx 2tCYCP ns Serial clock H pulse width tshsl SCKx tcycp ns SCK SOT delay time tshove SCKx, SOTx - 15 ns SN SCK setup time tvsle SCKx, External shift clock SNx operation 5 - ns SCK SN hold time tslxe SCKx, SNx 5 - ns SCK falling time tf SCKx - 5 ns SCK rising time tr SCKx - 5 ns Notes: The above characteristics apply to CLK synchronous mode. tcycp indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. These characteristics only guarantee the following pins. SN6_0, SOT6_0, SCK6_0, SCS60_0 When the external load capacitance CL = 30 pf. (For *, when CL = 10 pf) Document Number: Rev.*C Page 123 of 182

124 tscyc SCK VOH VOL VOH t SHOV SOT VOH VOL SN VH VL tvsl tslx VH VL MS bit = 0 t SHSL t SLSH SCK V H V H V L V L V L SOT t R t SHOVE V OH t F V OL SN t VSLE V H V L MS bit = 1 t SLXE V H V L Document Number: Rev.*C Page 124 of 182

125 High-Speed Synchronous Serial (SP = 1, SCNV = 0) Parameter Symbol Pin Name Conditions Serial clock cycle time tscyc SCKx SCK SOT delay time tshov SCKx, SOTx Min (VCC = 2.7V to 3.6V, VSS = 0V) Value Max Unit 4tCYCP - ns ns SN SCK setup time tvsl SCKx, 14 nternal shift clock SNx operation 12.5* - ns SCK SN hold time tslx SCKx, SNx 5 - ns SOT SCK delay time tsovl SCKx, SOTx 2tCYCP ns Serial clock L pulse width tslsh SCKx 2tCYCP ns Serial clock H pulse width tshsl SCKx tcycp ns SCK SOT delay time tshove SCKx, SOTx - 15 ns SN SCK setup time tvsle SCKx, External shift clock SNx operation 5 - ns SCK SN hold time tslxe SCKx, SNx 5 - ns SCK falling time tf SCKx - 5 ns SCK rising time tr SCKx - 5 ns Notes: The above characteristics apply to CLK synchronous mode. tcycp indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. These characteristics only guarantee the following pins. SN6_0, SOT6_0, SCK6_0, SCS60_0 When the external load capacitance CL = 30 pf. (For *, when CL = 10 pf) Document Number: Rev.*C Page 125 of 182

126 tscyc VOH SCK tsovl VOL tshov VOL SOT VOH VOL VOH VOL tvsl tslx SN VH VL VH VL MS bit = 0 t SLSH t SHSL SCK V H V H V H V L V L SOT * V OH V OL tf tr t SHOVE V OH V OL t VSLE t SLXE SN V H V L V H V L *: Changes when writing to TDR register MS bit = 1 Document Number: Rev.*C Page 126 of 182

127 High-Speed Synchronous Serial (SP = 1, SCNV = 1) Parameter Symbol Pin Name Serial clock cycle time tscyc SCKx SCK SOT delay time tslov SCKx, SOTx Conditions Min Value (VCC = 2.7V to 3.6V, VSS = 0V) Max Unit 4tCYCP - ns ns SCKx, 14 SN SCK setup time tvsh nternal shift - ns SNx clock operation 12.5* SCKx, SCK SN hold time tshx 5 - ns SNx SOT SCK delay time tsovh SCKx, SOTx 2tCYCP ns Serial clock L pulse width tslsh SCKx 2tCYCP ns Serial clock H pulse width tshsl SCKx tcycp ns SCK SOT delay time tslove SCKx, SOTx - 15 ns SN SCK setup time tvshe SCKx, External shift SNx clock operation 5 - ns SCK SN hold time tshxe SCKx, SNx 5 - ns SCK falling time tf SCKx - 5 ns SCK rising time tr SCKx - 5 ns Notes: The above characteristics apply to CLK synchronous mode. tcycp indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. These characteristics only guarantee the following pins. SN6_0, SOT6_0, SCK6_0, SCS60_0 When the external load capacitance CL = 30 pf. (For *, when CL = 10 pf) Document Number: Rev.*C Page 127 of 182

128 tscyc SCK VOH VOL VOH tsovh tslov SOT VOH VOL VOH VOL tvsh tshx SN VH VL VH VL MS bit = 0 SCK tr t SHSL t SLSH tf V H V L V H V H V L V L t SLOVE SOT V OH V OL V OH V OL t VSHE t SHXE SN V H V L V H V L MS bit = 1 Document Number: Rev.*C Page 128 of 182

129 When Using High-Speed Synchronous Serial Chip Select (SCNV = 0, CSLVL=1) (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Conditions Min Value SCS SCK setup time tcss (*1)-20 (*1)+0 ns SCK SCS hold time tcsh nternal shift clock operation (*2)+0 (*2)+20 ns SCS deselect time tcsd (*3)-20+5tCYCP (*3)+20+5tCYCP ns SCS SCK setup time tcsse SCK SCS hold time tcshe 0 - ns SCS deselect time tcsde External shift clock operation 3tCYCP+15 - ns SCS SOT delay time tdse - 25 ns Max Unit 3tCYCP+15 - ns SCS SOT delay time tdee 0 - ns (*1): CSSU bit value serial chip select timing operating clock cycle [ns] (*2): CSHD bit value serial chip select timing operating clock cycle [ns] (*3): CSDS bit value serial chip select timing operating clock cycle [ns] Notes: tcycp indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part ( ). When the external load capacitance CL = 30 pf. Document Number: Rev.*C Page 129 of 182

130 SCS output tcsd tcss tcsh SCK output SOT (SP=0) SOT (SP=1) MS bit = 0 SCS tcsde tcsse tcshe SCK tdee SOT (SP=0) tdse SOT (SP=1) MS bit = 1 Document Number: Rev.*C Page 130 of 182

131 When Using High-Speed Synchronous Serial Chip Select (SCNV = 1, CSLVL=1) Parameter Symbol Conditions Min Value (VCC = 2.7V to 3.6V, VSS = 0V) SCS SCK setup time tcss (*1)-20 (*1)+0 ns SCK SCS hold time tcsh nternal shift clock operation (*2)+0 (*2)+20 ns SCS deselect time tcsd (*3)-20+5tCYCP (*3)+20+5tCYCP ns SCS SCK setup time tcsse SCK SCS hold time tcshe 0 - ns SCS deselect time tcsde External shift clock operation 3tCYCP+15 - ns SCS SOT delay time tdse - 25 ns Max Unit 3tCYCP+15 - ns SCS SOT delay time tdee 0 - ns (*1): CSSU bit value serial chip select timing operating clock cycle [ns] (*2): CSHD bit value serial chip select timing operating clock cycle [ns] (*3): CSDS bit value serial chip select timing operating clock cycle [ns] Notes: tcycp indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part ( ). When the external load capacitance CL = 30 pf. Document Number: Rev.*C Page 131 of 182

132 SCS output tcsd tcss tcsh SCK output SOT (SP=0) SOT (SP=1) MS bit = 0 SCS intpu tcsde tcsse tcshe SCK tdee SOT (SP=0) tdse SOT (SP=1) MS bit = 1 Document Number: Rev.*C Page 132 of 182

133 When Using High-Speed Synchronous Serial Chip Select (SCNV = 0, CSLVL=0) (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Conditions Value Min Max Unit SCS SCK setup time tcss (*1)-20 (*1)+0 ns SCK SCS hold time tcsh nternal shift clock operation (*2)+0 (*2)+20 ns SCS deselect time tcsd (*3)-20+5tCYCP (*3)+20+5tCYCP ns SCS SCK setup time tcsse 3tCYCP+15 - ns SCK SCS hold time tcshe 0 - ns SCS deselect time tcsde External shift clock operation 3tCYCP+15 - ns SCS SOT delay time tdse - 25 ns SCS SOT delay time tdee 0 - ns (*1): CSSU bit value serial chip select timing operating clock cycle [ns] (*2): CSHD bit value serial chip select timing operating clock cycle [ns] (*3): CSDS bit value serial chip select timing operating clock cycle [ns] Notes: tcycp indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part ( ). When the external load capacitance CL = 30 pf. Document Number: Rev.*C Page 133 of 182

134 tcsd SCS output tcss tcsh SCK output SOT (SP=0) SOT (SP=1) MS bit = 0 tcsde SCS tcsse tcshe SCK tdee SOT (SP=0) tdse SOT (SP=1) MS bit = 1 Document Number: Rev.*C Page 134 of 182

135 When Using Synchronous Serial Chip Select (SCNV = 1, CSLVL=0) (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Conditions Value Min Max Unit SCS SCK setup time tcss (*1)-20 (*1)+0 ns SCK SCS hold time tcsh nternal shift clock operation (*2)+0 (*2)+20 ns SCS deselect time tcsd (*3)-20+5tCYCP (*3)+20+5tCYCP ns SCS SCK setup time tcsse 3tCYCP+15 - ns SCK SCS hold time tcshe 0 - ns SCS deselect time tcsde External shift clock operation 3tCYCP+15 - ns SCS SOT delay time tdse - 40 ns SCS SOT delay time tdee 0 - ns (*1): CSSU bit value serial chip select timing operating clock cycle [ns] (*2): CSHD bit value serial chip select timing operating clock cycle [ns] (*3): CSDS bit value serial chip select timing operating clock cycle [ns] Notes: tcycp indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part ( ). When the external load capacitance CL = 30 pf. Document Number: Rev.*C Page 135 of 182

136 tcsd SCS output tcss tcsh SCK output SOT (SP=0) SOT (SP=1) MS bit = 0 SCS tcsse tcshe tcsde SCK tdee SOT (SP=0) tdse SOT (SP=1) MS bit = 1 Document Number: Rev.*C Page 136 of 182

137 External Clock (EXT = 1): when in Asynchronous Mode Only Value Parameter Symbol Condition Unit Min Max Serial clock L pulse width tslsh tcycp ns Serial clock H pulse width tshsl tcycp ns CL = 30 pf SCK falling time tf - 5 ns SCK rising time tr - 5 ns (VCC = 2.7V to 3.6V, VSS = 0V) Remarks SCK tr t SHSL t SLSH V H V H V H V L V V L L tf Document Number: Rev.*C Page 137 of 182

138 External nput Timing (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Min Max Unit Remarks nput pulse width tnh, tnl ADTG FRCK0-2tCYCP*1 - ns A/D converter trigger Free-run timer clock C0x nput capture DTT0X - 2tCYCP*1 - ns Waveform generator NTxx, NMX - 2tCYCP + 100(*1) - ns 500(*2) - ns External interrupt, NM WKUPx - 500(*3) - ns Deep standby wake up (*1): tcycp indicates the APB bus clock cycle time except stop when in Stop mode, in timer mode. About the APB bus number which the Multi-function Timer and External interrupt are connected to, see 8. Block Diagram in this data sheet. (*2): When in Stop mode, in timer mode. (*3): When in deep standby RTC mode, in deep standby Stop mode. Document Number: Rev.*C Page 138 of 182

139 Quadrature Position/Revolution Counter Timing Parameter Symbol Conditions AN pin H width tahl - AN pin L width tall - BN pin H width tbhl - BN pin L width tbll - BN rising time from PC_Mode2 or taubu AN pin H level PC_Mode3 AN falling time from PC_Mode2 or tbuad BN pin H level PC_Mode3 BN falling time from PC_Mode2 or tadbd AN pin L level PC_Mode3 AN rising time from PC_Mode2 or tbdau BN pin L level PC_Mode3 AN rising time from PC_Mode2 or tbuau BN pin H level PC_Mode3 BN falling time from PC_Mode2 or taubd AN pin H level PC_Mode3 AN falling time from PC_Mode2 or tbdad BN pin L level PC_Mode3 BN rising time from PC_Mode2 or tadbu AN pin L level PC_Mode3 ZN pin H width tzhl QCR:CGSC=0 ZN pin L width tzll QCR:CGSC=0 AN/BN rising and falling time from determined ZN tzabe QCR:CGSC=1 level Determined ZN level from AN/BN rising and falling tabez QCR:CGSC=1 time Min Value Max (VCC = 2.7V to 3.6V, VSS = 0V) Unit 2tCYCP* - ns *: tcycp indicates the APB bus clock cycle time except when in Stop mode, in timer mode. About the APB bus number which Quadrature Position/Revolution Counter is connected to, see 8. Block Diagram in this data sheet. tahl tall AN taubu tbuad tadbd tbdau BN tbhl tbll Document Number: Rev.*C Page 139 of 182

140 tbhl tbll BN tbuau taubd tbdad tadbu AN tahl tall ZN Document Number: Rev.*C Page 140 of 182

141 ZN AN/BN Document Number: Rev.*C Page 141 of 182

142 C Timing Standard Mode, Fast Mode (VCC = 2.7V to 3.6, VSS = 0V) Parameter Symbol Conditions Standard Mode Fast Mode Unit Min Max Min Max khz SCL clock frequency fscl (Repeated) START condition hold time thdsta μs SDA SCL SCL clock L width tlow μs SCL clock H width thgh μs (Repeated) Start condition setup time SCL SDA Data hold time SCL SDA Data setup time SDA SCL STOP condition setup time SCL SDA Bus free time between Stop condition and Start condition Noise filter tsusta CL = 30 pf, μs R = (Vp/OL) *1 thddat * *3 μs tsudat ns tsusto μs tbuf μs tsp 2 MHz tcycp<40 MHz 40 MHz tcycp<60 MHz 60 MHz tcycp<80 MHz 80 MHz tcycp 100 MHz 2 tcycp *4-2 tcycp *4 - ns 4 tcycp *4-4 tcycp *4 - ns 6 tcycp *4-6 tcycp *4 - ns 8 tcycp *4-8 tcycp *4 - ns *1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up resistance and OL indicates VOL guaranteed current. *2: The maximum thddat must satisfy that it does not extend at least L period (tlow) of device's SCL signal. *3: A Fast mode 2 C bus device can be used on a Standard mode 2 C bus system as long as the device satisfies the requirement of tsudat 250 ns. *4: tcycp is the APB bus clock cycle time. About the APB bus number that 2 C is connected to, see 8. Block Diagram in this data sheet. When the standard mode is used, please set to 2 MHz or more peripheral bus clock. When fast mode is used, please set to 8MHz or more peripheral bus clock. *5: The noise filter time can be changed by register settings. Change the number of the noise filter steps according to APB bus clock frequency. Remarks *5 Document Number: Rev.*C Page 142 of 182

143 Fast Mode Plus (Fm+) Parameter Symbol Conditions (VCC = 2.7V to 3.6V, VSS = 0V) Fast Mode Plus (Fm+)*6 Unit Min Max khz SCL clock frequency fscl (Repeated) Start condition hold time thdsta μs SDA SCL SCL clock L width tlow μs SCL clock H width thgh μs (Repeated) Start condition setup time SCL SDA Data hold time SCL SDA Data setup time SDA SCL Stop condition setup time SCL SDA Bus free time between Stop condition and Start condition Noise filter tsusta CL = 30 pf, μs R = (Vp/OL) *1 thddat *2, *3 μs tsudat 50 - ns tsusto μs tbuf μs tsp 60 MHz tcycp<80 MHz 80 MHz tcycp 100 MHz 6 tcycp *4 - ns 8 tcycp *4 - ns Remarks *1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up resistance and OL indicates VOL guaranteed current. *2: The maximum thddat must satisfy that it does not extend at least L period (tlow) of device's SCL signal. *3: A Fast mode 2 C bus device can be used on a Standard mode 2 C bus system as long as the device satisfies the requirement of "tsudat 250 ns". *4: tcycp is the APB bus clock cycle time. About the APB bus number that 2 C is connected to, see 8. Block Diagram in this data sheet. To use fast mode plus (Fm+), set the peripheral bus clock at 64 MHz or more. *5: The noise filter time can be changed by register settings. Change the number of the noise filter steps according to APB bus clock frequency. *6: When using fast mode plus (Fm+), set the /O pin to the mode corresponding to 2 C Fm+ in the EPFR register. See Chapter 12 : /O Port in "FM4 Family Peripheral Manual Main part ( )" for the details. *5 SDA SCL Document Number: Rev.*C Page 143 of 182

144 ETM Timing (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Name Conditions Min Value Max Unit Remarks Data hold tetmh TRACECLK, TRACED[3:0] ns TRACECLK frequency TRACECLK clock cycle 1/tTRACE TRACECLK Note: When the external load capacitance CL= 30 pf MHz ttrace ns HCLK TRACECLK TRACED[3:0] Document Number: Rev.*C Page 144 of 182

145 JTAG Timing (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Name Conditions TMS, TD setup time tjtags TCK, TMS, TD Min Value Max Unit ns Remarks TMS, TD hold time tjtagh TCK, TMS, TD ns TDO delay time tjtagd TCK, TDO Note: When the external load capacitance CL= 30 pf ns TCK TMS/TD TDO Document Number: Rev.*C Page 145 of 182

146 S Timing Master Mode Timing (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Name Conditions Min Value Output frequency tmcyc 2SCK MHz Output clock pulse width tmhw % 2SCK - tmlw % 2SCK 2SWS 2SCK, tdfs delay time 2SWS ns 2SCK 2SDO 2SCK, tddo delay time* 2SDO ns 2SD 2SCK thsd setup time 2SCK, ns 2SD 2SCK 2SD thd hold time ns nput signal rising time tr ns 2SD nput signal falling time tf ns *: Except for the first bit of transmission frame Notes: When the external load capacitance CL = 20 pf Max Unit Remarks When 2SWS=48 khz, 2MCLK=256 2SWS Frame synchronization signal (2SWS) is settable to 48 khz, 32 khz, 16 khz. See Chapter 7-2: 2 S(nter-C Sound bus)nterface in FM4 Family Peripheral Manual Communication part ( ) for the details. Document Number: Rev.*C Page 146 of 182

147 2 SCK ( CPOL= 0 ) t MHW t MCYC t MLW 2 SCK ( CPOL= 1 ) 2SWS (FSPH=0, FSLN =0) 2SWS (FSPH=1, FSLN =0) t DFS t DFS t DFS t DFS t DFS t DFS 2SWS (FSPH=0, FSLN =1) 2SWS (FSPH=1, FSLN =1) t DFS t DDO t DFS 2SDO 2SD (SMPL= 0 ) 2SD (SMPL= 1 ) t SD t HD t SD t HD t SD t HD Note: See Chapter 7-2: 2 S(nter-C Sound bus)nterface in FM4 Family Peripheral Manual Communication part ( ) for the details of CPOL, FSPH, FSLN, SMPL. 2SD 0. 8 V CC 0. 8 V CC 0.2 V CC 0. 8 V CC 0. 2 V CC t F t R Document Number: Rev.*C Page 147 of 182

148 Slave Mode Timing Parameter Symbol Pin Name Conditions Min Value nput frequency tscyc 2SCK MHz nput clock pulse width tshw % 2SCK - tslw % 2SWS 2SCK 2SCK, tsf Setup time 2SWS ns 2SWS 2SCK 2SCK, thf Hold time 2SWS ns 2SCK 2SDO Delay time *1 tddo ns 2SCK, 2SDO 2SCK 2SDO Delay Time *2 tdfb ns 2SD 2SCK tsd ns Setup time 2SCK, 2SD 2SD 2SCK thd ns Hold time nput signal rising time tr 2SCK, ns nput signal falling time tf 2SWS,2SD ns *1: Except for the first bit of transmission frame *2: When FSPH register 1. Notes: When the external load capacitance CL = 20 pf (VCC = 2.7V to 3.6V, VSS = 0V) Max Unit Remarks When 2SWS=48 khz, 2MCLK=256 2SWS Frame synchronization signal (2SWS) is settable to 48 khz, 32 khz, 16 khz. See Chapter 7-2: 2 S(nter-C Sound bus)nterface in FM4 Family Peripheral Manual Communication part ( ) for the details. Document Number: Rev.*C Page 148 of 182

149 t SCYC 2 SCK ( CPOL=0 ) t SHW t SLW 2 SCK ( CPOL=1 ) 2SWS (FSPH= 0, FSLN = 0 ) 2SWS (FSPH= 1, FSLN = 0 ) 2SWS (FSPH= 0, FSLN = 1 ) t SF t HF t SF t t t SF HF SF 2SWS (FSPH= 1, FSLN = 1 ) 2SDO t DFB1 1 t DDO t SD t HD t SD t HD 2SD (SMPL= 0 ) 2SD (SMPL= 1 ) t SD t HD Notes: See Chapter 7-2: 2 S(nter-C Sound bus)nterface in FM4 Family Peripheral Manual Communication part ( ) for the details of FSPH, FSLN, SMPL 2SCK is selectable polarity by CPOL bit of CNTREG register 2SCK 2SWS 2SD 0. 8 V CC 0. 8 V CC 0.2 V CC 0. 8 V CC 0. 2 V CC t F t R Document Number: Rev.*C Page 149 of 182

150 2SMCLK nput Characteristics (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Name Conditions Min Value Max Unit Remarks nput frequency fchs 2SCK MHz nput clock cycle tcylhs ns nput clock pulse width - - nput clock rising time and falling time tcfs tcrs PWHS/tCYLHS PWLS/tCYLHS % ns When using external clock When using external clock t CYLHS 2SMCLK 0.8 V CC 0.8 V CC 0.8 V CC 0.2 V CC 0.2 V CC P WHS t CFS P WLS t CRS 2SMCLK Output Characteristics (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Name Conditions Min Value Max Unit Remarks nput frequency fchs 2SCK MHz Document Number: Rev.*C Page 150 of 182

151 GDC:Panel Output Timing Parameter Symbol Pin Name Conditions Min (VCC = 3.0V to 3.6V, VSS = 0V) Value Unit Max Output frequency tcycpnge PNL_DCLK MHz PNL_DCLK PNL_PD[23:0] Output delay time PNL_DCLK PNL_LH_SYN C Output delay time PNL_DCLK PNL_FV_SYN C Output delay time PNL_DCLK PNL_LE Output delay time PNL_DCLK PNL_DEN Output delay time PNL_DCLK PNL_PWE Output delay time tpdopdge PNL_PD[23:0] ns thdopdge PNL_LH_SYNC ns tvdopdge PNL_FV_SYNC ns tldopdge PNL_LE ns tddopdge PNL_DEN ns tpdopdge PNL_PWE ns PNL_DCLK t CYCPNGE PNL_PD[23:0] t PDOPDGE PNL_LHSYNC PNL_FVSYNC t HDOPDGE PNL_LE t VDOPDGE t LDOPDGE PNL_DEN t DDOPDGE PNL_PWE t PDOPDGE Document Number: Rev.*C Page 151 of 182

152 GDC: SDRAM-F Timing (VCC = 3.0V to 3.6V, VSS = 0V) Parameter Symbol Pin Name Min Value Max Unit Output frequency tcycsd GE_SDCLK - 80 MHz Address delay time taosd GE_SDCLK GE_SDA[11:0] 1 5 ns Bank address delay time tbaosd GE_SDCLK GE_SDBA[1:0] 1 5 ns GE_SDCLK Data output delay time tdosd GE_SDCLK GE_SDDQ[31:0] 1 5 ns GE_SDCLK Data output Hi-Z time tdozsd GE_SDCLK GE_SDDQ[31:0] 1 5 ns GE_SDDQM[3:0] delay time twrosd GE_SDCLK GE_SDDQM[3:0] 1 5 ns GE_SDCSX delay time tscssd GE_SDCLK GE_SDCSX 1 5 ns GE_SDRASX delay time trassd GE_SDCLK GE_SDRASX 1 5 ns GE_SDCASX delay time tcassd GE_SDCLK GE_SDCASX 1 5 ns GE_SDWEX delay time tswesd GE_SDCLK GE_SDWEX 1 5 ns GE_SDCKE delay time tckesd GE_SDCLK GE_SDCKE 1 5 ns Data setup time tdssd GE_SDCLK GE_SDDQ[31:0] 4 - ns Data hold time tdhsd GE_SDCLK GE_SDDQ[31:0] 0 - ns Document Number: Rev.*C Page 152 of 182

153 t CYCSD GE_SDCLK t AOSD GE_SDA[11:0] Address t BAOSD GE_SDBA[1:0] Address t WROSD GE_SDDQM[3:0] t SCSSD GE_SDCSX t RASSD GE_SDRASX t CASSD GE_SDCASX t SWESD GE_SDWEX t CKESD GE_SDCKE t DSSD t DHSD GE_SDRASX t DOSD RD t DOZSD GE_SDRASX WD Document Number: Rev.*C Page 153 of 182

154 GDC: High-Speed Quad SP Timing Parameter Symbol Pin Name Conditions Serial clock frequency tscycm GE_SPCK (VCC = 3.0V to 3.6V, VSS = 0V) Value Unit Min Max - 80 MHz Enabled CS CLK Starting Time (mode0/mode2) toslsk tscycm ns Enabled CS CLK Starting Time (mode1/mode3) CLK Last Disabled CS Time (mode0/mode2) CLK Last Disabled CS Time (mode1/mode3) toslsk13 tscycm ns GE_SPCK, GE_SPCSX0 tosksl02 CL=20 pf tscycm - ns tosksl tscycm - ns SO Data output time tosdat GE_SPCK, ns SO Setup tdsset GE_SPDQ0, GE_SPDQ1, GE_SPDQ2, 4 - ns GE_SPDQ3 SO Hold tsdhold 0.5 tscycm - ns Note: See Chapter 8-3: High-Speed Quad SP controller in FM4 Family Peripheral Manual Communication part ( ) for the detail of RTM mode. Document Number: Rev.*C Page 154 of 182

155 GE_SPCSX0 t SCYCM GE_SPCK mode0 mode2 t OSLSK02 t OSKSL02 mode1 mode3 t OSLSK13 t OSKSL13 GE_SPDQ0, GE_SPDQ1, GE_SPDQ2, GE_SPDQ3 tdsset output tsdhold tosdat Document Number: Rev.*C Page 155 of 182

156 GDC: HyperBus /F Timing HyperFlash Write (VCC = 3.0V to 3.6V, VSS = 0V) Parameter Symbol Pin Name Conditions Min Value Max Unit Hyper Bus clock cycle tckcyc GE_HBCK CS CK Chip Select setup time CS RDS Chip select active to RDS valid(low) DQ CK nput setup time CK DQ nput hold time CK CS Chip select hold time CS RDS(Hi-z) Chip select nactive to RDS High-Z CS CS Chip select HGH between operation tcss GE_HBCSX1 GE_HBCSX0 CL=30 pf 10 - ns 3 - ns tdsv GE_HBRWDS - 8 ns ts th tcsh tdsz tcsh GE_HBDQ7- GE_HBDQ0 GE_HBDQ7- GE_HBDQ0 GE_HBCSX1 GE_HBCSX0 GE_HBCSX1 GE_HBCSX0 GE_HBCSX1 GE_HBCSX ns ns 0 - ns - 7 ns 8 - ns t CSH GE_HBCSX0,1 V OL V OH GE_HBCK t CSS V OL V OH t CKCYC t CSH t CSS t DSV t DSZ GE_HBRWDS t S t H V H GE_HBDQ7-0 CA CA CA CA CA CA2 7-0 Dn 15-8 Dn 7-0 V L Document Number: Rev.*C Page 156 of 182

157 HyperFlash Read (VCC = 3.0V to 3.6V, VSS = 0V) Parameter Symbol Pin Name Conditions Min Value Max Unit Hyper Bus clock cycle trdscyc GE_HBCK 10 - ns Read initial Access Time tacc GE_HBCK ns CS CK Chip Select setup time CS RDS Chip select active to RDS valid (Low) DQ CK nput setup time CK DQ nput hold time CK CS Chip select hold time CS RDS(Hi-Z) Chip select nactive to RDS High-Z CK DQ (Low Z) Clock to DQs Low Z RDS DQ (valid) RDS transition to DQ valid RDS DQ (invalid) RDS transition to DQ invalid CS DQ (Hi-Z) Chip select nactive to DQs High-Z CK RDS CK transition to RDS transition CS CS Chip select HGH between Operation tcss GE_HBCSX1 GE_HBCSX0 3 - ns tdsv GE_HBRWDS - 8 ns ts GE_HBDQ7- GE_HBDQ ns th GE_HBDQ7- GE_HBDQ ns GE_HBCSX1 tcsh 0 - ns GE_HBCSX0 CL=30pF tdsz GE_HBRWDS - 7 ns tdqlz tdss tdsh toz GE_HBDQ7- GE_HBDQ0 GE_HBDQ7- GE_HBDQ0 GE_HBDQ7- GE_HBDQ0 GE_HBDQ7- GE_HBDQ0 0 - ns ns ns - 7 ns tckds GE_HBRWDS 1 7 ns tcsh GE_HBCSX1 GE_HBCSX0 8 - ns t CSH t ACC GE_HBCSX0,1 V OL V OH GE_HBCK t CSS V OH t CSH t CSS V OL t DSV t DQLZ t CKDS t RDSCYC t DSZ GE_HBRWDS V OH t OZ t H t S t DSH t DSS V H V OH GE_HBDQ7-0 CA CA CA CA CA CA2 7-0 Dn 15-8 Dn 7-0 Dn Dn V L V OL Document Number: Rev.*C Page 157 of 182

158 bit A/D Converter Electrical Characteristics for the A/D Converter (VCC = AVCC = 2.7V to 3.6V, VSS = AVSS = AVRL = 0V) Parameter Symbol Pin Value Name Min Typ Max Unit Resolution bit ntegral Nonlinearity ± 4.5 LSB Differential Nonlinearity ± 2.5 LSB Zero transition voltage VZT ANxx - ± 2 ± 7 LSB Full-scale transition AVRH ± VFST ANxx - voltage 2 AVRH ± 7 LSB Total error ± 3 ± 8 LSB Conversion time *1 - - μs Sampling time *2 ts μs Remarks AVRH=2.7 V to 3.6 V Offset calibration when used Compare clock cycle*3 tcck ns State transition time to operation permission Power supply current (analog + digital) Reference power supply current(avrh) tstt μs - AVCC - AVRH ma A/D 1unit operation μa When A/D stop A/D 1unit ma operation AVRH=3.3 V μa When A/D stop Analog capacity CAN pf Analog resistance RAN kω nterchannel disparity LSB Analog port leak current - ANxx μa Analog voltage - ANxx AVSS - AVRH V AVSS - AVCC V Reference voltage - AVRH AVCC V tcck 50 ns - AVRL AVSS - AVSS V *1: The conversion time is the value of sampling time (ts) + compare time (tc). Ensure that it satisfies the value of sampling time (ts) and compare clock cycle (tcck). For setting of sampling time and compare clock cycle, see Chapter 1-1: A/D Converter in FM4 Family Peripheral Manual Analog Macro Part ( ). The register setting of the A/D converter is reflected by the APB bus clock timing. For more information about the APB bus signal to which the A/D converter is connected, see 10. Block Diagram in this data sheet. The sampling clock and compare clock are set at base clock (HCLK). *2: A necessary sampling time changes by external impedance. Ensure that it set the sampling time to satisfy (Equation 1). *3: The compare time (tc) is the value of (Equation 2). Document Number: Rev.*C Page 158 of 182

159 ANxx Analog pin Comparator Analog signal source REXT R AN Cin C AN (Equation 1) ts (RAN + REXT) CAN 9 ts: Sampling time RAN: nput resistance of A/D = 1.8 kω CAN: nput capacity of A/D = pf REXT: Output impedance of external circuit (Equation 2) tc = tcck 14 tc: tcck: Compare time Compare clock cycle Document Number: Rev.*C Page 159 of 182

160 Digital output Digital output S6E2D5 Series Definition of 12-bit A/D Converter Terms Resolution: ntegral Nonlinearity: Differential Nonlinearity: Analog variation that is recognized by an A/D converter. Deviation of the line between the zero-transition point (0b b ) and the full-scale transition point (0b b ) from the actual conversion characteristics. Deviation from the ideal value of the voltage that is required to change the output code by 1 LSB. ntegral Nonlinearity Differential Nonlinearity 0xFFF 0xFFE 0xFFD 0x004 0x003 0x002 0x001 Actual conversion characteristics {1 LSB(N-1) + VZT} (Actuallymeasured value) (Actually-measured value) Actual conversion characteristics deal characteristics VZT VNT VFST (Actually-measured value) 0x(N+1) 0xN 0x(N-1) 0x(N-2) Actual conversion characteristics deal characteristics VNT V(N+1)T (Actually-measured value) (Actually-measured value) Actual conversion characteristics AVss AVRH AVss AVRH Analog Analog ntegral Nonlinearity of digital output N = VNT - {1LSB (N - 1) + VZT} 1LSB [LSB] Differential Nonlinearity of digital output N = V(N + 1) T - VNT 1LSB - 1 [LSB] 1LSB = VFST - VZT 4094 N: A/D converter digital output value. VZT: Voltage at which the digital output changes from 0x000 to 0x001. VFST : Voltage at which the digital output changes from 0xFFE to 0xFFF. VNT: Voltage at which the digital output changes from 0x(N 1) to 0xN. Document Number: Rev.*C Page 160 of 182

161 Total error: A difference between actual value and theoretical value. The overall error includes zero-transition voltage, full-scale transition voltage and linearity error. Total error 0xFFF Digital output 0xFFE 0xFFD 0x004 0x003 0x002 Actual conversion characteristics {1LSB x (N-1) LSB } Actual conversion characteristics V FST =1.5LSB V NT (Actually-measured value) deal characterisics V ZT =0.5LSB 0x001 AVRL Analog AVRH Total error of digital output N = V NT {1 LSB X (N-1) LSB } 1 LSB [LSB] 1 LSB (ideal value) = AVRH AVRL 4096 [V] V ZT (ideal value) = AVRL LSB [V] V FST (ideal value) = AVRH LSB [V] V NT : A voltage for causing transition of digital output from (N-1) to N Document Number: Rev.*C Page 161 of 182

162 12.6 USB Characteristics nput characteristi cs Output characteristi cs Parameter Symbol Pin Name Conditions (VCC = 3.0V to 3.6V, VSS = 0V) Value Min Max nput H level voltage VH VCC V *1 nput L level voltage VL - VSS V *1 Differential sensitivity VD V *2 Different common mode range VCM V *2 External pullup Output H level voltage VOH resistance V *3 = 15kΩ External pullup resistance = 15kΩ Output L level voltage VOL UDP0/ UDM V *3 Crossover voltage VCRS V *4 Rising time tfr Full-Speed 4 20 ns *5 Falling time tff Full-Speed 4 20 ns *5 Rising/falling time matching tfrfm Full-Speed % *5 Output impedance ZDRV Full-Speed Ω *6 Rising time tlr Low-Speed ns *7 Falling time tlf Low-Speed ns *7 Rising/falling time matching tlrfm Low-Speed % *7 *1: The switching threshold voltage of Single-end-receiver of USB /O buffer is set as within VL (Max) = 0.8 V, VH (Min) = 2.0 V (TTL standard). There are some hysteresis to lower noise sensitivity. *2: Use differential-receiver to receive USB differential data signal. Differential-receiver has 200 mv of differential sensitivity when the differential data is within 0.8 V to 2.5 V to the local ground reference level. Above voltage range is the common mode voltage range. Unit Remarks Minimum differential sensitivity [V] Common mode voltage [V] *3: The output drive capability of the driver is below 0.3 V at Low- (VOL) (to 3.6 V and 1.5 kω load), and 2.8 V or above (to the VSS and 15 kω load) at High-State (VOH). *4: The cross voltage of the external differential output signal (D + /D ) of USB /O buffer is within 1.3 V to 2.0 V. Document Number: Rev.*C Page 162 of 182

163 D+ Max 2.0 V Min 1.3 V D- VCRS specified range *5: They indicate Rising time (tfr) and Falling time (tff) of the Full-speed differential data signal. They are defined by the time between 10 % and 90 % of the output signal voltage. For Full-speed buffer, tfr/tff ratio is regulated as within ± 10 % to minimize RF emission. D+ 90% 90% D- 10% 10% tfr Rising time tff Falling time Full-speed Buffer Rs=27Ω TxD+ C L =50pF TxD- Rs=27Ω 3-State Enable C L =50pF Document Number: Rev.*C Page 163 of 182

164 *6: USB Full-speed connection is performed via twist pair cable shield with 90 Ω ± 15 % characteristic impedance (Differential Mode). USB standard defines that output impedance of USB driver must be in range from 28 Ω to 44 Ω. So, discrete series resistor (Rs) addition is defined in order to satisfy the above definition and keep balance. When using this USB /O, use it with 25 Ω to 30 Ω (recommendation value 27 Ω) Series resistor Rs. 28Ω to 44Ω Equiv. mped. 28Ω to 44Ω Equiv. mped. Mount it as external resistance. Rs series resistor 25 Ω to 30 Ω Series resistor of 27 Ω (recommendation value) must be added. And, use "resistance with an uncertainty of 5% by E24 sequence". *7: They indicate rising time (tlr) and Falling time (tlf) of the Low-speed differential data signal. They are defined by the time between 10 % and 90 % of the output signal voltage. D+ 90% 90% D- 10% 10% tlr Rising time tlf Falling time Note: See Low-speed load (Compliance load) for conditions of external load. Document Number: Rev.*C Page 164 of 182

165 Low-speed load (Upstream port load) - Reference 1 CL = 50pF to 150pF CL = 50pF to 150pF Low-speed load (Downstream port load) - Reference 2 CL = 200pF to 600pF CL = 200pF to 600pF Low-speed load (Compliance load) CL = 200pF to 450pF CL = 200pF to 450pF Document Number: Rev.*C Page 165 of 182