MB91F355A/F353A/F356B/355A/354A/ MB91353A/352A/351A/V350A

Transcription

1 FUJITSU SEMICONDUCTOR DATA SHEET DS E 32-Bit Proprietary Microcontroller CMOS FR60 MB91F355A/F353A/F356B/355A/354A/ MB91353A/352A/351A/V350A DESCRIPTION The FR families are lines of standard single-chip microcontrollers each based on a 32-bit high-performance RISC CPU, incorporating a variety of I/O resources and bus control features for embedded control applications which require high CPU performance for high-speed processing. This FR60 is based on FR30 and FR40 CPU and enhanced bus access. The FR60 is a line of single-chip oriented microcontrollers incorporating a wealth of peripheral resources. The FR60 family is optimized for embedded control applications requiring high processing power of the CPU, such as DVD player, navigation, high performance Fax machine, and printer controls. FEATURES 1. FR CPU 32-bit RISC, load/store architecture with a five-stage pipeline Maximum operating frequency: 50 MHz (using the PLL at an oscillation frequency of 12.5 MHz) 16-bit fixed length instructions (basic instructions), 1 instruction per cycle Instruction set optimized for embedded applications: Memory-to-memory transfer, bit manipulation, barrel shift etc. Instructions adapted for high-level languages : Function entry/exit instructions, multiple-register load/store instructions Register interlock functions: Facilitating coding in assemblers (Continued) Be sure to refer to the Check Sheet for the latest cautions on development. Check Sheet is seen at the following support page URL : Check Sheet lists the minimal requirement items to be checked to prevent problems beforehand in system development. Copyright FUJITSU LIMITED All rights reserved

2 On-chip multiplier supported at the instruction level. Signed 32-bit multiplication: 5 cycles Signed 16-bit multiplication: 3 cycles Interrupt (PC, PS save): 6 cycles, 16 priority levels Harvard architecture allowing program access and data access to be executed simultaneously 2. Bus interface Maximum operating frequency: 25 MHz 24-bit address full output (16M bytes space) capability (21-bit address full output (2M bytes space) capability: MB91F353A/353A/352A/351A) 8,16-bit data output Built-in pre-fetch buffer Non-used data and address pin are usable as general I/O port. Capable of chip-select signal output for completely independent four areas settable in 64K bytes minimum Support for various memory interfaces: SRAM, ROM/Flash page mode Flash ROM, page mode ROM interface Basic bus cycle : 2 cycles Programmable automatic wait cycle generator capable of inserting wait cycles for each area RDY input for external wait cycles DMA support of fly-by transfer capable of wait control for independent I/O (The MB91F353A/353A/352A/351A does not support fly-by transfer.) 3. Mounted memory D-bus memory MB91V350A MB91F353A MB91F355A MB91F356B MB91353A MB91355A 4. DMAC (DMA Controller) Capable of simultaneous operation of up to 5 channels (external external: 3 channels) 3 transfer sources (external pin/internal peripheral or software): Activation sources are software-selectable (transfer can be activated by UART0/1/2). Addressing using 32-bit full addressing mode (increment, decrement, fixed) Transfer modes (demand transfer, burst transfer, step transfer, block transfer) Fly-by transfer support (external I/O and between memories) Selectable transfer data size: 8, 16, or 32-bit Multi-byte transfer enabled (by software) DMAC descriptor in IO areas (200H to 240H, 1000H to 1024H) (The MB91F353A/353A/352A/351A does not have an external interface.) External pin transfer is not supported. Demand transfer and fly-by transfer cannot be used. 5. Bit search module (for REALOS) Search for the position of the bit 1/0-changed first in 1 word from the MSB MB91352A MB91354A MB91351A ROM No 512 KB 256 KB 512 KB 384 KB 384 KB RAM (stack) 16 KB 16 KB 16 KB 16 KB 8 KB 16 KB RAM (Execute instruction) 16 KB 8 KB 8 KB 8 KB 8 KB 8 KB (Continued) 2

3 6. Various timers 4 channels of 16-bit reload timer (including 1 channel for REALOS) : Internal clock frequency selectable from among divisions by 2/8/32 (division by 64/128 selectable only for ch.3) 16-bit free-running timer : 1 channel. Output compare : 8 channels (MB91F353A/353A/352A/351A: 2 channels) Input capture : 4 channels. 16-bit PPG timer : 6 channels (MB91F353A/353A/352A/351A: 3 channels) 7. UART UART Full duplex double buffer: 5 channels (MB91F353A/353A/352A/351A: 4 channels) Selectable parity On/Off Asynchronous (start-stop synchronized) or CLK-synchronous communications selectable Internal timer for dedicated baud rate External clock can be used as transfer clock Assorted error detection functions (for parity, frame, and overrun errors) Support for 115 Kbps 8. SIO 8-bit data serial transfer: 3 channels (MB91F353A/353A/352A/351A: 2 channels) Shift clock selectable from among internal three and external one Shift direction selectable (transfer from LSB or MSB) selectable 9. Interrupt controller Total number of external interrupts: 17 (MB91F353A/353A/352A/351A: 9) (One non-maskable interrupt pin and 16/8 ordinary interrupt pins that can be used for wakeup in stop mode.) interrupt from internal peripheral Programmable priorities (16 levels) for all interrupts except the non-maskable interrupt 10. D/A converter 8-bit resolution: 3 channels (MB91F353A/353A/352A/351A: 2 channels) 11. A/D converter 10-bit resolution: 12 channels (MB91F353A/353A/352A/351A: 8 channels) Casting time for serial/parallel conversion: 1.48 µs Conversion mode (single conversion mode, continuous conversion mode) Activation source (software, external trigger, peripheral interrupt) 12. Other interval timer/counter 8/16-bit up/down counter The MB91F353A/353A/352A/351A supports only an 8-bit up/down counter. 16-bit timer (U-TIMER): 5 channels (MB91F353A/353A/352A/351A: 4 channels) Watch dog timer 13. I 2 C bus interface* (400 kbps supported) 1 channel master/slave sending and receiving Arbitration and clock synchronization 14. I/O port 3 V I/O ports (5 V input is supported for those ports that are also used for external interrupts (16 ports, MB91F353A/353A/ 352A/351A: 8 ports). Up to 126 ports (MB91F353A/353A/352A/351A: Up to 84 ports) (Continued) 3

4 (Continued) 15. Other features Internal oscillator circuit as clock source, allowing PLL multiplication to be selected Provided with INIT as a reset pin (The CPU operates without oscillation stabilization wait interval when the INIT pin is reset.) others, watch-dog timer reset, software reset enable Support for stop and sleep modes for low power consumption, capable of saving power during CPU operation at 32 khz. Gear function Built-in time base timer Package: MB91F355A/F356B/355A/354A: LQFP-176 (lead pitch 0.50 mm) MB91F353A/353A/352A/351A: LQFP-120 (lead pitch 0.50 mm) CMOS technology(0.35 µm) Power supply voltage: 3.3 V ± 0.3 V *: Purchase of Fujitsu I 2 C components conveys a license under the Philips I 2 C Patent Rights to use, these components in an I 2 C system provided that the system conforms to the I 2 C Standard Specification as defined by Philips. 4

5 5 PIN ASSIGNMENTS MB91F353A/353A/352A/351A (TOP VIEW) (FPT-120P-M21) P20/D16 P21/D17 P22/D18 P23/D19 P24/D20 P25/D21 P26/D22 P27/D23 P30/D24 P31/D25 P32/D26 P33/D27 P34/D28 P35/D29 P36/D30 P37/D31 P40/A00 VSS VCC P41/A01 P42/A02 P43/A03 P44/A04 P45/A05 P46/A06 P47/A07 P50/A08 P51/A09 P52/A10 P53/A P54/A12 P55/A13 P56/A14 P57/A15 P60/A16 P61/A17 P62/A18 P63/A19 P64/A20 VSS PL1/SCL PL0/SDA VSS VCC P80/IN0/RDY P81/IN1/BGRNT P82/IN2/BRQ P83/RD P84/WR0 P85/IN3/WR1 NMI MD2 MD1 MD0 INIT VCC X1 X0 VSS X0A AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 VSS AVSS/AVRL AVRH AVCC DAVC DAVS DA0 DA1 PH5/SCK3 PH4/SO3 PH3/SI3 PH2/SCK2 PH1/SO2 PH0/SI2 PO2/OC2 PO0/OC0 VSS VCC PI5/SCK1 PI4/SO1 PI3/SI1 PI2/SCK PI1/SO0 PI0/SI0 PK7/INT7/ATG PK6/INT6/FRCK PK5/INT5 PK4/INT4 PK3/INT3 PK2/INT2 PK1/INT1 PK0/INT0 PM5/SCK7 PM4/SO7/TRG4 PM3/SI7/TRG3 VCC VSS PM2/SCK6/ZIN0/TRG2 PM1/SO6/BIN0/TRG1 PM0/SI6/AIN0/TRG0 PN4/PPG4 PN2/PPG2 PN0/PPG0 PA3/CS3 PA2/CS2 PA1/CS1 PA0/CS0 P94/AS P93 P91 P90/SYSCLK X1A

6 6 MB91F355A/F356B/355A/354A (TOP VIEW) (FPT-176P-M02) PG5/SCK5 NMI X1A VSS X0A MD2 MD1 MD0 X0 VCC X1 INIT VSS VCC PC0/DREQ2 PC1/DACK2 PC2/DSTP2/DEOP2 PB0/DREQ0 PB1/DACK0 PB2/DSTP0/DEOP0 PB3/DREQ1 PB4/DACK1 PB5/DSTP1/DEOP1 PB6/IOWR PB7/IORD PA0/CS0 PA1/CS1 PA2/CS2 PA3/CS3 VSS VCC P80/IN0/RDY P81/IN1/BGRNT P82/IN2/BRQ P83/RD P84/WR0 P85/IN3/WR1 P90/SYSCLK P91 P92/MCLK P93 P94/AS VSS VCC P20/D16 P21/D17 P22/D18 P23/D19 P24/D20 P25/D21 P26/D22 P27/D23 P30/D24 P31/D25 P32/D26 P33/D27 P34/D28 P35/D29 P36/D30 P37/D31 VSS VCC P40/A00 P41/A01 P42/A02 P43/A03 P44/A04 P45/A05 P46/A06 P47/A07 P50/A08 P51/A09 P52/A10 P53/A11 P54/A12 P55/A13 P56/A14 P57/A15 VSS VCC P60/A16 P61/A17 P62/A18 P63/A19 P64/A20 P65/A21 P66/A22 P67/A23 PG4/SO5 PG3/SI5 PG2/SCK4 PG1/SO4 PG0/SI4 PH5/SCK3 PH4/SO3 PH3/SI3 PH2/SCK2 PH1/SO2 PH0/SI2 PI5/SCK1 PI4/SO1 PI3/SI1 PI2/SCK0 PI1/SO0 PI0/SI0 VCC VSS PJ7/INT15 PJ6/INT14 PJ5/INT13 PJ4/INT12 PJ3/INT11 PJ2/INT10 PJ1/INT9 PJ0/INT8 PK7/INT7/ATG PK6/INT6/FRCK PK5/INT5 PK4/INT4 PK3/INT3 PK2/INT2 PK1/INT1 PK0/INT0 VCC VSS PL1/SCL PL0/SDA VSS PM5/SCK7/ZIN1/TRG5 PM4/SO7/BIN1/TRG4 PM3/SI7/AIN1/TRG3 PM2/SCK6/ZIN0/TRG PM1/SO6/BIN0/TRG1 PM0/SI6/AIN0/TRG0 PN5/PPG5 PN4/PPG4 PN3/PPG3 PN2/PPG2 PN1/PPG1 PN0/PPG0 VCC VSS PO7/OC7 PO6/OC6 PO5/OC5 PO4/OC4 PO3/OC3 PO2/OC2 PO1/OC1 PO0/OC0 PP3/TOT3 PP2/TOT2 PP1/TOT1 PP0/TOT0 VCC VSS AVSS/AVRL AVRH AVCC AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 DA2 DA1 DA0 DAVC DAVS

7 PIN DESCRIPTION Pin no. LQFP* 1 LQFP* 2 1 to 8 1 to 8 9 to 16 9 to to 26 17, 20 to to to to to to 44 - Pin name D16 to D23 P20 to P27 D24 to D31 P30 to P37 A00 to A07 P40 to P47 A08 to A15 P50 to P57 A16 to A20 P60 to P64 A21 to A23 I/O circuit type* 3 C C C C C C Function Bits 16 to bit 23 of the external data bus. Valid only in external bus mode. Can be used as a port in external bus 8-bit mode. Bits 24 to bit 31 of the external data bus. Valid only in external bus mode. Can be used as a port in single-chip mode. Bits 0 to bit 7 of the external address bus. Valid only in external bus mode. Can be used as a port in single-chip mode. Bits 8 to bit 15 of the external address bus. Valid only in external bus mode. Can be used as a port in single-chip mode. Bits 16 to bit 20 of the external address bus. Valid only in external bus mode. Can be used as a port in single-chip mode or when an external address bus is not used. Bits 21 to bit 23 of the external address bus. Valid only in external bus mode. P65 to P67 Can be used as a port in single-chip mode or when an external address bus is not used. 47, ,105 DA0, DA1 - D/A converter output pin 49 - DA2 - D/A converter output pin 50 to to 120 AN0 to AN7 G Analog input pin 58 to 61 - AN8 to AN11 G Analog input pin 67 to TOT0 to TOT3 PP0 to PP3 OC0 PO0 D D Reload timer output ports. This function is valid when timer output is enabled. General-purpose I/O ports. This function is valid when the timer output function is disabled. Output compare output pin General-purpose I/O port. This function can be used as a port when output compare output is not used. (Continued) 7

8 Pin no. LQFP* 1 LQFP* 2 Pin name I/O circuit type* 3 Function OC1 Output compare output pin 72 - PO1 D General-purpose I/O port. This function can be used as a port when output compare output is not used. OC2 Output compare output pin PO2 D General-purpose I/O port. This function can be used as a port when output compare output is not used. OC3 to OC7 Output compare output pins 74 to 78 - PO3 to PO7 D General-purpose I/O ports. This function can be used as a port when output compare output is not used. PPG0 PPG timer output pin PN0 D General-purpose I/O port. This function can be used as a port when PPG timer output is not used. PPG1 PPG timer output pin 82 - PN1 D General-purpose I/O port. This function can be used as a port when PPG timer output is not used. PPG2 PPG timer output pin PN2 D General-purpose I/O port. This function can be used as a port when PPG timer output is not used. PPG3 PPG timer output pin 84 - PN3 D General-purpose I/O port. This function can be used as a port when PPG timer output is not used. PPG4 PPG timer output pin PN4 D General-purpose I/O port. This function can be used as a port when PPG timer output is not used. PPG5 PPG timer output pin 86 - PN5 D General-purpose I/O port. This function can be used as a port when PPG timer output is not used. (Continued) 8

9 Pin no. LQFP* 1 LQFP* 2 Pin name I/O circuit type* 3 Function SI6 Data input for serial I/O6. Since this input is always used when serial I/O6 input is operating, output using the port must be stopped beforehand unless this operation is the intended operation AIN0 TRG0 D Input for the up/down counter. Since this input is always used when input is allowed, output using the port must be stopped beforehand unless this operation is the intended operation. External trigger input for PPG timer 0. Since this input is always used when input is allowed, output using the port must be stopped beforehand unless this operation is the intended operation. PM0 General-purpose I/O port. This function can be used as a port when serial I/O, up/down counter, and PPG timer output are not used. SO6 Data output from serial I/O6. This function is valid when data output from serial I/O6 is allowed BIN0 TRG1 D Input for the up/down counter. Since this input is always used when input is allowed, output using the port must be stopped beforehand unless this operation is the intended operation. External trigger input for PPG timer 1. Since this input is always used when input is allowed, output using the port must be stopped beforehand unless this operation is the intended operation. PM1 General-purpose I/O port. This function can be used as a port when serial I/O, up/down counter, and PPG timer output are not used. SCK6 Clock I/O for serial I/O6. This function is valid when clock output from serial I/O6 is allowed or when external shift clock input is used ZIN0 TRG2 D Input for the up/down counter. Since this input is always used when input is allowed, output using the port must be stopped beforehand unless this operation is the intended operation. External trigger input for PPG timer 2. Since this input is always used when input is allowed, output using the port must be stopped beforehand unless this operation is the intended operation. PM2 General-purpose I/O port. This function can be used as a port when serial I/O, up/down counter, and PPG timer output are not used. (Continued) 9

10 Pin no. LQFP* 1 LQFP* Pin name SI7 AIN1* 4 TRG3 PM3 S07 BIN1* 4 TRG4 PM4 SCK7 ZIN1* 4 I/O circuit type* 3 D D D Function Data input for serial I/O7. Since this input is always used when serial I/O7 input is operating, output using the port must be stopped beforehand unless this operation is the intended operation. Input for the up/down counter. Since this input is always used when input is allowed, output using the port must be stopped beforehand unless this operation is the intended operation. External trigger input for PPG timer 3. Since this input is always used when input is allowed, output using the port must be stopped beforehand unless this operation is the intended operation. General-purpose I/O port. This function can be used as a port when serial I/O, up/down counter, and PPG timer output are not used. Data output from serial I/O7. This function is valid when data output from serial I/O7 is allowed. Input for the up/down counter. Since this input is always used when input is allowed, output using the port must be stopped beforehand unless this operation is the intended operation. External trigger input for PPG timer 4. Since this input is always used when input is allowed, output using the port must be stopped beforehand unless this operation is the intended operation. General-purpose I/O port. This function can be used as a port when serial I/O, up/down counter, and PPG timer output are not used. Clock I/O for serial I/O7. This function is valid when clock output from serial I/O7 is allowed or when external shift clock input is used. Input for the up/down counter. Since this input is always used when input is allowed, output using the port must be stopped beforehand unless this operation is the intended operation. External trigger input for PPG timer 5. Since this input is always used when input is allowed, output TRG5* 4 using the port must be stopped beforehand unless this operation is the intended operation. General-purpose I/O port. PM5 This function can be used as a port when serial I/O, up/down counter, and PPG timer output are not used. (Continued) 10

11 Pin no. LQFP* 1 LQFP* 2 Pin name I/O circuit type* 3 Function SDA F DATA I/O pin for the I 2 C bus. This function is valid when the I 2 C is allowed to operate in standard mode. Output using the port must be stopped beforehand unless this operation is intended (open drain output). PL0 General-purpose I/O port. This function can be used as a port when I 2 C operation is not allowed (open drain output) SCL F Clock I/O pin for the I 2 C bus. This function is valid when the I 2 C is allowed to operate in standard mode. Output using the port must be stopped beforehand unless this operation is intended (open drain output). PL1 General-purpose I/O port. This function can be used as a port when I 2 C operation is not allowed (open drain output). 98 to to 86 INT0 to INT5 E External interrupt input. Since this input is always used when the corresponding external interrupt is allowed, output using the port must be stopped beforehand unless this operation is the intended operation. PK0 to PK5 General-purpose I/O ports INT6 External interrupt input. Since this input is always used when the corresponding external interrupt is allowed, output using the port must be stopped beforehand unless this operation is the intended operation FRCK E External clock input pin for the free-running timer. Since this input is always used when it is selected as external clock input for the free-running timer, output using the port must be stopped beforehand unless this operation is the intended operation. PK6 General-purpose I/O port INT7 External interrupt input. Since this input is always used when the corresponding external interrupt is allowed, output using the port must be stopped beforehand unless this operation is the intended operation ATG E External trigger for the A/D converter. Since this input is always used when it is selected as the source of A/D activation, output using the port must be stopped beforehand unless this operation is the intended operation. PK7 General-purpose I/O port (Continued) 11

12 Pin no. LQFP* 1 LQFP* 2 Pin name I/O circuit type* 3 Function 106 to INT8 to INT15 E External interrupt input. Since this input is always used when the corresponding external interrupt is allowed, output using the port must be stopped beforehand unless this operation is the intended operation. PJ0 to PJ7 General-purpose I/O ports SI0 D Data input for UART0. Since this input is always used when UART0 input is operating, output using the port must be stopped beforehand unless this operation is the intended operation. PI0 General-purpose I/O port SO0 PI1 D Data output from UART0. This function is valid when UART0 data output is allowed. General-purpose I/O port. This function is valid when UART0 data output is not allowed SCK0 PI2 D Clock I/O for UART0. This function is valid when UART0 clock output is allowed or when external clock input is used. General-purpose I/O port. This function is valid when UART0 clock output is not allowed or when external clock input is not used SI1 D Data input for UART1. Since this input is always used when UART1 input is operating, output using the port must be stopped beforehand unless this operation is the intended operation. PI3 General-purpose I/O port SO1 PI4 D Data output from UART1. This function is valid when UART1 data output is allowed. General-purpose I/O port. This function is valid when UART1 data output is not allowed SCK1 PI5 D Clock I/O for UART1. This function is valid when UART1 clock output is allowed or when external clock input is used. General-purpose I/O port. This function is valid when UART1 clock output is not allowed or when external clock input is not used SI2 D Data input for UART2. Since this input is always used when UART2 input is operating, output using the port must be stopped beforehand unless this operation is the intended operation. PH0 General-purpose I/O port (Continued) 12

13 Pin no. LQFP* 1 LQFP* 2 Pin name I/O circuit type* 3 Function SO2 PH1 D Data output from UART2. This function is valid when UART2 data output is allowed. General-purpose I/O port. This function is valid when UART2 data output is not allowed or when external shift clock input is used SCK2 PH2 D Clock I/O for UART2. This function is valid when UART2 clock output is allowed or when external clock input is used. General-purpose I/O port. This function is valid when UART2 clock output is not allowed or when external clock input is not used SI3 D Data input for UART3. Since this input is always used when UART3 input is operating, output using the port must be stopped beforehand unless this operation is the intended operation. PH3 General-purpose I/O port SO3 PH4 D Data output from UART3. This function is valid when UART3 data output is allowed. General-purpose I/O port. This function is valid when UART3 data output is not allowed SCK3 PH5 D Clock I/O for UART3. This function is valid when UART3 clock output is allowed or when external clock input is used. General-purpose I/O port. This function is valid when UART3 clock output is not allowed or when external clock input is not used SI4 D Data input for UART4. Since this input is always used when UART4 input is operating, output using the port must be stopped beforehand unless this operation is the intended operation. PG0 General-purpose I/O port SO4 PG1 D Data output from UART4. This function is valid when serial I/O4 data output is allowed. General-purpose I/O port. This function is valid when serial I/O4 data output is not allowed. (Continued) 13

14 Pin no. LQFP* 1 LQFP* Pin name SCK4 PG2 SI5 PG3 SO5 PG4 SCK5 I/O circuit type* 3 D D D D Function Clock I/O for UART4. This function is valid when serial I/O4 clock output is allowed or when external clock input is used. General-purpose I/O port. This function is valid when serial I/O4 clock output is not allowed or when external clock input is not used. Data input for serial I/O5. Since this input is always used when serial I/O5 input is operating, output using the port must be stopped beforehand unless this operation is the intended operation. General-purpose I/O port Data output from serial I/O5. This function is valid when serial I/O5 data output is allowed. General-purpose I/O port. This function is valid when serial I/O5 data output is not allowed. Clock I/O for serial I/O5. This function is valid when serial I/O5 clock output is allowed or when external shift clock input is used. General-purpose I/O port. PG5 This function is valid when serial I/O5 clock output is not allowed or when external clock input is not used NMI H NMI (non-maskable interrupt) input X1A B Clock (oscillation) output (subclock) X0A B Clock (oscillation) input (subclock) 138 to to 54 MD2 to MD0 H Mode pins 2 to 0. These pins set the basic operating mode. Connect the pins to VCC or VSS. J Input circuit type: The production version (mask ROM version) is the "H" type. The flash ROM version is the "J" type X0 A Clock (oscillation) input (main clock) X1 A Clock (oscillation) output (main clock) INIT I External reset input DREQ2 PC0 C DMA external transfer request input. Since this input is always used when it is selected as the source of DMA activation, output using the port must be stopped beforehand unless this operation is the intended operation. General-purpose I/O port (Continued) 14

15 Pin no. LQFP* 1 LQFP* 2 Pin name I/O circuit type* 3 Function DACK2 PC1 C DMA external transfer request acceptance output. This function is valid when DMA transfer request acceptance output is allowed. General-purpose I/O port. This function is valid when DMA transfer request acceptance output is allowed. DEOP2 DMA external transfer end output. This function is valid when DMA external transfer end output is allowed DSTP2 C DMA external transfer stop input. This function is valid when DMA external transfer stop input is allowed. PC2 General-purpose I/O port. This function is valid when DMA external transfer end output and external transfer stop input are not allowed DREQ0 C DMA external transfer request input. Since this input is always used when it is selected as the source of DMA activation, output using the port must be stopped beforehand unless this operation is the intended operation. PB0 General-purpose I/O port DACK0 PB1 C DMA external transfer request acceptance output. This function is valid when DMA transfer request acceptance output is allowed. General-purpose I/O port. This function is valid when DMA transfer request acceptance output is not allowed. DEOP0 DMA external transfer end output. This function is valid when DMA external transfer end output is allowed DSTP0 C DMA external transfer stop input. This function is valid when DMA external transfer stop input is allowed. PB2 General-purpose I/O port. This function is valid when DMA external transfer end output and external transfer stop input are not allowed DREQ1 C DMA external transfer request input. Since this input is always used when it is selected as the source of DMA activation, output using the port must be stopped beforehand unless this operation is the intended operation. PB3 General-purpose I/O port. (Continued) 15

16 Pin no. LQFP* 1 LQFP* 2 Pin name I/O circuit type* 3 Function DACK1 PB4 C DMA external transfer request acceptance output. This function is valid when DMA transfer request acceptance output is allowed. General-purpose I/O port. This function is valid when DMA external transfer request acceptance output is not allowed. DEOP1 DMA external transfer end output. This function is valid when DMA external transfer end output is allowed DSTP1 C DMA external transfer stop input. This function is valid when DMA external transfer stop input is allowed. PB5 General-purpose I/O port. This function is valid when DMA external transfer end output and external transfer stop input are not allowed IOWR PB6 C Write strobe output for DMA fly-by transfer. This function is valid when write strobe output for DMA fly-by transfer is allowed. General-purpose I/O port. This function is valid when write strobe output for DMA fly-by transfer is not allowed IORD PB7 C Read strobe output for DMA fly-by transfer. This function is valid when read strobe output for DMA fly-by transfer is allowed. General-purpose I/O port. This function is valid when read strobe output for DMA fly-by transfer is not allowed CS0 PA0 C Chip select 0 output. This function is valid in external bus mode. General-purpose I/O port. This function is valid in single-chip mode CS1 PA1 C Chip select 1 output. This function is valid when chip select 1 output is allowed. General-purpose I/O port. This function is valid when chip select 1 output is not allowed CS2 PA2 C Chip select 2 output. This function is valid when chip select 2 output is allowed. General-purpose I/O port. This function is valid when chip select 2 output is not allowed. (Continued) 16

17 Pin no. LQFP* 1 LQFP* 2 Pin name I/O circuit type* 3 Function CS3 PA3 C Chip select 3 output. This function is valid when chip select 3 output is allowed. General-purpose I/O port. This function is valid when chip select 3 output is not allowed. RDY External ready input. This function is valid when external ready input is allowed IN0 D Input capture input pin. Since this input is always used when it is selected for input capture input, output using the port must be stopped beforehand unless this operation is the intended operation. P80 General-purpose I/O port. This function is valid when external ready input is not allowed. BGRNT External bus open acceptance output. The L level is output when the external bus is open. This function is valid when output is allowed IN1 D Input capture input pin. Since this input is always used when it is selected for input capture input, output using the port must be stopped beforehand unless this operation is the intended operation. P81 General-purpose I/O port. This function is valid when external bus open acceptance is not allowed. BRQ External bus open request input. Input to the high level if you want to open the external bus. This function is valid when input is allowed IN2 D Input capture input pin. Since this input is always used when it is selected for input capture input, output using the port must be stopped beforehand unless this operation is the intended operation. P82 General-purpose I/O port. This function is valid when external bus open request is not allowed RD P83 D External bus read strobe output. This function is valid in external bus mode. General-purpose I/O port. This function is valid in single-chip mode. (Continued) 17

18 (Continued) Pin no. LQFP* 1 LQFP* Pin name WR0 P84 WR1 IN3 P85 SYSCLK I/O circuit type* 3 *1 : FPT-176P-M02 *2 : FPT-120P-M21 *3 : Refer to I/O CIRCUIT TYPE about I/O circuit type. *4 : These functions are not supported for the FPT-120P-M21. D D C Function External bus write strobe output. This function is valid in external bus mode. General-purpose I/O port. This function is valid in single-chip mode. External bus write strobe output. This function is valid when WR1 output in external bus mode is allowed. Input capture input pin. Since this input is always used when it is selected for input capture input, output using the port must be stopped beforehand unless this operation is the intended operation. General-purpose I/O port. This function is valid when external bus write enable output is not allowed. System clock output. This function is valid when system clock output is allowed. A clock having the same frequency as the external bus operating frequency is output (stopped in stop mode). P90 General-purpose I/O port. This function is valid when system clock output is not allowed P91 C General-purpose I/O port MCLK C Memory clock output. This function is valid when memory clock output is allowed. A clock having the same frequency as the external bus operating frequency is output (stopped in sleep mode). General-purpose I/O port. P92 This function is valid when memory clock output is not allowed P93 C General-purpose I/O port AS P94 C Address strobe output. This function is valid when address strobe output is allowed. General-purpose I/O port. This function is valid when address load output is not allowed. 18

19 [Power supply and GND pins] Pin number LQFP* 1 LQFP* 2 Pin name Function 17, 35, 65, 79, 93, 96, 114, 136, 145, 162, , 40, 43, 59, 76, 96, 112 VSS GND pins. Use the same potential for all pins. 18, 36, 66, 80, 97, 115, 142, 146, 163, , 44, 56, 77, 95 VCC 3.3 V power supply pins. Use the same potential for all pins DAVS D/A converter GND pin DAVC D/A converter power supply pin AVCC A/D converter analog power supply pin AVRH A/D converter reference power supply pin AVSS/AVRL A/D converter analog GND pin *1 : FPT-176P-M02 *2 : FPT-120P-M21 19

20 I/O CIRCUIT TYPE Type Circuit type Remarks X1 Clock input Oscillation feedback resistance: approx. 1 MΩ A X0 Standby control X1A Clock input Oscillation feedback resistance for low speed (subclock oscillation): approx. 7 MΩ B X0A Standby control P-ch P-ch Pull-up control Digital output CMOS level output CMOS level input C N-ch Digital output With standby control With Pull-up control Digital input Standby control P-ch P-ch Pull-up control Digital output CMOS level output CMOS level hysteresis input D N-ch Digital output With standby control With Pull-up control Digital input Standby control (Continued) 20

21 Type Circuit type Remarks P-ch Digital output CMOS level output CMOS level hysteresis input E N-ch P-ch Digital output With stand voltage of 5 V Digital input N-ch Digital output N-ch (Open drain input) CMOS level hysteresis input F Digital input With standby control With stand voltage of 5 V Standby control P-ch Analog input With switch N-ch G Analog input Control CMOS level hysteresis input P-ch H N-ch Digital input CMOS level hysteresis input P-ch P-ch With pull-up resistor I Digital input (Continued) 21

22 (Continued) Type Circuit type Remarks N-ch N-ch CMOS level input Flash product only J N-ch N-ch Control signal N-ch Mode input Diffused resistor 22

23 HANDLING DEVICES Preventing Latch-up Latch-up may occur in a CMOS IC if a voltage greater than VCC or less than VSS is applied to an input or output pin or if an above-rating voltage is applied between VCC and VSS. A latch-up,if it occurs, significantly increases the power supply current and may cause thermal destruction of an element. When you use a CMOS IC, don t exceed the absolute maximum rating. Treatment of Unused Pins Do not leave an unused input pin open, since it may cause a malfunction. Handle by using a pull-up or pulldown resistor. About Power Supply Pins In products with multiple VCC and VSS pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance. It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µf between VCC and VSS pins near this device. About Crystal Oscillator Circuit Noise near the X0, X1, X0A and X1A pins may cause the device to malfunction. Design the printed circuit board so that X0, X1, X0A, X1A, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located close to the device as possible. It is strongly recommended to design the PC board artwork with the X0, X1, X0A and X1A pins surrounded by ground plane because stable operation can be expected with such a layout. Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device. Notes on Using External Clock When external clock is selected, supply it to X0 pin generally, and simultaneously the opposite phase clock to X0 must be supplied to X1 pin. However, in this case the stop mode(oscillator stop mode) must not be used. (This is because the X1 pin stops at High level output in STOP mode.) Using an external clock (normal) X0 X1 MB91350A series Note: STOP mode (oscillation stop mode) cannot be used. Clock Control Block Take the oscillation stabilization wait time during Low level input to the INIT pin. 23

24 Notes on Using the Sub Clock When no oscillator is connected to the X0A and X1A pins, pull down the X0A pin and open the X1A pin. Using an external clock (normal) X0 OPEN X1 MB91350A series Treatment of NC and OPEN Pins Pins marked as NC and OPEN must be left open-circuit. About Mode Pins (MD0 to MD2) These pins should be connected directly to VCC or VSS pin. To prevent the device erroneously switching to test mode due to noise, design the printed circuit board such that the distance between the mode pins and VCC or VSS pin is short as possible and the connection impedance is low. Operation at Start-up The INIT pin must be at Low level when the power supply is turned on. Immediately after the power supply is turned on, hold the Low level input to the INIT pin for the settling time required for the oscillator circuit to take the oscillation stabilization wait time for the oscillator circuit. (For INIT via the INIT pin, the oscillation stabilization wait time setting is initialized to the minimum value.) About Oscillation Input at Power On When turning the power on, maintain clock input until the device is released from the oscillation stabilization wait state. Caution on Operations during PLL Clock Mode On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs. External Bus Setting This model guarantees an external bus frequency of 25 MHz. Setting the base clock frequency to 50 MHz with DIVR1 (external bus base clock division setting register) initialized sets the external bus frequency also to 50 MHz. Before changing the base clock frequency, set the external bus frequency not exceeding 25 MHz. MCLK and SYSCLK MCLK and SYSCLK has a difference that MCLK stops in SLEEP/STOP mode but SYSCLK stops only in STOP mode. Use either depending on each application. Upon initialization, MCLK becomes invalid (PORT) and SYSCLK becomes valid. To use MCLK, set the port function register (PFR) to select the use of that clock. 24

25 Pull-up Control Connecting a pull-up resistor to the pin serving as an external bus pin cannot a guarantee the ELECTRICAL CHARACTERISTICS 4. AC Characteristics (4) Normal Bus Access Read/Write Operation, (5) Multiplex Bus Access Read/Write operation and (7) Hold Timing. Even the port for which a pull-up resistor has been set is invalid in stop mode with HIZ = 1 or in hardware standby mode. Sub Clock Select Immediately after switching from main clock mode to subclock mode for the clock source, insert at least one NOP instruction. (Idi #0x0b, r0) (Idi #_CLKR, r12) stb // sub-clock mode nop // Must insert NOP instruction Bit Search Module The BSD0, BSD1, and BDSC registers are accessed only in words. D-bus Memory Do not allocate the code area in memory on the D-bus because no instruction fetch takes place to the D-bus. Executing an instruction fetch to the D-bus area causes wrong data to be interpreted as code, possibly letting the device to run out of control. Low Power Consumption Mode To enter the sleep or stop mode, be sure to read the standby control register (STCR) immediately after writing to it. Precisely, use the following sequence. Set the I flag, ILM, and ICR to, after returning from standby mode, branch to the interrupt handler having caused the device to return. (Idi #value_of_standby, r0) (Idi #_STCR, r12) stb // set STOP/SLEEP bit r0 // Must read STCR r0 // after reading, go into standby mode nop // Must insert NOP *5 nop nop nop nop Switch Shared Port Function To switch between the use as a port and the use as a dedicated pin, use the port function register (PFR). Note, however, that bus pins are switched depending on external bus settings. Pre-fetch When accessing a prefetch-enabled little endian area, be sure to use word access (in 32-bit, word length) only. Byte or halfword access results in wrong data read. 25

26 I/O Port Access Ports are accessed only in bytes. Built-in RAM Immediately after a reset is canceled, the internal RAM allocation restricting function is still working, allowing only 4 KB to be used for data and for program execution irrespective of the on-chip RAM capacity. To kill the restricting function, update the setting. When the above setting is updated, the instruction must be followed by at least one NOP instruction. Flash MEMORY In programming mode, flash memory cannot be used as an interrupt vector table. A reset is possible. Notes on the PS Register As the PS register is processed by some instructions in advance, exception handling below may cause the interrupt handling routine to break when the debugger is used or the display contents of flags in the PS register to be updated. As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event, it performs operations before and after the EIT as specified in either case. 1. The following operations are performed when the instruction followed by a DIVOU/DIVOS instruction results in: (a) acceptance of a user interrupt or NMI, (b) single-stepping, or (c) a break at a data event or emulator menu. The D0 and D1 flags are updated in advance. An EIT handling routine (user interrupt, NMI, or emulator) is executed. Upon returning from the EIT, the DIVOU/DIVOS instruction is executed and the D0 and D1 flags are updated to the same values as in (1). 2. The following operations are performed when the ORCCR/STILM/MOVRi and PS instructions are executed. The PS register is updated in advance. An EIT handling routine (user interrupt, NMI, or emulator) is executed. Upon returning from the EIT, the above instructions are executed and the PS register is updated to the same value as in (1). 26

27 [Note on Debugger] Step Execution of RETI Command If an interrupt occurs frequently during single-stepping, the corresponding interrupt handling routine is executed repeatedly. This will prevent the main routine and low-interrupt-level programs from being executed. (Whenever RETI is single-stepped when interrupts by the timebase timer have been enabled, for example, the timebase timer routine causes a break at the beginning.) Disable the corresponding interrupt when the corresponding interrupt handling routine no longer needs debugging. Break Function If the address at which to cause a hardware break (including a event break) is set to the address currently contained in the system stack pointer or in the area containing the stack pointer, the user program causes a break after execution of one instruction. To prevent this, do not set (word) access to the area containing the address in the system stack pointer as the target of a hardware break (including an event break). Internal ROM area Do not set an area of internal ROM as a DMAC transfer destination. Simultaneous Occurrences of a Software Break (INTE instruction) and a User Interrupt/NMI When a software break and a user interrupt/nmi occur simultaneously, the emulator debugger may react as follows. The debugger stops pointing to a location other than the programmed breakpoints. The halted program is not re-executed correctly. If this symptom occurs, use a hardware break in place of a hardware break. When using a monitor debugger, do not set a break at the relevant location. A stack pointer placed in an area set for a DSU operand break can cause a malfunction. Do not apply a data event break to access to the area containing the address of a system stack pointer. 27

28 BLOCK DIAGRAMS MB91F353A/353A/352A/351A FR CPU Bit search DMAC 5 channels RAM 16 KB (stack)* ROM 512 KB* Bus Converter A20 to A00 D31 to D16 X0, X1 MD0 to MD2 INIT Clock control RAM 8 KB Adapter 32 External memory I/F RD WR1, WR0 RDY BRQ BGRNT SYSCLK X0A, X1A INT0 to INT7 NMI SI0 to SI3 SO0 to SO3 SCK0 to SCK3 Clock timer Interrupt Controller 8 channels External interrupt 4 channels UART 16 PORT 3 channels PPG 4 channels Reload timer Free-run timer PORT TRG0 to TRG4 PPG0, PPG2, PPG4 FRCK 4 channels U-timer 4 channels Input capture IN0 to IN3 SI6, SI7 SO6, SO7 SCK6, SCK7 2 channels SIO 2 channels Output compare OC0, OC2 AN0 to AN7 ATG AVRH, AVCC AVSS/AVRL 8 channels A/D converter 1 channel I 2 C SDA SCL DA0, DA1 DAVC, DAVS 2 channels D/A converter * : MB91352A : RAM 8 KB (stack), ROM 384 KB MB91351A : RAM 16 KB (stack), ROM 384 KB 1 channel 8-bit up/down counter AIN0 BIN0 ZIN0 28

29 MB91F355A/F356B/355A/354A FR CPU Bit search RAM (stack) DMAC 5 channels DREQ0 to DREQ2 DACK0 to DACK2 DEOP0/DSTP0 to DEOP2/DSTP2 IOWR IORD ROM/Flash Bus Converter A23 to A00 D31 to D16 X0, X1 MD0 to MD2 INIT RAM (Execute instruction) Clock control Adapter 32 External memory I/F RD WR1, WR0 RDY BRQ BGRNT SYSCLK X0A, X1A INT0 to INT15 NMI SI0 to SI4 SO0 to SO4 SCK0 to SCK4 Clock timer Interrupt Controller 16 channels External interrupt 5 channels UART 16 PORT 6 channels PPG 4 channels reload timer Free-run timer PORT TRG0 to TRG5 PPG0 to PPG5 TOT0 to TOT3 FRCK 5 channels U-Timer 4 channels input capture IN0 to IN3 SI5 to SI7 SO5 to SO7 SCK5 to SCK7 3 channels SIO 8 channels output compare AN0 to AN11 ATG AVRH, AVCC AVSS/AVRL DA0 to DA2 DAVC, DAVS 12 channels A/D converter 3 channels D/A converter 1 channel I 2 C 2 channels 8/16-bit up/down counter MB91F355A MB91F356B MB91355A MB91354A ROM/Flash 512 KB (Flash) 256 KB (Flash) 512 KB 384 KB RAM (stack) 16 KB 16 KB 16 KB 8 KB RAM (Execute instruction) 8 KB 8 KB 8 KB 8 KB SDA SCL OC0 to OC7 AIN0, AIN1 BIN0, BIN1 ZIN0, ZIN1 29

30 CPU AND CONTROL UNIT Internal architecture The FR family CPU is a high performance core based on a RISC architecture while incorporating advanced instructions for embedded controller applications. 1. Features RISC architecture employed. Basic instructions: Executed at 1 instruction per cycle General-purpose registers: 32-bit 16 registers 4GB linear memory space Multiplier integrated. 32-bit 32-bit multiplication: 5 cycles. 16-bit 16-bit multiplication: 3 cycles Enhanced interrupt servicing. Fast response speed (6 cycles). Multiple interrupts supported. Level masking (16 levels) Enhanced I/O manipulation instructions. Memory-to-memory transfer instructions Bit manipulation instructions High code efficiency. Basic instruction word length: 16-bit Low-power consumption. Sleep mode and stop mode Gear function 30

31 2. Internal architecture The FR-family CPU has a Harvard architecture in which the instruction and data buses are separated. The 32-bit 16-bit bus converter is connected to a 32-bit bus (F-bus), providing an interface between the CPU and peripheral resources. The Harvard Princeton bus converter is connected to both of the I-bus and D-bus, providing an interface between the CPU and the bus controller. FR CPU D-bus I-bus 32 I address 32 Harvard External address 24 D address I data 32 External data 16 Data RAM D data 32 Princeton bus converter 32-bit Address bit bus converter Data R-bus F-bus Peripherals resource Internal I/O bus controller 31

32 3. Programming model Basic programming model 32-bit [Initial Value] GENERAL PURPOSE REGISTERS R0 R1 R12 R13 R14 R15 AC FP SP XXXX XXXXH XXXX XXXXH H Program counter PC program status Table base register Return pointer System stack pointer User stack pointer Multiplication and division result register PS ILM SCR CCR TBR RP SSP USP MDH MDL 32

33 4. Register General purpose registers 32-bit [Initial Value] R0 R1 XXXX XXXXH R12 R13 R14 R15 AC FP SP XXXX XXXXH H Registers R0 to R15 are general-purpose registers. The registers are used as the accumulator and memory access pointers for CPU operations. Of these 16 registers, the registers listed below are intended for special applications, for which some instructions are enhanced. R13: Virtual accumulator R14: Frame pointer R15: Stack pointer The initial values of R0 to R14 after a reset are indeterminate. R15 is initialized to H (SSP value). PS (Program Status) This register holds the program status and is divided into the ILM, SCR, and CCR. The undefined bits in the following illustration are all reserved bits. Reading these bits always returns 0. Writing to them has no effect. PS bit 31 bit 20 bit 16 bit 10 bit 8 bit 7 bit 0 ILM SCR CCR 33

34 CCR (Condition Code Register) CCR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 S I N Z V C Initial Value XXXXB S : Stack flag. Cleared to 0 by a reset. I : Interrupt enable flag. Cleared to 0 by a reset. N : Negative flag. The initial value after a reset is indeterminate. Z : Zero flag. The initial value after a reset is indeterminate. V : Overflow flag. The initial value after a reset is indeterminate. C : Carry flag. The initial value after a reset is indeterminate. SCR (System Condition code Register) SCR bit 10 bit 9 bit 8 D1 D0 T Initial Value XX0B ILM Flag for step dividing Stores intermediate data for stepwise multiplication operations. Step trace trap flag A flag specifying whether the step trace trap function is enabled or not. Emulator use step trace trap function. The function cannot be used by the user program when using the emulator. ILM bit 20 bit 19 bit 18 bit 17 bit 16 ILM4 ILM3 ILM2 ILM1 ILM0 Initial Value 01111B This register stores the interrupt level mask value. The value in the ILM register is used as the level mask. Initialized to 15 (01111B) by a reset. PC (Program Counter) PC bit 31 bit 0 Initial Value XXXXXXXXH The program counter contains the address of the instruction currently being executed. The initial value after a reset is indeterminate. TBR (Table Base Register) TBR bit 31 bit 0 Initial Value 000FFC00H 34 The table base register contains the start address of the vector table used for servicing EIT events. The initial value after a reset is 000FFC00H.