Spansion Analog and Microcontroller Products

Transcription

1 Spansion Analog and Microcontroller Products The following document contains information on Spansion analog and microcontroller products. Although the document is marked with the name Fujitsu, the company that originally developed the specification, Spansion will continue to offer these products to new and existing customers. Continuity of Specifications There is no change to this document as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal document improvements and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers Spansion continues to support existing part numbers beginning with MB. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local sales office for additional information about Spansion memory, analog, and microcontroller products and solutions.

2 Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign xchange and Foreign Trade Law of Japan, the US xport Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright 2013 Spansion Inc. All rights reserved. Spansion, the Spansion logo, MirrorBit, MirrorBit clipse TM, ORNAND TM and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners.

3 FUJITSU SMICONDUCTOR DATA SHT DS v01-32-bit ARM TM Cortex TM -M3 based Microcontroller MB9BF429S/T, MB9BF428S/T DSCRIPTION The are highly integrated 32-bit microcontrollers dedicated for embedded controllers with low-power consumption mode and competitive cost. These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions such as various timers, ADCs, DACs and Communication Interfaces ( CAN, UART, CSIO, I 2 C, LIN). The products which are described in this data sheet are placed into TYP12 product categories in "FM3 Family PRIPHRAL MANUAL". Note: ARM and Cortex are the trademarks of ARM Limited in the U and other countries. Copyright 2013 FUJITSU SMICONDUCTOR LIMITD All rights reserved

4 FATURS 32-bit ARM Cortex-M3 Core Processor version: r2p1 Up to 60 MHz Frequency Operation Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels 24-bit System timer (Sys Tick): System timer for OS task management On-chip Memories [Flash memory] Dual operation Flash memory Main area: Up to 1.5Mbytes(1008Kbytes(ROM0) + 512Kbytes(ROM1) of Upper bank and 16Kbytes(ROM0) of Lower bank.) Work area 64 Kbytes(ROM1) of Lower bank Read cycle: 0 wait-cycle Security function for code protection [SRAM] This Series on-chip SRAM is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus or D-code bus of Cortex-M3 core. SRAM1 is connected to System bus. SRAM0: Up to 96 Kbytes SRAM1: Up to 96 Kbytes xternal Bus Interface Supports SRAM, NOR NAND Flash memory device Up to 8 chip selects 8/16-bit Data width Up to 25-bit Address bit Supports Address/Data multiplex Supports external RDY function DS v01-2

5 CAN Interface Compatible with CAN Specification 2.0A/B Maximum transfer rate: 1 Mbps Built-in 32 message buffer Multi-function Serial Interface (Max 16channels) 4 channels with 16steps 9-bit FIFO Operation mode is selectable from the followings for each channel. UART CSIO LIN I 2 C [UART] Full duplex double buffer Selection with or without parity supported Built-in dedicated baud rate generator xternal clock available as a serial clock Hardware Flow control: Automatically control the transmission/reception by CTS/RTS (only ch.4) Various error detection functions available (parity errors, framing errors, and overrun errors) [CSIO] Full duplex double buffer Built-in dedicated baud rate generator Overrun error detection function available [LIN] LIN protocol Rev.2.1 supported Full duplex double buffer Master/Slave mode supported LIN break field generation (can be changed to 13 to 16-bit length) LIN break delimiter generation (can be changed to 1 to 4-bit length) Various error detection functions available (parity errors, framing errors, and overrun errors) [I 2 C] Standard - mode (Max 100kbps) / Fast - mode (Max 400kbps) supported DMA Controller (8channels) The DMA Controller has an independent bus from the CPU, so CPU and DMA Controller can process simultaneously. 8 independently configured and operated channels Transfer can be started by software or request from the built-in peripherals Transfer address area: 32-bit (4 Gbytes) Transfer mode: Block transfer/burst transfer/demand transfer Transfer data type: byte/half-word/word Transfer block count: 1 to 16 Number of transfers: 1 to A/D Converter (Max 24channels) [12-bit A/D Converter] Successive Approximation type Built-in 2units Conversion time: 2.7V to 5.5V Priority conversion available (priority at 2levels) Scanning conversion mode Built-in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion: 4steps) 3 DS v01-

6 D/A Converter (Max 2channels) R-2R type 10-bit resolution Base Timer (Max 16channels) Operation mode is selectable from the followings for each channel. 16-bit PWM timer 16-bit PPG timer 16/32-bit reload timer 16/32-bit PWC timer General-Purpose I/O Port This series can use its pins as general-purpose I/O ports when they are not used for external bus or peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function can be allocated to. Capable of pull-up control per pin Capable of reading pin level directly Built-in the port relocate function Up to 154 high-speed general-purpose I/O Package Some ports are 5V tolerant. See " LIST OF PIN FUNCTIONS" and " I/O CIRCUIT TYP" to confirm the corresponding pins. Dual Timer (32/16-bit Down Counter) The Dual Timer consists of two programmable 32/16-bit down counters. Operation mode is selectable from the followings for each channel. Free-running Periodic (=Reload) One-shot Quadrature Position/Revolution Counter (QPRC) (Max 2channels) The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position encoder. Moreover, it is possible to use as the up/down counter. The detection edge of the three external event input pins AIN, BIN and ZIN is configurable. 16-bit position counter 16-bit revolution counter Two 16-bit compare registers HDMI-CC/Remote Control Reception (Up to 2channels) HDMI-CC transmission Header block automatic transmission by judging Signal free Generating status interrupt by detecting Arbitration lost Generating START, OM, ACK automatically to output CC transmission by setting 1 byte data Generating transmission status interrupt when transmitting 1 block (1 byte data and OM/ACK) HDMI-CC reception Automatic ACK reply function available Line error detection function available Remote control reception 4 bytes reception buffer Repeat code detection function available DS v01-4

7 Multi-function Timer The Multi-function timer is composed of the following blocks. 16-bit free-run timer 3ch./unit capture 4ch./unit Output compare 6ch./unit A/D activation compare 3ch./unit Waveform generator 3ch./unit 16-bit PPG timer 3ch./unit The following function can be used to achieve the motor control. PWM signal output function DC chopper waveform output function Dead time function capture function A/D convertor activate function DTIF (Motor emergency stop) interrupt function Real-time clock (RTC) The Real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 01 to 99. The interrupt function with specifying date and time (Year/Month/Day/Hour/Minute/Second/A day of the week.) is available. This function is also available by specifying only Year, Month, Day, Hour or Minute. Timer interrupt function after set time or each set time. Capable of rewriting the time with continuing the time count. Leap year automatic count is available. Watch Counter The Watch counter is used for wake up from sleep and timer mode. Interval timer: up to 64s Sub Clock : khz xternal Interrupt Controller Unit Up to 32 external interrupt input 176pin Package Include one non-maskable interrupt (NMI) input pin Watchdog Timer (2channels) A watchdog timer can generate interrupts or a reset when a time-out value is reached. This series consists of two different watchdogs, a "Hardware" watchdog and a "Software" watchdog. The "Hardware" watchdog timer is clocked by the built-in low-speed CR oscillator. Therefore, the "Hardware" watchdog is active in any low-power consumption modes except RTC, STOP, Deep standby RTC, Deep standby STOP modes. CRC (Cyclic Redundancy Check) Accelerator The CRC accelerator calculates the CRC which has a heavy software processing load, and achieves a reduction of the integrity check processing load for reception data and storage. CCITT CRC16 and I CRC32 are supported. CCITT CRC16 Generator Polynomial: 0x1021 I CRC32 Generator Polynomial: 0x04C11DB7 5 DS v01-

8 Clock and Reset [Clocks] Selectable from five clock sources (2 external oscillators, 2 built-in CR oscillators, and Main PLL). Main Clock Sub Clock Built-in high-speed CR Clock Built-in low-speed CR Clock Main PLL Clock [Resets] Reset requests from INITX pin Power-on reset Software reset Watchdog timers reset Low-voltage detection reset Clock Super Visor reset : 4 MHz to 48 MHz : khz : 4 MHz : 100 khz Clock Super Visor (CSV) Clocks generated by built-in CR oscillators are used to supervise abnormality of the external clocks. If external clock failure (clock stop) is detected, reset is asserted. If external frequency anomaly is detected, interrupt or reset is asserted. Low-Voltage Detector (LVD) This Series includes 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the voltage that has been set, Low-Voltage Detector generates an interrupt or reset. LVD1: error reporting via interrupt LVD2: auto-reset operation Low-Power Consumption Mode Six low-power consumption modes supported. SLP TIMR RTC STOP Deep standby RTC (selectable between keeping the value of RAM and not) Deep standby STOP (selectable between keeping the value of RAM and not) Debug Serial Wire JTAG Debug Port (SWJ-DP) mbedded Trace Macrocell (TM) Unique ID Unique value of the device (41-bit) is set. Power Supply Wide range voltage : VCC = 2.7V to 5.5V DS v01-6

9 PRODUCT LINUP Memory size Product name MB9BF428S/T MB9BF429S/T On-chip Flash memory On-chip SRAM Main area 1 Mbytes 1.5 Mbytes Work area 64 Kbytes 64 Kbytes SRAM0 80 Kbytes 96 Kbytes SRAM1 80 Kbytes 96 Kbytes Total 160 Kbytes 192 Kbytes Function Product name MB9BF428S MB9BF428T MB9BF429S MB9BF429T Pin count /192 CPU Cortex-M3 Freq. 60 MHz Power supply voltage range 2.7V to 5.5V CAN 1ch. DMAC 8ch. Addr: 25 bit (Max) xternal Bus Interface R/Wdata : 8/16 bit (Max) CS: 8 (Max) SRAM, NOR Flash memory, NAND Flash memory Multi-function Serial Interface (UART/CSIO/LIN/I 2 C) 16ch. (Max) Base Timer (PWC/Reload timer/pwm/ppg) 16ch. (Max) A/D activation compare 3ch. capture 4ch. MF- Free-run timer 3ch. Timer Output compare 6ch. 1 unit Waveform generator 3ch. PPG 3ch. QPRC 1ch.(Max) 2ch. (Max) Dual Timer 1 unit HDMI-CC/ Remote Control Reception 2ch. (Max) Real-Time Clock 1 unit Watch Counter 1 unit CRC Accelerator Yes Watchdog timer 1ch. (SW) + 1ch. (HW) xternal Interrupts 32pins (Max) + NMI 1 I/O ports 122pins (Max) 154pins (Max) 12-bit A/D converter 24ch. (2 units) 10-bit D/A converter 2ch. (Max) CSV (Clock Super Visor) Yes LVD (Low-Voltage Detector) 2ch. Built-in CR High-speed 4 MHz (± 2%) Low-speed 100 khz (Typ) Debug Function SWJ-DP / TM Unique ID Yes 7 DS v01-

10 Note: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use the port relocate function of the I/O port according to your function use. DS v01-8

11 PACKAGS Package Product name MB9BF428S MB9BF429S MB9BF428T MB9BF429T LQFP: FPT-144P-M08 (0.5mm pitch) - LQFP: FPT-176P-M07 (0.5mm pitch) - BGA: BGA-192P-M06 (0.8mm pitch) - : Supported Note: See " PACKAG DIMNSIONS" for detailed information on each package. 9 DS v01-

12 PIN ASSIGNMNT FPT-176P-M07 (TOP VIW) VSS P81 P80 VCC PF5/SCK6_2/IGTRG0_1/INT08_0/WKUP3/CC1_0 PF4/SOT6_2/TIOB06_0/INT07_0 PF3/SIN6_2/TIOA06_0/INT06_0 P60/SIN5_0/TIOA02_2/INT15_1/WKUP5/MAD20_0 P61/SOT5_0/TIOB02_2/MAD19_0 P62/ADTG_3/SCK5_0/MAD18_0 PD3/TIOB03_2/MAD17_0 PD2/SIN4_0/TIOA03_2/INT00_2/MAD16_0 PD1/SOT4_0/TIOB14_0/INT31_1/MAD15_0 PD0/SCK4_0/TIOB10_2/INT30_1/MAD14_0 PCF/CTS4_0/TIOB08_2/MAD13_0 PC/RTS4_0/TIOB06_1/MAD12_0 PCD/MAD11_0 PCC/MAD10_0 PCB/MAD09_0 VSS VCC PCA/SCK15_0/MAD08_0 PC9/SOT15_0/MAD07_0 PC8/SIN15_0/MAD06_0 PC7/CROUT_1/RTCCO_0/SUBOUT_0/MAD05_0 PC6/SCK14_0/TIOA14_0/MAD04_0 PC5/SOT14_0/TIOA10_2/MAD03_0 PC4/SIN14_0/TIOA08_2/CC0_1/MAD02_0 PC3/TIOA06_1/MAD01_0 PC2/SCK13_0/MAD00_0 PC1/DA1_0/SOT13_0/MCSX4_0 PC0/DA0_0/SIN13_0/MCSX5_0 P95/TIOB13_0/INT27_0 P94/SCK5_1/TIOB12_0/INT26_0 P93/SOT5_1/TIOB11_0 P92/SIN5_1/TIOB10_0 P91/TIOB09_0/INT31_0 P90/TIOB08_0/INT30_0 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX VCC VCC VSS PA0/SIN8_0/TIOA08_0/MAD21_ VCC PA1/SOT8_0/TIOA09_0/MAD22_ P83/MCSX6_0 PA2/SCK8_0/TIOA10_0/MAD23_ P82/MCSX7_0 PA3/SIN9_0/TIOA11_0/MAD24_ PF6/NMIX/WKUP0 PA4/RX0_2/SOT9_0/TIOA12_0/INT03_ P20/AIN1_1/INT05_0/CROUT_0 PA5/TX0_2/SCK9_0/TIOA13_0/INT10_ P21/SIN0_0/BIN1_1/INT06_1 P05/TRACD0/SIN4_2/TIOA05_2/INT00_ P22/AN23/SOT0_0/ZIN1_1/TIOB07_1 P06/TRACD1/SOT4_2/TIOB05_2/INT01_ P23/AN22/SCK0_0/RTO00_1/TIOA07_1 P07/TRACD2/ADTG_0/SCK4_ P24/AN21/SIN2_1/RTO01_1/INT01_2 P08/TRACD3/CTS4_2/TIOA00_ P25/AN20/SOT2_1/RTO02_1 P09/TRACCLK/RTS4_2/TIOB00_ P26/AN19/SCK2_1/RTO03_1 P50/SIN3_1/AIN0_2/INT00_0/MOX_ P27/AN18/SCK12_0/RTO04_1/INT02_2 P51/SOT3_1/BIN0_2/INT01_0/MWX_ P28/AN17/ADTG_4/SOT12_0/RTO05_1/INT09_0 P52/SCK3_1/ZIN0_2/INT02_0/MDQM0_ P29/AN16/SIN12_0 P53/SIN6_0/TIOA01_2/INT07_2/MDQM1_ AVRH P54/SOT6_0/TIOB01_2/MAL_ AVRL P55/ADTG_1/SCK6_0/MRDY_ AVSS P56/SIN1_0/TIOA09_2/INT08_2/CC1_1/MNAL_ AVCC P57/SOT1_0/TIOB09_2/INT16_1/MNCL_ PB7/TIOB12_1/INT23_0 P58/SCK1_0/TIOA11_2/INT17_1/MNWX_ PB6/SCK0_2/TIOA12_1/INT22_0 P59/SIN7_0/TIOB11_2/INT09_2/MNRX_ PB5/SOT0_2/TIOB11_1/INT21_0 P5A/SOT7_0/TIOA13_1/INT18_1/MCSX0_ PB4/SIN0_2/TIOA11_1/INT20_0 P5B/SCK7_0/TIOB13_1/INT19_1/MCSX1_ PB3/TIOB10_1/INT19_0 P5C/TIOA06_2/INT28_ PB2/SCK7_2/TIOA10_1/INT18_0 P5D/TIOB06_2/INT29_ PB1/SOT7_2/TIOB09_1/INT17_0 VSS PB0/SIN7_2/TIOA09_1/INT16_0 P30/AIN0_0/TIOB00_1/INT03_2/WKUP P1F/AN15/ADTG_5/FRCK0_1/TIOB15_2/INT29_1 P31/SCK6_1/BIN0_0/TIOB01_1/INT04_ P1/AN14/RTS4_1/DTTI0X_1/TIOA15_2/INT28_1 P32/SOT6_1/ZIN0_0/TIOB02_1/INT05_ P1D/AN13/CTS4_1/IC03_1/TIOB14_2/INT27_1 P33/ADTG_6/SIN6_1/TIOB03_1/INT04_ P1C/AN12/SCK4_1/IC02_1/TIOA14_2/INT26_1 P34/TX0_1/FRCK0_0/TIOB04_ P1B/AN11/SOT4_1/IC01_1/TIOB13_2/INT25_1 P35/RX0_1/IC03_0/TIOB05_1/INT08_ P1A/AN10/SIN4_1/IC00_1/TIOA13_2/INT05_1 P36/SIN5_2/IC02_0/TIOA12_2/INT09_ P19/AN09/SCK2_2/INT22_1 P37/SOT5_2/IC01_0/TIOB12_2/INT10_ P18/AN08/SOT2_2/INT21_1 P38/SCK5_2/IC00_0/INT11_ P17/AN07/SIN2_2/INT04_1 P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_ P16/AN06/SCK0_1/INT20_1 P3A/RTO00_0/TIOA00_ P15/AN05/SOT0_1/IC03_2 P3B/RTO01_0/TIOA01_ P14/AN04/SIN0_1/IC02_2/INT03_1 P3C/RTO02_0/TIOA02_ P13/AN03/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1 P3D/RTO03_0/TIOA03_ P12/AN02/SOT1_1/IC00_2 P3/RTO04_0/TIOA04_ P11/AN01/SIN1_1/FRCK0_2/INT02_1/WKUP1 P3F/RTO05_0/TIOA05_ P10/AN00 VSS VCC VCC P40/SIN10_0/TIOA00_0/INT12_1/MCSX2_0 P41/SOT10_0/TIOA01_0/INT13_1/MCSX3_0 P42/SCK10_0/TIOA02_0/MCLKOUT_0 P43/ADTG_7/SIN11_0/TIOA03_0 P44/SOT11_0/TIOA04_0 P45/SCK11_0/TIOA05_0 VSS VCC P46/X0A P47/X1A INITX P48/SIN3_2/INT14_1 P49/SOT3_2/AIN0_1/TIOB00_0 P4A/SCK3_2/BIN0_1/TIOB01_0/MADATA00_0 P4B/IGTRG0_0/ZIN0_1/TIOB02_0/MADATA01_0 P4C/SCK7_1/AIN1_2/TIOB03_0/MADATA02_0 P4D/SOT7_1/BIN1_2/TIOB04_0/MADATA03_0 P4/SIN7_1/ZIN1_2/TIOB05_0/INT06_2/MADATA04_0 P70/TX0_0/TIOA04_2/MADATA05_0 P71/RX0_0/TIOB04_2/INT13_2/MADATA06_0 P72/SIN2_0/INT14_2/WKUP2/MADATA07_0 P73/SOT2_0/INT15_2/MADATA08_0 P74/SCK2_0/MADATA09_0 P75/ADTG_8/SIN3_0/INT07_1/MADATA10_0 P76/SOT3_0/TIOA07_2/INT11_2/MADATA11_0 P77/SCK3_0/TIOB07_2/INT12_2/MADATA12_0 P78/AIN1_0/TIOA15_0/MADATA13_0 P79/BIN1_0/TIOB15_0/INT23_1/MADATA14_0 P7A/ZIN1_0/INT24_1/MADATA15_0 P7B/TIOB07_0/INT10_0 P7C/TIOA07_0/INT11_0 P7D/TIOA14_1/INT12_0 P7/TIOB14_1/INT24_0 P7F/TIOA15_1/INT25_0 PF0/SIN1_2/TIOB15_1/INT13_0/CC0_0 PF1/SOT1_2/TIOA08_1/INT14_0 PF2/SCK1_2/TIOB08_1/INT15_0 P0/MD1 MD0 P2/X0 P3/X1 VSS C LQFP <Note> The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (PFR) to select the pin. DS v01-10

13 FPT-144P-M08 (TOP VIW) VSS P81 P80 VCC PF5/IGTRG0_1/INT08_0/WKUP3/CC1_0 P60/SIN5_0/TIOA02_2/INT15_1/WKUP5/MAD20_0 P61/SOT5_0/TIOB02_2/MAD19_0 P62/ADTG_3/SCK5_0/MAD18_0 PD3/TIOB03_2/MAD17_0 PD2/SIN4_0/TIOA03_2/INT00_2/MAD16_0 PD1/SOT4_0/TIOB14_0/INT31_1/MAD15_0 PD0/SCK4_0/TIOB10_2/INT30_1/MAD14_0 PCF/CTS4_0/TIOB08_2/MAD13_0 PC/RTS4_0/TIOB06_1/MAD12_0 PCD/MAD11_0 PCC/MAD10_0 PCB/MAD09_0 VSS VCC PCA/SCK15_0/MAD08_0 PC9/SOT15_0/MAD07_0 PC8/SIN15_0/MAD06_0 PC7/CROUT_1/RTCCO_0/SUBOUT_0/MAD05_0 PC6/SCK14_0/TIOA14_0/MAD04_0 PC5/SOT14_0/TIOA10_2/MAD03_0 PC4/SIN14_0/TIOA08_2/CC0_1/MAD02_0 PC3/TIOA06_1/MAD01_0 PC2/SCK13_0/MAD00_0 PC1/DA1_0/SOT13_0/MCSX4_0 PC0/DA0_0/SIN13_0/MCSX5_0 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX VCC VCC VSS PA0/SIN8_0/TIOA08_0/MAD21_ VCC PA1/SOT8_0/TIOA09_0/MAD22_ P83/MCSX6_0 PA2/SCK8_0/TIOA10_0/MAD23_ P82/MCSX7_0 PA3/SIN9_0/TIOA11_0/MAD24_ PF6/NMIX/WKUP0 PA4/RX0_2/SOT9_0/TIOA12_0/INT03_ P20/AIN1_1/INT05_0/CROUT_0 PA5/TX0_2/SCK9_0/TIOA13_0/INT10_ P21/SIN0_0/BIN1_1/INT06_1 P05/TRACD0/SIN4_2/TIOA05_2/INT00_ P22/AN23/SOT0_0/ZIN1_1/TIOB07_1 P06/TRACD1/SOT4_2/TIOB05_2/INT01_ P23/AN22/SCK0_0/RTO00_1/TIOA07_1 P07/TRACD2/ADTG_0/SCK4_ P24/AN21/SIN2_1/RTO01_1/INT01_2 P08/TRACD3/CTS4_2/TIOA00_ P25/AN20/SOT2_1/RTO02_1 P09/TRACCLK/RTS4_2/TIOB00_ P26/AN19/SCK2_1/RTO03_1 P50/SIN3_1/AIN0_2/INT00_0/MOX_ P27/AN18/SCK12_0/RTO04_1/INT02_2 P51/SOT3_1/BIN0_2/INT01_0/MWX_ P28/AN17/ADTG_4/SOT12_0/RTO05_1/INT09_0 P52/SCK3_1/ZIN0_2/INT02_0/MDQM0_ P29/AN16/SIN12_0 P53/SIN6_0/TIOA01_2/INT07_2/MDQM1_ AVRH P54/SOT6_0/TIOB01_2/MAL_ AVRL P55/ADTG_1/SCK6_0/MRDY_ AVSS P56/SIN1_0/TIOA09_2/INT08_2/CC1_1/MNAL_ AVCC P57/SOT1_0/TIOB09_2/INT16_1/MNCL_ P1F/AN15/ADTG_5/FRCK0_1/TIOB15_2/INT29_1 P58/SCK1_0/TIOA11_2/INT17_1/MNWX_ P1/AN14/RTS4_1/DTTI0X_1/TIOA15_2/INT28_1 P59/SIN7_0/TIOB11_2/INT09_2/MNRX_ P1D/AN13/CTS4_1/IC03_1/TIOB14_2/INT27_1 P5A/SOT7_0/TIOA13_1/INT18_1/MCSX0_ P1C/AN12/SCK4_1/IC02_1/TIOA14_2/INT26_1 P5B/SCK7_0/TIOB13_1/INT19_1/MCSX1_ P1B/AN11/SOT4_1/IC01_1/TIOB13_2/INT25_1 VSS P1A/AN10/SIN4_1/IC00_1/TIOA13_2/INT05_1 P36/SIN5_2/IC02_0/TIOA12_2/INT09_ P19/AN09/SCK2_2/INT22_1 P37/SOT5_2/IC01_0/TIOB12_2/INT10_ P18/AN08/SOT2_2/INT21_1 P38/SCK5_2/IC00_0/INT11_ P17/AN07/SIN2_2/INT04_1 P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_ P16/AN06/SCK0_1/INT20_1 P3A/RTO00_0/TIOA00_ P15/AN05/SOT0_1/IC03_2 P3B/RTO01_0/TIOA01_ P14/AN04/SIN0_1/IC02_2/INT03_1 P3C/RTO02_0/TIOA02_ P13/AN03/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1 P3D/RTO03_0/TIOA03_ P12/AN02/SOT1_1/IC00_2 P3/RTO04_0/TIOA04_ P11/AN01/SIN1_1/FRCK0_2/INT02_1/WKUP1 P3F/RTO05_0/TIOA05_ P10/AN00 VSS VCC VCC P40/SIN10_0/TIOA00_0/INT12_1/MCSX2_0 P41/SOT10_0/TIOA01_0/INT13_1/MCSX3_0 P42/SCK10_0/TIOA02_0/MCLKOUT_0 P43/ADTG_7/SIN11_0/TIOA03_0 P44/SOT11_0/TIOA04_0 P45/SCK11_0/TIOA05_0 VSS VCC P46/X0A P47/X1A INITX P48/SIN3_2/INT14_1 P49/SOT3_2/AIN0_1/TIOB00_0 P4A/SCK3_2/BIN0_1/TIOB01_0/MADATA00_0 P4B/IGTRG0_0/ZIN0_1/TIOB02_0/MADATA01_0 P4C/SCK7_1/AIN1_2/TIOB03_0/MADATA02_0 P4D/SOT7_1/BIN1_2/TIOB04_0/MADATA03_0 P4/SIN7_1/ZIN1_2/TIOB05_0/INT06_2/MADATA04_0 P70/TX0_0/TIOA04_2/MADATA05_0 P71/RX0_0/TIOB04_2/INT13_2/MADATA06_0 P72/SIN2_0/INT14_2/WKUP2/MADATA07_0 P73/SOT2_0/INT15_2/MADATA08_0 P74/SCK2_0/MADATA09_0 P75/ADTG_8/SIN3_0/INT07_1/MADATA10_0 P76/SOT3_0/TIOA07_2/INT11_2/MADATA11_0 P77/SCK3_0/TIOB07_2/INT12_2/MADATA12_0 P78/AIN1_0/TIOA15_0/MADATA13_0 P79/BIN1_0/TIOB15_0/INT23_1/MADATA14_0 P7A/ZIN1_0/INT24_1/MADATA15_0 P0/MD1 MD0 P2/X0 P3/X1 VSS C LQFP <Note> The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (PFR) to select the pin. 11 DS v01-

14 BGA-192P-M06 (TOP VIW) A P81 P80 VCC VSS PCD PCB VSS VCC PC8 VSS TCK VCC B VSS PA0 PF5 PF3 P61 PD1 PCA PC1 P95 P92 TDO TMS TRSTX VSS C VCC PA1 PA2 PF4 P60 PD2 PCC PC5 PC0 P93 P90 TDI PF6 VCC D PA5 PA4 P05 P06 PA3 PD3 PC PC6 PC2 P94 P91 P21 P20 P83 VSS P07 P08 P09 P50 P62 PCF PC7 PC3 P25 P24 P23 P22 P82 F P51 P52 P53 P54 P55 P56 PD0 PC9 PC4 P29 P28 P27 P26 AVRH G VSS P57 P58 P59 P5A P5B VSS VSS PB7 PB6 PB5 PB4 PB3 AVRL H P5C P5D P30 P31 P32 P33 VSS VSS P1F P1 PB2 PB1 PB0 AVSS J VSS P37 P36 P35 P34 P70 VSS P76 P1D P1C P1B P1A P19 AVCC K P38 P39 P3A P3B P4A P4 VSS P74 P7B P7F P18 P16 P15 P17 L P3C P3D P3 P43 P49 P4D VSS P73 P7A P7 P14 P13 P12 VSS M VSS P3F P42 P44 P48 P4C VSS P72 P79 PF0 PF2 P11 P10 VCC N VCC P40 P41 P45 INITX P4B VSS P71 P78 P7D PF1 MD0 MD1 VSS P C VSS VCC X0A X1A VSS P75 P77 P7C VSS X0 X1 <Note> The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (PFR) to select the pin. DS v01-12

15 LIST OF PIN FUNCTIONS List of pin numbers The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (PFR) to select the pin. Pin No I/O circuit Pin Pin Name LQFP-176 LQFP-144 BGA-192 type type 1 1 C1 VCC - PA0 2 2 B2 SIN8_0 TIOA08_0 MAD21_0 I* J PA1 3 3 C2 SOT8_0 TIOA09_0 MAD22_0 I* J PA2 4 4 C3 SCK8_0 TIOA10_0 MAD23_0 I* J PA3 5 5 D5 SIN9_0 TIOA11_0 MAD24_0 I* J PA4 6 6 D2 RX0_2 SOT9_0 TIOA12_0 INT03_0 I* K PA5 7 7 D1 TX0_2 SCK9_0 TIOA13_0 INT10_2 I* K P D3 TRACD0 SIN4_2 TIOA05_2 Q 9 9 D4 INT00_1 P06 TRACD1 SOT4_2 TIOB05_2 INT01_1 Q 13 DS v01-

16 Pin No LQFP-176 LQFP-144 BGA F F2 Pin Name P07 TRACD2 ADTG_0 SCK4_2 P08 TRACD3 CTS4_2 TIOA00_2 P09 TRACCLK RTS4_2 TIOB00_2 P50 SIN3_1 AIN0_2 INT00_0 MOX_0 P51 SOT3_1 BIN0_2 INT01_0 MWX_0 P52 SCK3_1 ZIN0_2 INT02_0 MDQM0_0 I/O circuit type Pin type P P P K K K DS v01-14

17 Pin No LQFP-176 LQFP-144 BGA F F F F G G G4 Pin Name P53 SIN6_0 TIOA01_2 INT07_2 MDQM1_0 P54 SOT6_0 TIOB01_2 MAL_0 P55 ADTG_1 SCK6_0 MRDY_0 P56 SIN1_0 TIOA09_2 INT08_2 CC1_1 MNAL_0 P57 SOT1_0 TIOB09_2 INT16_1 MNCL_0 P58 SCK1_0 TIOA11_2 INT17_1 MNWX_0 P59 SIN7_0 TIOB11_2 INT09_2 MNRX_0 I/O circuit type Pin type K J J I* S I* K I* K K 15 DS v01-

18 Pin No I/O circuit Pin name LQFP-176 LQFP-144 BGA-192 type P5A SOT7_ G5 TIOA13_1 INT18_1 MCSX0_0 P5B SCK7_ G6 TIOB13_1 INT19_1 MCSX1_0 P5C 25 - H1 TIOA06_2 INT28_0 P5D 26 - H2 TIOB06_2 INT29_ A5 VSS - P30 AIN0_ H3 TIOB00_1 INT03_2 WKUP4 P31 SCK6_ H4 BIN0_0 TIOB01_1 INT04_2 P32 SOT6_ H5 ZIN0_0 TIOB02_1 INT05_2 P33 ADTG_ H6 SIN6_1 TIOB03_1 INT04_0 Pin type K K K K U K K K DS v01-16

19 Pin No LQFP-176 LQFP-144 BGA J J J J K K K K L1 Pin name P34 TX0_1 FRCK0_0 TIOB04_1 P35 RX0_1 IC03_0 TIOB05_1 INT08_1 P36 SIN5_2 IC02_0 TIOA12_2 INT09_1 P37 SOT5_2 IC01_0 TIOB12_2 INT10_1 P38 SCK5_2 IC00_0 INT11_1 P39 ADTG_2 DTTI0X_0 RTCCO_2 SUBOUT_2 P3A RTO00_0 TIOA00_1 P3B RTO01_0 TIOA01_1 P3C RTO02_0 TIOA02_1 I/O circuit type F F F Pin type J K K K K J J J J 17 DS v01-

20 Pin No I/O circuit Pin Pin name LQFP-176 LQFP-144 BGA-192 type type P3D L2 RTO03_0 TIOA03_1 F J P L3 RTO04_0 TIOA04_1 F J P3F M2 RTO05_0 TIOA05_1 F J A8 VSS N1 VCC - P40 SIN10_ N2 TIOA00_0 INT12_1 MCSX2_0 K P N3 SOT10_0 TIOA01_0 INT13_1 MCSX3_0 K P M3 SCK10_0 TIOA02_0 MCLKOUT_0 J P L4 ADTG_7 SIN11_0 TIOA03_0 I* J P M4 SOT11_0 TIOA04_0 I* J P N4 SCK11_0 TIOA05_0 I* J P2 C A11 VSS P4 VCC P5 P46 X0A D F P6 P47 X1A D G N5 INITX B C P M5 SIN3_2 INT14_1 K DS v01-18

21 Pin No LQFP-176 LQFP-144 BGA L K N M L K J N8 Pin name P49 SOT3_2 AIN0_1 TIOB00_0 P4A SCK3_2 BIN0_1 TIOB01_0 MADATA00_0 P4B IGTRG0_0 ZIN0_1 TIOB02_0 MADATA01_0 P4C SCK7_1 AIN1_2 TIOB03_0 MADATA02_0 P4D SOT7_1 BIN1_2 TIOB04_0 MADATA03_0 P4 SIN7_1 ZIN1_2 TIOB05_0 INT06_2 MADATA04_0 P70 TX0_0 TIOA04_2 MADATA05_0 P71 RX0_0 TIOB04_2 INT13_2 MADATA06_0 I/O circuit type Pin type J J J J J K J K 19 DS v01-

22 Pin No LQFP-176 LQFP-144 BGA-192 Pin name I/O circuit type P72 SIN2_ M8 INT14_2 WKUP2 MADATA07_0 P L8 SOT2_0 INT15_2 MADATA08_0 P K8 SCK2_0 MADATA09_0 P75 ADTG_ P8 SIN3_0 INT07_1 MADATA10_0 P76 SOT3_ J8 TIOA07_2 INT11_2 MADATA11_0 P77 SCK3_ P9 TIOB07_2 INT12_2 MADATA12_0 P N9 AIN1_0 TIOA15_0 MADATA13_0 P79 BIN1_ M9 TIOB15_0 INT23_1 MADATA14_0 - - M1 VSS P3 VSS - Pin type U K J K K K J K DS v01-20

23 Pin No I/O circuit Pin Pin name LQFP-176 LQFP-144 BGA-192 type type P7A L9 ZIN1_0 INT24_1 MADATA15_0 K P7B 76 - K9 TIOB07_0 INT10_0 K P7C 77 - P10 TIOA07_0 INT11_0 K P7D 78 - N10 TIOA14_1 INT12_0 K P L10 TIOB14_1 INT24_0 K P7F 80 - K10 TIOA15_1 INT25_0 K PF M10 SIN1_2 TIOB15_1 INT13_0 CC0_0 I* S PF N11 SOT1_2 TIOA08_1 INT14_0 I* K PF M11 SCK1_2 TIOB08_1 INT15_0 I* K N13 P0 MD1 C N12 MD0 J D P12 P2 X0 A A P13 P3 X1 A B VSS M14 VCC P7 VSS N7 VSS - 21 DS v01-

24 Pin No LQFP-176 LQFP-144 BGA-192 Pin name I/O circuit type M13 P10 AN00 G P11 AN M12 SIN1_1 FRCK0_2 G INT02_1 WKUP1 P L13 AN02 SOT1_1 G IC00_2 P13 AN L12 SCK1_1 IC01_2 G RTCCO_1 SUBOUT_1 P14 AN L11 SIN0_1 G IC02_2 INT03_1 P K13 AN05 SOT0_1 G IC03_2 P K12 AN06 SCK0_1 G INT20_1 P K14 AN07 SIN2_2 G INT04_1 - - M7 VSS L7 VSS K7 VSS - Pin type L N L L M L M M DS v01-22

25 Pin No LQFP-176 LQFP-144 BGA K J J J J J H10 Pin name P18 AN08 SOT2_2 INT21_1 P19 AN09 SCK2_2 INT22_1 P1A AN10 SIN4_1 IC00_1 TIOA13_2 INT05_1 P1B AN11 SOT4_1 IC01_1 TIOB13_2 INT25_1 P1C AN12 SCK4_1 IC02_1 TIOA14_2 INT26_1 P1D AN13 CTS4_1 IC03_1 TIOB14_2 INT27_1 P1 AN14 RTS4_1 DTTI0X_1 TIOA15_2 INT28_1 I/O circuit type G G G G G G G Pin type M M M M M M M 23 DS v01-

26 Pin No LQFP-176 LQFP-144 BGA-192 Pin name I/O circuit type P1F AN H9 ADTG_5 FRCK0_1 G TIOB15_2 INT29_1 PB H13 SIN7_2 TIOA09_1 INT16_0 PB H12 SOT7_2 TIOB09_1 INT17_0 PB H11 SCK7_2 TIOA10_1 INT18_0 PB G13 TIOB10_1 INT19_0 PB G12 SIN0_2 TIOA11_1 INT20_0 PB G11 SOT0_2 TIOB11_1 INT21_0 PB G10 SCK0_2 TIOA12_1 INT22_0 PB G9 TIOB12_1 INT23_ J14 AVCC H14 AVSS J7 VSS P11 VSS - Pin type M K K K K K K K K DS v01-24

27 Pin No I/O circuit Pin name LQFP-176 LQFP-144 BGA-192 type G14 AVRL F14 AVRH - P F10 AN16 G SIN12_0 P28 AN F11 ADTG_4 SOT12_0 G RTO05_1 INT09_0 P27 AN F12 SCK12_0 G RTO04_1 INT02_2 P F13 AN19 SCK2_1 G RTO03_1 P AN20 SOT2_1 G RTO02_1 P24 AN SIN2_1 G RTO01_1 INT01_2 Pin type L M M L L M 25 DS v01-

28 Pin No LQFP-176 LQFP-144 BGA-192 Pin name I/O circuit type P23 AN SCK0_0 G RTO00_1 TIOA07_1 P22 AN SOT0_0 G ZIN1_1 TIOB07_1 P D12 SIN0_0 BIN1_1 INT06_1 P D13 AIN1_1 INT05_0 CROUT_0 PF C13 NMIX WKUP P82 MCSX7_ D14 P83 MCSX6_ C14 VCC G7 VSS A13 VCC - Pin type L L K K I* H B13 P00 TRSTX P A12 TCK SWCLK C12 P02 TDI P B12 TMS SWDIO P B11 TDO SWO P C11 TIOB08_0 INT30_0 - - N14 VSS - J J I I I I I K DS v01-26

29 Pin No I/O circuit Pin Pin name LQFP-176 LQFP-144 BGA-192 type type P D11 TIOB09_0 INT31_0 K P B10 SIN5_1 TIOB10_0 J P C10 SOT5_1 TIOB11_0 J P D10 SCK5_1 TIOB12_0 INT26_0 K P B9 TIOB13_0 INT27_0 K PC C9 DA0_0 SIN13_0 MCSX5_0 H O PC B8 DA1_0 SOT13_0 MCSX4_0 H O PC D9 SCK13_0 MAD00_0 J PC TIOA06_1 MAD01_0 J PC F9 SIN14_0 TIOA08_2 CC0_1 MAD02_0 I* R PC C8 SOT14_0 TIOA10_2 MAD03_0 I* J - - L14 VSS - 27 DS v01-

30 Pin No I/O circuit Pin Pin name LQFP-176 LQFP-144 BGA-192 type type PC D8 SCK14_0 TIOA14_0 MAD04_0 I* J PC CROUT_1 RTCCO_0 SUBOUT_0 MAD05_0 J PC A10 SIN15_0 MAD06_0 J PC F8 SOT15_0 MAD07_0 J PCA B7 SCK15_0 MAD08_0 J A9 VCC G8 VSS A7 PCB MAD09_0 J C7 PCC MAD10_0 J A6 PCD MAD11_0 J PC D7 RTS4_0 TIOB06_1 MAD12_0 J PCF CTS4_0 TIOB08_2 MAD13_0 J PD F7 SCK4_0 TIOB10_2 INT30_1 MAD14_0 K PD B6 SOT4_0 TIOB14_0 INT31_1 MAD15_0 K - - B14 VSS H7 VSS B1 VSS G1 VSS - DS v01-28

31 Pin No LQFP-176 LQFP-144 BGA-192 Pin name I/O circuit type Pin type PD C6 SIN4_0 TIOA03_2 INT00_2 MAD16_0 K PD D6 TIOB03_2 MAD17_0 J P ADTG_3 SCK5_0 MAD18_0 J P B5 SOT5_0 TIOB02_2 MAD19_0 J P C5 SIN5_0 TIOA02_2 INT15_1 WKUP5 MAD20_0 U PF B4 SIN6_2 TIOA06_0 INT06_0 I* K PF C4 SOT6_2 TIOB06_0 INT07_0 I* K PF5 IGTRG0_ INT08_0 B3 WKUP3 CC1_0 I* T - SCK6_ A4 VCC A3 P80 K V A2 P81 K V H8 VSS J1 VSS - * : 5V tolerant I/O 29 DS v01-

32 List of pin functions The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (PFR) to select the pin. Pin function ADC Pin name Function description Pin No LQFP-176 LQFP-144 BGA-192 ADTG_ ADTG_ F5 ADTG_ K2 ADTG_ A/D converter external trigger input ADTG_ F11 pin ADTG_ H9 ADTG_ H6 ADTG_ L4 ADTG_ P8 AN M13 AN M12 AN L13 AN L12 AN L11 AN K13 AN K12 AN K14 AN K11 AN J13 AN J12 AN11 A/D converter analog input pin J11 AN12 ANxx describes ADC ch.xx J10 AN J9 AN H10 AN H9 AN F10 AN F11 AN F12 AN F13 AN AN AN AN DS v01-30

33 Pin function Base Timer 0 Base Timer 1 Base Timer 2 Base Timer 3 Base Timer 4 Base Timer 5 Base Timer 6 Pin name Function description Pin No LQFP-176 LQFP-144 BGA-192 TIOA00_ N2 TIOA00_1 Base timer ch.0 TIOA pin K3 TIOA00_ TIOB00_ L5 TIOB00_1 Base timer ch.0 TIOB pin 28 - H3 TIOB00_ TIOA01_ N3 TIOA01_1 Base timer ch.1 TIOA pin K4 TIOA01_ F3 TIOB01_ K5 TIOB01_1 Base timer ch.1 TIOB pin 29 - H4 TIOB01_ F4 TIOA02_ M3 TIOA02_1 Base timer ch.2 TIOA pin L1 TIOA02_ C5 TIOB02_ N6 TIOB02_1 Base timer ch.2 TIOB pin 30 - H5 TIOB02_ B5 TIOA03_ L4 TIOA03_1 Base timer ch.3 TIOA pin L2 TIOA03_ C6 TIOB03_ M6 TIOB03_1 Base timer ch.3 TIOB pin 31 - H6 TIOB03_ D6 TIOA04_ M4 TIOA04_1 Base timer ch.4 TIOA pin L3 TIOA04_ J6 TIOB04_ L6 TIOB04_1 Base timer ch.4 TIOB pin 32 - J5 TIOB04_ N8 TIOA05_ N4 TIOA05_1 Base timer ch.5 TIOA pin M2 TIOA05_2 8 8 D3 TIOB05_ K6 TIOB05_1 Base timer ch.5 TIOB pin 33 - J4 TIOB05_2 9 9 D4 TIOA06_ B4 TIOA06_1 Base timer ch.6 TIOA pin TIOA06_ H1 TIOB06_ C4 TIOB06_1 Base timer ch.6 TIOB pin D7 TIOB06_ H2 31 DS v01-

34 Pin function Base Timer 7 Base Timer 8 Base Timer 9 Base Timer 10 Base Timer 11 Base Timer 12 Base Timer 13 Pin name Function description Pin No LQFP-176 LQFP-144 BGA-192 TIOA07_ P10 TIOA07_1 Base timer ch.7 TIOA pin TIOA07_ J8 TIOB07_ K9 TIOB07_1 Base timer ch.7 TIOB pin TIOB07_ P9 TIOA08_0 2 2 B2 TIOA08_1 Base timer ch.8 TIOA pin 82 - N11 TIOA08_ F9 TIOB08_ C11 TIOB08_1 Base timer ch.8 TIOB pin 83 - M11 TIOB08_ TIOA09_0 3 3 C2 TIOA09_1 Base timer ch.9 TIOA pin H13 TIOA09_ F6 TIOB09_ D11 TIOB09_1 Base timer ch.9 TIOB pin H12 TIOB09_ G2 TIOA10_0 4 4 C3 TIOA10_1 Base timer ch.10 TIOA pin H11 TIOA10_ C8 TIOB10_ B10 TIOB10_1 Base timer ch.10 TIOB pin G13 TIOB10_ F7 TIOA11_0 5 5 D5 TIOA11_1 Base timer ch.11 TIOA pin G12 TIOA11_ G3 TIOB11_ C10 TIOB11_1 Base timer ch.11 TIOB pin G11 TIOB11_ G4 TIOA12_0 6 6 D2 TIOA12_1 Base timer ch.12 TIOA pin G10 TIOA12_ J3 TIOB12_ D10 TIOB12_1 Base timer ch.12 TIOB pin G9 TIOB12_ J2 TIOA13_0 7 7 D1 TIOA13_1 Base timer ch.13 TIOA pin G5 TIOA13_ J12 TIOB13_ B9 TIOB13_1 Base timer ch.13 TIOB pin G6 TIOB13_ J11 DS v01-32

35 Pin Pin No Pin name Function description function LQFP-176 LQFP-144 BGA-192 Base Timer TIOA14_ D8 14 TIOA14_1 Base timer ch.14 TIOA pin 78 - N10 TIOA14_ J10 TIOB14_ B6 TIOB14_1 Base timer ch.14 TIOB pin 79 - L10 TIOB14_ J9 Base Timer TIOA15_ N9 15 TIOA15_1 Base timer ch.15 TIOA pin 80 - K10 TIOA15_ H10 TIOB15_ M9 TIOB15_1 Base timer ch.15 TIOB pin 81 - M10 TIOB15_ H9 Debugger SWCLK Serial wire debug interface clock input A12 SWDIO Serial wire debug interface data input / output B12 SWO Serial wire viewer output B11 TCK J-TAG test clock input A12 TDI J-TAG test data input C12 TDO J-TAG debug data output B11 TMS J-TAG test mode input/output B12 TRACCLK Trace CLK output of TM TRACD0 8 8 D3 TRACD1 9 9 D4 Trace data output of TM TRACD TRACD TRSTX J-TAG test reset B13 33 DS v01-

36 Pin function xternal Bus Pin name Function description Pin No LQFP-176 LQFP-144 BGA-192 MAD00_ D9 MAD01_ MAD02_ F9 MAD03_ C8 MAD04_ D8 MAD05_ MAD06_ A10 MAD07_ F8 MAD08_ B7 MAD09_ A7 MAD10_ C7 MAD11_ A6 MAD12_0 xternal bus interface address bus D7 MAD13_ MAD14_ F7 MAD15_ B6 MAD16_ C6 MAD17_ D6 MAD18_ MAD19_ B5 MAD20_ C5 MAD21_0 2 2 B2 MAD22_0 3 3 C2 MAD23_0 4 4 C3 MAD24_0 5 5 D5 MCSX0_ G5 MCSX1_ G6 MCSX2_ N2 MCSX3_0 xternal bus interface chip select N3 MCSX4_0 output pin B8 MCSX5_ C9 MCSX6_ D14 MCSX7_ MDQM0_0 xternal bus interface byte mask F2 MDQM1_0 signal output F3 MOX_0 xternal bus interface read enable signal for SRAM MWX_0 xternal bus interface write enable signal for SRAM F1 DS v01-34

37 Pin function xternal Bus Pin name Function description Pin No LQFP-176 LQFP-144 BGA-192 MNAL_0 xternal bus interface AL signal to control NAND Flash output pin F6 MNCL_0 xternal bus interface CL signal to control NAND Flash output pin G2 MNRX_0 xternal bus interface read enable signal to control NAND Flash G4 MNWX_0 xternal bus interface write enable signal to control NAND Flash G3 MADATA00_ K5 MADATA01_ N6 MADATA02_ M6 MADATA03_ L6 MADATA04_ K6 MADATA05_ J6 MADATA06_ N8 MADATA07_0 xternal bus interface data bus M8 MADATA08_0 (Address / data multiplex bus) L8 MADATA09_ K8 MADATA10_ P8 MADATA11_ J8 MADATA12_ P9 MADATA13_ N9 MADATA14_ M9 MADATA15_ L9 MAL_0 xternal bus interface Address Latch enable output signal for multiplex F4 MRDY_0 xternal bus interface external RDY input signal F5 MCLKOUT_0 xternal bus interface external clock output M3 35 DS v01-

38 Pin function xternal Interrupt Pin No Function description LQFP-176 LQFP-144 BGA-192 INT00_ xternal interrupt request 00 input INT00_1 8 8 D3 pin INT00_ C6 INT01_ F1 xternal interrupt request 01 input INT01_1 9 9 D4 pin INT01_ INT02_ F2 xternal interrupt request 02 input INT02_ M12 pin INT02_ F12 INT03_0 6 6 D2 xternal interrupt request 03 input INT03_ L11 pin INT03_ H3 INT04_ H6 xternal interrupt request 04 input INT04_ K14 pin INT04_ H4 INT05_ D13 xternal interrupt request 05 input INT05_ J12 pin INT05_ H5 INT06_ B4 xternal interrupt request 06 input INT06_ D12 pin INT06_ K6 INT07_ C4 xternal interrupt request 07 input INT07_ P8 pin INT07_ F3 INT08_ B3 xternal interrupt request 08 input INT08_ J4 pin INT08_ F6 INT09_ F11 xternal interrupt request 09 input INT09_ J3 pin INT09_ G4 INT10_ K9 xternal interrupt request 10 input INT10_ J2 pin INT10_2 7 7 D1 INT11_ P10 xternal interrupt request 11 input INT11_ K1 pin INT11_ J8 INT12_ N10 xternal interrupt request 12 input INT12_ N2 pin INT12_ P9 INT13_ M10 xternal interrupt request 13 input INT13_ N3 pin INT13_ N8 INT14_ N11 xternal interrupt request 14 input INT14_ M5 pin INT14_ M8 Pin name DS v01-36

39 Pin function xternal Interrupt Function description Pin No LQFP-176 LQFP-144 BGA-192 INT15_ M11 xternal interrupt request 15 input INT15_ C5 pin INT15_ L8 INT16_0 xternal interrupt request 16 input H13 INT16_1 pin G2 INT17_0 xternal interrupt request 17 input H12 INT17_1 pin G3 INT18_0 xternal interrupt request 18 input H11 INT18_1 pin G5 INT19_0 xternal interrupt request 19 input G13 INT19_1 pin G6 INT20_0 xternal interrupt request 20 input G12 INT20_1 pin K12 INT21_0 xternal interrupt request 21 input G11 INT21_1 pin K11 INT22_0 xternal interrupt request 22 input G10 INT22_1 pin J13 INT23_0 xternal interrupt request 23 input G9 INT23_1 pin M9 INT24_0 xternal interrupt request 24 input 79 - L10 INT24_1 pin L9 INT25_0 xternal interrupt request 25 input 80 - K10 INT25_1 pin J11 INT26_0 xternal interrupt request 26 input D10 INT26_1 pin J10 INT27_0 xternal interrupt request 27 input B9 INT27_1 pin J9 INT28_0 xternal interrupt request 28 input 25 - H1 INT28_1 pin H10 INT29_0 xternal interrupt request 29 input 26 - H2 INT29_1 pin H9 INT30_0 xternal interrupt request 30 input C11 INT30_1 pin F7 INT31_0 xternal interrupt request 31 input D11 INT31_1 pin B6 NMIX Non-Maskable Interrupt input C13 Pin name 37 DS v01-

40 Pin function GPIO Function description Pin No LQFP-176 LQFP-144 BGA-192 P B13 P A12 P C12 P B12 P B11 General-purpose I/O port 0 P D3 P D4 P P P P M13 P M12 P L13 P L12 P L11 P K13 P K12 P K14 General-purpose I/O port 1 P K11 P J13 P1A J12 P1B J11 P1C J10 P1D J9 P H10 P1F H9 P D13 P D12 P P P General-purpose I/O port 2 P P F13 P F12 P F11 P F10 Pin name DS v01-38

41 Pin function GPIO Function description Pin No LQFP-176 LQFP-144 BGA-192 P H3 P H4 P H5 P H6 P J5 P J4 P J3 P J2 General-purpose I/O port 3 P K1 P K2 P3A K3 P3B K4 P3C L1 P3D L2 P L3 P3F M2 P N2 P N3 P M3 P L4 P M4 P N4 P P5 P47 General-purpose I/O port P6 P M5 P L5 P4A K5 P4B N6 P4C M6 P4D L6 P K6 P P F1 P F2 P F3 P F4 P F5 P F6 General-purpose I/O port 5 P G2 P G3 P G4 P5A G5 P5B G6 P5C 25 - H1 P5D 26 - H2 Pin name 39 DS v01-

42 Pin function GPIO Function description Pin No LQFP-176 LQFP-144 BGA-192 P C5 P61 General-purpose I/O port B5 P P J6 P N8 P M8 P L8 P K8 P P8 P J8 P P9 General-purpose I/O port 7 P N9 P M9 P7A L9 P7B 76 - K9 P7C 77 - P10 P7D 78 - N10 P L10 P7F 80 - K10 P A3 P A2 General-purpose I/O port 8 P P D14 P C11 P D11 P B10 General-purpose I/O port 9 P C10 P D10 P B9 PA0 2 2 B2 PA1 3 3 C2 PA2 4 4 C3 General-purpose I/O port A PA3 5 5 D5 PA4 6 6 D2 PA5 7 7 D1 PB H13 PB H12 PB H11 PB G13 General-purpose I/O port B PB G12 PB G11 PB G10 PB G9 Pin name DS v01-40

43 Pin function GPIO Function description Pin No LQFP-176 LQFP-144 BGA-192 PC C9 PC B8 PC D9 PC PC F9 PC C8 PC D8 PC General-purpose I/O port C PC A10 PC F8 PCA B7 PCB A7 PCC C7 PCD A6 PC D7 PCF PD F7 PD B6 General-purpose I/O port D PD C6 PD D6 P N13 P2 General-purpose I/O port P12 P P13 PF M10 PF N11 PF M11 PF3 General-purpose I/O port F * B4 PF C4 PF B3 PF C13 Pin name 41 DS v01-

44 Pin function Multi Function Serial 0 Multi Function Serial 1 Function description Pin No. LQFP-176 LQFP-144 BGA-192 SIN0_ D12 Multifunction serial interface ch.0 SIN0_ L11 input pin SIN0_ G12 SOT0_0 Multifunction serial interface ch.0 (SDA0_0) output pin SOT0_1 This pin operates as SOT0 when it is (SDA0_1) used in a UART/CSIO (operation K13 SOT0_2 modes 0 to 2) and as SDA0 when it (SDA0_2) is used in an I 2 C (operation mode 4) G11 SCK0_0 Multifunction serial interface ch.0 (SCL0_0) clock I/O pin SCK0_1 This pin operates as SCK0 when it is (SCL0_1) used in a UART/CSIO (operation K12 SCK0_2 modes 0 to 2) and as SCL0 when it is (SCL0_2) used in an I 2 C (operation mode 4) G10 SIN1_ F6 Multifunction serial interface ch.1 SIN1_ M12 input pin SIN1_ M10 SOT1_0 Multifunction serial interface ch.1 (SDA1_0) output pin G2 SOT1_1 This pin operates as SOT1 when it is (SDA1_1) used in a UART/CSIO (operation L13 SOT1_2 modes 0 to 2) and as SDA1 when it (SDA1_2) is used in an I 2 C (operation mode 4) N11 Pin name SCK1_0 (SCL1_0) SCK1_1 (SCL1_1) SCK1_2 (SCL1_2) Multifunction serial interface ch.1 clock I/O pin. This pin operates as SCK1 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL1 when it is used in an I 2 C (operation mode 4) G L M11 DS v01-42

45 Pin function Multi Function Serial 2 Multi Function Serial 3 Function description Pin No. LQFP-176 LQFP-144 BGA-192 SIN2_ M8 Multifunction serial interface ch.2 SIN2_ input pin SIN2_ K14 SOT2_0 Multifunction serial interface ch.2 (SDA2_0) output pin L8 SOT2_1 This pin operates as SOT2 when it is (SDA2_1) used in a UART/CSIO (operation SOT2_2 modes 0 to 2) and as SDA2 when it (SDA2_2) is used in an I 2 C (operation mode 4) K11 SCK2_0 Multifunction serial interface ch.2 (SCL2_0) clock I/O pin K8 SCK2_1 This pin operates as SCK2 when it is (SCL2_1) used in a UART/CSIO (operation F13 SCK2_2 modes 0 to 2) and as SCL2 when it is (SCL2_2) used in an I 2 C (operation mode 4) J13 SIN3_ P8 Multifunction serial interface ch.3 SIN3_ input pin SIN3_ M5 SOT3_0 Multifunction serial interface ch.3 (SDA3_0) output pin J8 SOT3_1 This pin operates as SOT3 when it is (SDA3_1) used in a UART/CSIO (operation F1 SOT3_2 modes 0 to 2) and as SDA3 when it (SDA3_2) is used in an I 2 C (operation mode 4) L5 Pin name SCK3_0 (SCL3_0) SCK3_1 (SCL3_1) SCK3_2 (SCL3_2) Multifunction serial interface ch.3 clock I/O pin. This pin operates as SCK3 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL3 when it is used in an I 2 C (operation mode 4) P F K5 43 DS v01-

46 Pin function Multi Function Serial 4 Multi Function Serial 5 Function description Pin No. LQFP-176 LQFP-144 BGA-192 SIN4_ C6 Multifunction serial interface ch.4 SIN4_ J12 input pin SIN4_2 8 8 D3 SOT4_0 Multifunction serial interface ch.4 (SDA4_0) output pin B6 SOT4_1 This pin operates as SOT4 when it is (SDA4_1) used in a UART/CSIO (operation J11 SOT4_2 modes 0 to 2) and as SDA4 when it (SDA4_2) is used in an I 2 C (operation mode 4). 9 9 D4 SCK4_0 Multifunction serial interface ch.4 (SCL4_0) clock I/O pin F7 SCK4_1 This pin operates as SCK4 when it is (SCL4_1) used in a UART/CSIO (operation J10 SCK4_2 modes 0 to 2) and as SCL4 when it is (SCL4_2) used in an I 2 C (operation mode 4) RTS4_ D7 Multifunction serial interface ch.4 RTS4_ H10 RTS output pin RTS4_ CTS4_ Multifunction serial interface ch.4 CTS4_ J9 CTS input pin CTS4_ SIN5_ C5 Multifunction serial interface ch.5 SIN5_ B10 input pin SIN5_ J3 Pin name SOT5_0 (SDA5_0) SOT5_1 (SDA5_1) SOT5_2 (SDA5_2) SCK5_0 (SCL5_0) SCK5_1 (SCL5_1) SCK5_2 (SCL5_2) Multifunction serial interface ch.5 output pin. This pin operates as SOT5 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA5 when it is used in an I 2 C (operation mode 4). Multifunction serial interface ch.5 clock I/O pin. This pin operates as SCK5 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL5 when it is used in an I 2 C (operation mode 4) B C J D K1 DS v01-44

47 Pin function Multi Function Serial 6 Multi Function Serial 7 Function description Pin No. LQFP-176 LQFP-144 BGA-192 SIN6_ F3 Multifunction serial interface ch.6 SIN6_ H6 input pin SIN6_ B4 SOT6_0 Multifunction serial interface ch.6 (SDA6_0) output pin F4 SOT6_1 This pin operates as SOT6 when it is (SDA6_1) used in a UART/CSIO (operation 30 - H5 SOT6_2 modes 0 to 2) and as SDA6 when it (SDA6_2) is used in an I 2 C (operation mode 4) C4 SCK6_0 Multifunction serial interface ch.6 (SCL6_0) clock I/O pin F5 SCK6_1 This pin operates as SCK6 when it is (SCL6_1) used in a UART/CSIO (operation 29 - H4 SCK6_2 modes 0 to 2) and as SCL6 when it is (SCL6_2) used in an I 2 C (operation mode 4) B3 SIN7_ G4 Multifunction serial interface ch.7 SIN7_ K6 input pin SIN7_ H13 Pin name SOT7_0 (SDA7_0) SOT7_1 (SDA7_1) SOT7_2 (SDA7_2) SCK7_0 (SCL7_0) SCK7_1 (SCL7_1) SCK7_2 (SCL7_2) Multifunction serial interface ch.7 output pin. This pin operates as SOT7 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA7 when it is used in an I 2 C (operation mode 4). Multifunction serial interface ch.7 clock I/O pin. This pin operates as SCK7 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL7 when it is used in an I 2 C (operation mode 4) G L H G M H11 45 DS v01-

48 Pin function Multi Function Serial 8 Multi Function Serial 9 Pin name SIN8_0 SOT8_0 (SDA8_0) SCK8_0 (SCL8_0) SIN9_0 SOT9_0 (SDA9_0) SCK9_0 (SCL9_0) Function description Multifunction serial interface ch.8 input pin Multifunction serial interface ch.6 output pin. This pin operates as SOT8 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA8 when it is used in an I 2 C (operation mode 4). Multifunction serial interface ch.7 clock I/O pin. This pin operates as SCK8 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL8 when it is used in an I 2 C (operation mode 4). Multifunction serial interface ch.9 input pin Multifunction serial interface ch.9 output pin. This pin operates as SOT9 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA9 when it is used in an I 2 C (operation mode 4). Multifunction serial interface ch.9 clock I/O pin. This pin operates as SCK9 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL9 when it is used in an I 2 C (operation mode 4). Pin No. LQFP-176 LQFP-144 BGA B2 3 3 C2 4 4 C3 5 5 D5 6 6 D2 7 7 D1 DS v01-46

49 Pin function Multi Function Serial 10 Multi Function Serial 11 Pin name SIN10_0 SOT10_0 (SDA10_0) SCK10_0 (SCL10_0) SIN11_0 SOT11_0 (SDA11_0) SCK11_0 (SCL11_0) Function description Multifunction serial interface ch.10 input pin Multifunction serial interface ch.10 output pin. This pin operates as SOT10 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA10 when it is used in an I 2 C (operation mode 4). Multifunction serial interface ch.10 clock I/O pin. This pin operates as SCK10 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL10 when it is used in an I 2 C (operation mode 4). Multifunction serial interface ch.11 input pin Multifunction serial interface ch.11 output pin. This pin operates as SOT11 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA11 when it is used in an I 2 C (operation mode 4). Multifunction serial interface ch.11 clock I/O pin. This pin operates as SCK11 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL11 when it is used in an I 2 C (operation mode 4). Pin No. LQFP-176 LQFP-144 BGA N N M L M N4 47 DS v01-

50 Pin function Multi Function Serial 12 Multi Function Serial 13 Pin name SIN12_0 SOT12_0 (SDA12_0) SCK12_0 (SCL12_0) SIN13_0 SOT13_0 (SDA13_0) SCK13_0 (SCL13_0) Function description Multifunction serial interface ch.12 input pin Multifunction serial interface ch.12 output pin. This pin operates as SOT12 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA12 when it is used in an I 2 C (operation mode 4). Multifunction serial interface ch.12 clock I/O pin. This pin operates as SCK12 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL12 when it is used in an I 2 C (operation mode 4). Multifunction serial interface ch.13 input pin Multifunction serial interface ch.13 output pin. This pin operates as SOT13 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA13 when it is used in an I 2 C (operation mode 4). Multifunction serial interface ch.13 clock I/O pin. This pin operates as SCK13 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL13 when it is used in an I 2 C (operation mode 4). Pin No. LQFP-176 LQFP-144 BGA F F F C B D9 DS v01-48

51 Pin function Multi Function Serial 14 Multi Function Serial 15 Pin name SIN14_0 SOT14_0 (SDA14_0) SCK14_0 (SCL14_0) SIN15_0 SOT15_0 (SDA15_0) SCK15_0 (SCL15_0) Function description Multifunction serial interface ch.14 input pin Multifunction serial interface ch.14 output pin. This pin operates as SOT14 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA14 when it is used in an I 2 C (operation mode 4). Multifunction serial interface ch.14 clock I/O pin. This pin operates as SCK14 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL14 when it is used in an I 2 C (operation mode 4). Multifunction serial interface ch.15 input pin Multifunction serial interface ch.15 output pin. This pin operates as SOT15 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA15 when it is used in an I 2 C (operation mode 4). Multifunction serial interface ch.15 clock I/O pin. This pin operates as SCK15 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL15 when it is used in an I 2 C (operation mode 4). Pin No. LQFP-176 LQFP-144 BGA F C D A F B7 49 DS v01-

52 Pin function Multi Function Timer 0 Pin name Function description Pin No LQFP-176 LQFP-144 BGA-192 DTTI0X_0 signal controlling wave form K2 generator outputs RTO00 to RTO05 DTTI0X_1 of multi-function timer H10 FRCK0_ J5 16-bit free-run timer ch.0 external FRCK0_ H9 clock input pin FRCK0_ M12 IC00_ K1 IC00_ J12 IC00_ L13 IC01_ J2 IC01_ J11 16-bit input capture ch.0 input pin of IC01_ L12 multi-function timer 0. IC02_ J3 ICxx describes channel number. IC02_ J10 IC02_ L11 IC03_ J4 IC03_ J9 IC03_ K13 RTO00_0 Wave form generator output of (PPG00_0) multi-function timer K3 RTO00_1 This pin operates as PPG00 when it (PPG00_1) is used in PPG0 output modes RTO01_0 Wave form generator output of (PPG00_0) multi-function timer K4 RTO01_1 This pin operates as PPG00 when it (PPG00_1) is used in PPG0 output modes RTO02_0 Wave form generator output of (PPG02_0) multi-function timer L1 RTO02_1 This pin operates as PPG02 when it (PPG02_1) is used in PPG0 output modes RTO03_0 Wave form generator output of (PPG02_0) multi-function timer L2 RTO03_1 This pin operates as PPG02 when it (PPG02_1) is used in PPG0 output modes F13 RTO04_0 Wave form generator output of (PPG04_0) multi-function timer L3 RTO04_1 This pin operates as PPG04 when it (PPG04_1) is used in PPG0 output modes F12 RTO05_0 Wave form generator output of (PPG04_0) multi-function timer M2 RTO05_1 This pin operates as PPG04 when it (PPG04_1) is used in PPG0 output modes F11 IGTRG0_0 PPG IGBT mode external trigger N6 IGTRG0_1 input pin B3 DS v01-50

53 Pin function Quadrature Position/ Revolution Counter 0 Quadrature Position/ Revolution Counter 1 CAN Real-time clock Pin name Function description Pin No LQFP-176 LQFP-144 BGA-192 AIN0_ H3 AIN0_1 QPRC ch.0 AIN input pin L5 AIN0_ BIN0_ H4 BIN0_1 QPRC ch.0 BIN input pin K5 BIN0_ F1 ZIN0_ H5 ZIN0_1 QPRC ch.0 ZIN input pin N6 ZIN0_ F2 AIN1_ N9 AIN1_1 QPRC ch.1 AIN input pin D13 AIN1_ M6 BIN1_ M9 BIN1_1 QPRC ch.1 BIN input pin D12 BIN1_ L6 ZIN1_ L9 ZIN1_1 QPRC ch.1 ZIN input pin ZIN1_ K6 TX0_ J6 TX0_1 CAN interface ch.0 TX output 32 - J5 TX0_2 7 7 D1 RX0_ N8 RX0_1 CAN interface ch.0 RX output 33 - J4 RX0_2 6 6 D2 RTCCO_ seconds pulse output pin of Realtime clock RTCCO_ L12 RTCCO_ K2 SUBOUT_ SUBOUT_1 Sub clock output pin L12 SUBOUT_ K2 51 DS v01-

54 Pin function RST Mode POWR Low-Power Consumption Mode Pin name INITX MD0 MD1 VCC WKUP0 WKUP1 WKUP2 WKUP3 WKUP4 WKUP5 Function description xternal Reset. A reset is valid when INITX="L". Mode 0 Pin. During normal operation, MD0="L" must be input. During serial programming to Flash memory, MD0="H" must be input. Mode 1 Pin. During serial programming to Flash memory, MD1="L" must be input. Power supply Pin Deep standby mode return signal input pin 0 Deep standby mode return signal input pin 1 Deep standby mode return signal input pin 2 Deep standby mode return signal input pin 3 Deep standby mode return signal input pin 4 Deep standby mode return signal input pin 5 Pin No LQFP-176 LQFP-144 BGA N N N C N P M C A A C M M B H C5 HDMI- CC0_0 HDMI-CC/Remote Control 81 - M10 CC/ CC0_1 Reception ch.0 input/output pin F9 Remote Control CC1_0 HDMI-CC/Remote Control B3 Reception CC1_1 Reception ch.1 input/output pin F6 DAC DA0_0 D/A converter ch.0 analog output pin C9 DA1_0 D/A converter ch.1 analog output pin B8 DS v01-52

55 Pin function GND Pin name VSS GND Pin Function description Pin No LQFP-176 LQFP-144 BGA A A A G G H8 - - M1 - - P3 - - P7 - - N7 - - M7 - - L7 - - K7 - - J7 - - P N L B H7 - - B1 - - G1 - - J1 CLOCK X0 Main clock (oscillation) input pin P12 X0A Sub clock (oscillation) input pin P5 X1 Main clock (oscillation) I/O pin P13 X1A Sub clock (oscillation) I/O pin P6 CROUT_ D13 CR-osc clock output port CROUT_ Analog A/D converter, D/A converter analog AVCC POWR power pin J14 AVRH A/D converter analog reference voltage input pin F14 Analog A/D converter, D/A converter GND AVSS GND pin H14 AVRL A/D converter analog reference voltage input pin G14 C pin Power supply stabilization capacity C pin P2 *: 5V tolerant I/O 53 DS v01-

56 I/O CIRCUIT TYP Type Circuit Remarks A It is possible to select the main oscillation / GPIO function X1 P-ch P-ch Digital output When the main oscillation is. Oscillation feedback resistor : Approximately 1MΩ With Standby mode control R N-ch Digital output Pull-up resistor control Digital input When the GPIO is. CMOS level output. CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50kΩ I OH = -4mA, I OL = 4mA Standby mode control Clock input Standby mode control Digital input Standby mode control R X0 P-ch P-ch Digital output N-ch Digital output Pull-up resistor control B Pull-up resistor CMOS level hysteresis input Pull-up resistor : Approximately 50kΩ Digital input DS v01-54

57 Type Circuit Remarks C Open drain output CMOS level hysteresis input Digital input N-ch Digital output D It is possible to select the sub oscillation / GPIO function X1A P-ch P-ch Digital output When the sub oscillation is. Oscillation feedback resistor : Approximately 5MΩ With Standby mode control R N-ch Digital output Pull-up resistor control Digital input When the GPIO is. CMOS level output. CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50kΩ I OH = -4mA, I OL = 4mA Standby mode control Clock input Standby mode control Digital input Standby mode control R X0A P-ch P-ch Digital output N-ch Digital output Pull-up resistor control 55 DS v01-

58 Type Circuit Remarks CMOS level output CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor P-ch P-ch Digital output : Approximately 50kΩ I OH = -4mA, I OL = 4mA When this pin is used as an I 2 C pin, the digital output P-ch transistor is always off R N-ch Digital output Pull-up resistor control Digital input Standby mode control F P-ch P-ch Digital output CMOS level output CMOS level hysteresis input With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50kΩ I OH = -12mA, I OL = 12mA R N-ch Digital output Pull-up resistor control Digital input Standby mode control DS v01-56

59 Type Circuit Remarks G CMOS level output CMOS level hysteresis input With input control Analog input With pull-up resistor control P-ch P-ch Digital output With standby mode control Pull-up resistor : Approximately 50kΩ I OH = -4mA, I OL = 4mA When this pin is used as an N-ch Digital output I 2 C pin, the digital output P-ch transistor is always off R Pull-up resistor control Digital input Standby mode control Analog input control H P-ch P-ch N-ch Digital output Digital output CMOS level output CMOS level hysteresis input With input control Analog output With pull-up resistor control With standby mode control Pull-up resistor : Approximately 50kΩ I OH = -4mA, I OL = 4mA R Pull-up resistor control Digital input Standby mode Control Analog output 57 DS v01-

60 Type Circuit Remarks I CMOS level output CMOS level hysteresis input 5V tolerant With pull-up resistor control With standby mode control P-ch P-ch Digital output Pull-up resistor N-ch Digital output : Approximately 50kΩ I OH = -4mA, I OL = 4mA Available to control PZR registers. When this pin is used as an R I 2 C pin, the digital output P-ch transistor is always off Pull-up resistor control Digital input Standby mode control J CMOS level hysteresis input Mode input K CMOS level output CMOS level hysteresis input With standby mode control I OH = -18.0mA, I OL = 16.5mA P-ch Digital output R N-ch Digital output Digital input Standby mode Control DS v01-58

61 HANDLING PRCAUTIONS Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your FUJITSU SMICONDUCTOR semiconductor devices. 1. Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices. Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. (1) Preventing Over-Voltage and Over-Current Conditions xposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. (2) Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. (3) Handling of Unused Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin. Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred ma to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: (1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. (2) Be sure that abnormal current flows do not occur during the power-on sequence. Code: DS a 59 DS v01-

62 Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Precautions Related to Usage of Devices FUJITSU SMICONDUCTOR semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 2. Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under FUJITSU SMICONDUCTOR's recommended conditions. For detailed information about mount conditions, contact your sales representative. Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to FUJITSU SMICONDUCTOR recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. FUJITSU SMICONDUCTOR recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with FUJITSU SMICONDUCTOR ranking of recommended conditions. DS v01-60

63 Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: (1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. (2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5 C and 30 C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. (3) When necessary, FUJITSU SMICONDUCTOR packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. (4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust. Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the FUJITSU SMICONDUCTOR recommended conditions for baking. Condition: 125 C/24 h Static lectricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: (1) relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. (2) lectrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3) liminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. (4) Ground all fixtures and instruments, or protect with anti-static measures. (5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies. 61 DS v01-

64 3. Precautions for Use nvironment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: (1) Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. (2) Discharge of Static lectricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. (3) Corrosive Gases, Dust, or Oil xposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4) Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. (5) Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of FUJITSU SMICONDUCTOR products in other special environmental conditions should consult with sales representatives. Please check the latest handling precautions at the following URL. DS v01-62

65 HANDLING DVICS Power supply pins In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µf be connected as a bypass capacitor between each Power supply pin and GND pin near this device. Stabilizing power supply voltage A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a momentary fluctuation on switching the power supply. Crystal oscillator circuit Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1, X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by ground plane as this is expected to produce stable operation. valuate oscillation of your using crystal oscillator by your mount board. Sub crystal oscillator This series sub oscillator circuit is low gain to keep the low current consumption. The crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation. Surface mount type Size : More than 3.2mm 1.5mm Load capacitance : Approximately 6pF to 7pF Lead type Load capacitance : Approximately 6pF to 7pF 63 DS v01-

66 Using an external clock When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1(P3) can be used as a general-purpose I/O port. Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input, and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port. xample of Using an xternal Clock Device Can be used as general-purpose I/O ports. X0(X0A) X1(P3), X1A (P47) Set as xternal clock input Handling when using Multi-function serial pin as I 2 C pin If it is using the multi-function serial pin as I 2 C pins, P-ch transistor of digital output is always disabled. However, I 2 C pins need to keep the electrical characteristic like other pins and not to connect to the external I 2 C bus system with power OFF. C Pin This series contains the regulator. Be sure to connect a smoothing capacitor (C S ) for the regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. A smoothing capacitor of about 4.7μF would be recommended for this series. Device C VSS C S Mode pins (MD0) Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is because of preventing the device erroneously switching to test mode due to noise. GND DS v01-64

67 Notes on power-on Turn power on/off in the following order or at the same time. If not using the A/D converter and D/A converter, connect AVCC = VCC and AVSS = VSS. Turning on : VCC AVCC AVRH Turning off : AVRH AVCC VCC Serial Communication There is a possibility to receive wrong data due to the noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. If an error is detected, retransmit the data. Differences in features among the products with different memory sizes and between Flash memory products and MASK products The electric characteristics including power consumption, SD, latch-up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between Flash memory products and MASK products are different because chip layout and memory structures are different. If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics. Pull-Up function of 5V tolerant I/O Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5V tolerant I/O. Adjoining wiring on circuit board If wiring of the crystal oscillation circuit (X0/X1 and X0A/X1A) adjoins and also runs in parallel with the wiring of GPIO, there is a possibility that the oscillation erroneously counts because oscillation wave has noise with the change of GPIO. Keep as much distance as possible between both wirings and insert the ground pattern between them in order to avoid this possibility. 65 DS v01-

68 BLOCK DIAGRAM TRSTX,TCK, TDI,TMS TDO TRACDx, TRACCLK INITX SWJ-DP TPIU Cortex-M3 MHz(Max) Dual-Timer Clock Reset Generator WatchDog Timer (Hardware) CSV NVIC WatchDog Timer (Software) TM ROM Table I D Sys AHB-APB Bridge: APB0(Max 32 MHz) Multi-layer AHB (Max 60 MHz) Flash I/F Security SRAM0 80/96 Kbytes SRAM1 80/96 Kbytes On-Chip Flash 1 Mbytes+64 Kbytes/ 1.5 Mbytes+64 Kbytes DMAC 8ch. CLK X0 X1 X0A X1A CROUT Main Osc Sub Osc PLL CR 4 MHz Source Clock CR 100 khz AHB-AHB Bridge CAN 1ch. TX0_x, RX0_x MADx AVCC, AVSS, AVRH ANxx ADTGx 12-bit A/D Converter Unit 0 Unit 1 xternal Bus I/F CAN Prescaler MADATAx MCSXx,MDQMx, MOX,MWX, MAL,MRDY, MNAL,MNCL, MNWX,MNRX, MCLKOUT TIOAx TIOBx Base Timer 16-bit 16ch./ 32-bit 8ch. LVD Ctrl Power-On Reset LVD AINx BINx ZINx IC0x FRCK0 DTTI0X RTO0x IGTRGx QPRC 2ch. A/D Activation Compare 3ch. 16-bit Capture 4ch. 16-bit Free-run Timer 3ch. 16-bit Output Compare 6ch. Waveform Generator 3ch. 16-bit PPG 3ch. Multi-function Timer 1 AHB-APB Bridge : APB1 (Max 32 MHz) AHB-APB Bridge : APB2 (Max 32 MHz) IRQ-Monitor CRC Accelerator Watch Counter Deep Standby Ctrl HDMI-CC/ Remote Reciver Control Real-Time Clock xternal Interrupt Controller 32pin + NMI MOD-Ctrl GPIO Multi-function Serial I/F 16ch. HW flow control(ch.4) Regulator PIN-Function-Ctrl C WKUPx CC0_x, CC1_x RTCCO, SUBOUT INTx NMIX MD0, MD1 P0x, P1x,... PFx SCKx SINx SOTx CTS4 RTS4 MMORY SIZ See " Memory size" in " PRODUCT LINUP" to confirm the memory size. DS v01-66

69 4 MMORY MAP Memory Map (1) 0x41FF_FFFF Peripherals Area Reserved 0xFFFF_FFFF Reserved 0x010_0000 Cortex-M3 Private 0x4006_3000 0x000_0000 Peripherals 0x4006_2000 CAN ch.0 0x4006_1000 Reserved 0x4006_0000 DMAC See " Memory map(2)" for the memory size details. Reserved 0x4004_0000 xternal Device 0x4003_F000 XT-bus I/F Area 0x4003_C000 Reserved 0x4003_B000 RTC 0x4003_A000 Watch Counter 0x6000_0000 0x4003_9000 CRC 0x4003_8000 MFS Reserved 0x4003_7000 CAN Prescaler 0x4400_0000 0x4003_6000 Reserved 32Mbytes 0x4003_5000 LVD/DS mode 0x4200_0000 Bit band alias 0x4003_4000 HDMI-CC 0x4003_3000 GPIO Peripherals 0x4000_0000 0x4003_2000 Reserved 0x4003_1000 Int-Req.Read Reserved 0x2400_0000 0x4003_0000 XTI 32Mbytes 0x4002_F000 Reserved 0x2200_0000 Bit band alias 0x4002_000 CR Trim 0x4002_9000 Reserved Reserved 0x2001_8000 0x4002_8000 D/AC 0x2000_0000 SRAM1 0x4002_7000 A/DC 0x1FF_8000 SRAM0 0x4002_6000 QPRC 0x4002_5000 Base Timer Reserved 0x0051_8000 0x4002_4000 PPG 0x0050_8000 Flash(Work area) 0x0040_4000 Reserved Reserved 0x0040_0000 Security/CR Trim 0x4002_1000 0x4002_0000 MFT unit0 0x0000_0000 Flash(Main area) 0x4001_6000 0x4001_5000 0x4001_3000 0x4001_2000 0x4001_1000 0x4001_0000 0x4000_1000 0x4000_0000 Reserved Dual Timer Reserved SW WDT HW WDT Clock/Reset Reserved Flash I/F 67 DS v01-

70 Memory Map (2) MB9BF429S/T MB9BF428S/T 0x2008_0000 0x2008_0000 0x2001_8000 Reserved Reserved SRAM1 80Kbytes 0x2001_4000 SRAM1 64Kbytes 0x2000_4000 0x2000_4000 0x2000_0000 SRAM1 16Kbytes* 0x2000_0000 SRAM1 16Kbytes* 0x1FFF_C000 SRAM0 16Kbytes* 0x1FFF_C000 SRAM0 16Kbytes* SRAM0 80Kbytes 0x1FF_C000 SRAM0 64Kbytes 0x1FF_8000 Reserved Reserved 0x0051_8000 0x0050_8000 Flash (Work area, ROM1) 64Kbytes 0x0051_8000 0x0050_8000 Flash (Work area, ROM1) 64Kbytes Reserved Reserved 0x0040_4000 0x0040_4000 0x0040_2000 CR trimming 0x0040_2000 CR trimming 0x0040_0000 Security 0x0040_0000 Security Reserved 0x0018_0000 Reserved 0x0010_0000 Flash (Main area, ROM1) 512Kbytes 0x0010_0000 Flash (Main area, ROM0) 1Mbytes Flash (Main area, ROM0) 1Mbytes 0x0000_0000 0x0000_0000 *:The content of SRAM can be retained at the deep standby modes by the setting of Deep Standby RAM Retention Register (DSRAMR). See "MB9B520T/420T/320T/120T Series Flash programming Manual" for sector structure of Flash. DS v01-68

71 4 Peripheral Address Map Start address nd address Bus Peripherals 0x4000_0000 0x4000_0FFF Flash Memory I/F register AHB 0x4000_1000 0x4000_FFFF Reserved 0x4001_0000 0x4001_0FFF Clock/Reset Control 0x4001_1000 0x4001_1FFF Hardware Watchdog timer 0x4001_2000 0x4001_2FFF Software Watchdog timer APB0 0x4001_3000 0x4001_4FFF Reserved 0x4001_5000 0x4001_5FFF Dual-Timer 0x4001_6000 0x4001_FFFF Reserved 0x4002_0000 0x4002_0FFF Multi-function timer unit0 0x4002_1000 0x4002_3FFF Reserved 0x4002_4000 0x4002_4FFF PPG 0x4002_5000 0x4002_5FFF Base Timer 0x4002_6000 0x4002_6FFF Quadrature Position/Revolution Counter (QPRC) APB1 0x4002_7000 0x4002_7FFF A/D Converter 0x4002_8000 0x4002_8FFF D/A Converter 0x4002_9000 0x4002_DFFF Reserved 0x4002_000 0x4002_FFF Built-in CR trimming 0x4002_F000 0x4002_FFFF Reserved 0x4003_0000 0x4003_0FFF xternal Interrupt 0x4003_1000 0x4003_1FFF Interrupt Source Check Resister 0x4003_2000 0x4003_2FFF Reserved 0x4003_3000 0x4003_3FFF GPIO 0x4003_4000 0x4003_4FFF HDMI-CC/Remote control Reception 0x4003_5000 0x4003_57FF Low-Voltage Detector 0x4003_5800 0x4003_5FFF Deep standby mode Controller 0x4003_6000 0x4003_6FFF APB2 Reserved 0x4003_7000 0x4003_7FFF CAN prescaler 0x4003_8000 0x4003_8FFF Multi-function serial Interface 0x4003_9000 0x4003_9FFF CRC 0x4003_A000 0x4003_AFFF Watch Counter 0x4003_B000 0x4003_BFFF Real-time clock 0x4003_C000 0x4003_FFF Reserved 0x4003_F000 0x4003_FFFF xternal bus interface 0x4004_0000 0x4005_FFFF Reserved 0x4006_0000 0x4006_0FFF DMAC register 0x4006_1000 0x4006_1FFF AHB Reserved 0x4006_2000 0x4006_2FFF CAN ch.0 0x4006_3000 0x41FF_FFFF Reserved 69 DS v01-

72 PIN STATUS IN ACH CPU STAT The terms used for pin status have the following meanings. INITX=0 This is the period when the INITX pin is the "L" level. INITX=1 This is the period when the INITX pin is the "H" level. SPL=0 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to "0". SPL=1 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to "1". Indicates that the input function can be used. This is the status that the input function cannot be used. input is fixed at "L". Hi-Z Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z. Setting disabled Indicates that the setting is disabled. s the that was immediately prior to entering the current mode. If a built-in peripheral function is operating, the output follows the peripheral function. If the pin is being used as a port, that output is maintained. Analog input is Indicates that the analog input is. Trace output Indicates that the trace function can be used. GPIO In Deep standby mode, pins switch to the general-purpose I/O port. DS v01-70

73 List of Pin Status Pin status type A B Function group GPIO Main crystal oscillator input pin/ xternal main clock input GPIO xternal main clock input Main crystal oscillator output pin Power-on reset or low-voltage detection Power supply unstable INITX input Device internal reset Power supply stable Run mode or SLP mode Power supply stable Timer mode, RTC mode, or STOP mode Power supply stable Deep standby RTC mode or Deep standby STOP mode Power supply stable Return from Deep standby mode Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = SPL = 0 SPL = 1 SPL = 0 SPL = 1 - Setting disabled Setting disabled Setting disabled input fixed at "0"/ or enable Setting disabled Setting disabled Setting disabled Setting disabled Setting disabled Setting disabled /When oscillation stops* 1, /When oscillation stops* 1, /When oscillation stops* 1, GPIO GPIO /When oscillation stops* 1, /When oscillation stops* 1, GPIO GPIO /When oscillation stops* 1, C INITX input pin Pull-up / Pull-up / Pull-up / Pull-up / Pull-up / Pull-up / Pull-up / Pull-up / Pull-up / D Mode input pin Mode input pin GPIO Setting disabled Setting disabled Setting disabled GPIO GPIO 71 DS v01-

74 Pin status type F G H I Function group GPIO Sub crystal oscillator input pin / xternal sub clock input GPIO xternal sub clock input Sub crystal oscillator output pin NMIX GPIO JTAG GPIO Power-on reset or low-voltage detection Power supply unstable INITX input Device internal reset Power supply stable Run mode or SLP mode Power supply stable Timer mode, RTC mode, or STOP mode Power supply stable Deep standby RTC mode or Deep standby STOP mode Power supply stable Return from Deep standby mode Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = SPL = 0 SPL = 1 SPL = 0 SPL = 1 - Setting disabled Setting disabled Setting disabled input fixed at "0"/ or enable Setting disabled Hi-Z Hi-Z Setting disabled Setting disabled Setting disabled Setting disabled Setting disabled Pull-up / Setting disabled Setting disabled Setting disabled Setting disabled Setting disabled Pull-up / Setting disabled /When oscillation stops* 2, /When oscillation stops* 2, GPIO GPIO /When oscillation stops* 2, Hi-Z/ WKUP input GPIO Hi-Z/ /When oscillation stops* 2, Hi-Z/ WKUP input GPIO GPIO /When oscillation stops* 2, Hi-Z/ GPIO GPIO DS v01-72

75 Pin status type J K L Function group Resource GPIO xternal interrupt Resource other than above GPIO Analog input Resource other than above GPIO Power-on reset or low-voltage detection Power supply unstable INITX input Device internal reset Power supply stable Run mode or SLP mode Power supply stable Timer mode, RTC mode, or STOP mode Power supply stable Deep standby RTC mode or Deep standby STOP mode Power supply stable Return from Deep standby mode Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = SPL = 0 SPL = 1 SPL = 0 SPL = 1 - Hi-Z Setting disabled Hi-Z Hi-Z Setting disabled Setting disabled / Analog input Setting disabled Setting disabled / Analog input Setting disabled / Analog input / Analog input / Analog input GPIO GPIO / Analog input GPIO / Analog input GPIO GPIO / Analog input GPIO Analog input Hi-Z / Analog input / Analog input / Analog input / Analog input / Analog input / Analog input / Analog input / Analog input M xternal interrupt Resource other than above GPIO Setting disabled Setting disabled Setting disabled GPIO GPIO 73 DS v01-

76 Pin status type Function group Power-on reset or low-voltage detection Power supply unstable INITX input Device internal reset Power supply stable Run mode or SLP mode Power supply stable Timer mode, RTC mode, or STOP mode Power supply stable Deep standby RTC mode or Deep standby STOP mode Power supply stable Return from Deep standby mode Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = SPL = 0 SPL = 1 SPL = 0 SPL = 1 - Analog input Hi-Z / Analog input / Analog input / Analog input / Analog input / Analog input / Analog input / Analog input / Analog input N WKUP WKUP input WKUP input xternal interrupt Resource other than above GPIO Setting disabled Setting disabled Setting disabled GPIO GPIO O Analog output Resource other than above GPIO Setting disabled Hi-Z Setting disabled Setting disabled *3 *4 GPIO GPIO P Trace Resource other than above GPIO Setting disabled Hi-Z Setting disabled Setting disabled Trace output GPIO GPIO DS v01-74

77 Pin status type Function group Power-on reset or low-voltage detection Power supply unstable INITX input Device internal reset Power supply stable Run mode or SLP mode Power supply stable Timer mode, RTC mode, or STOP mode Power supply stable Deep standby RTC mode or Deep standby STOP mode Power supply stable Return from Deep standby mode Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = SPL = 0 SPL = 1 SPL = 0 SPL = 1 - Q Trace xternal interrupt Resource other than above GPIO CC Setting disabled Hi-Z Setting disabled Setting disabled Setting disabled Setting disabled Setting disabled Trace output GPIO GPIO R Resource other than above GPIO Hi-Z GPIO GPIO S CC xternal interrupt Resource other than above GPIO Setting disabled Hi-Z Setting disabled Setting disabled GPIO GPIO CC T WKUP xternal interrupt Resource other than above GPIO Setting disabled Hi-Z Setting disabled Setting disabled WKUP input GPIO WKUP input GPIO 75 DS v01-

78 Pin status type U Function group WKUP xternal interrupt Resource other than above GPIO Power-on reset or low-voltage detection Power supply unstable INITX input Device internal reset Power supply stable Run mode or SLP mode Power supply stable Timer mode, RTC mode, or STOP mode Power supply stable Deep standby RTC mode or Deep standby STOP mode Power supply stable Return from Deep standby mode Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = SPL = 0 SPL = 1 SPL = 0 SPL = 1 - Setting disabled Hi-Z Setting disabled Setting disabled WKUP input GPIO WKUP input GPIO GPIO GPIO GPIO V Hi-Z *1 : Oscillation is stopped at Sub timer mode, sub CR timer mode, RTC mode, STOP mode, Deep standby RTC mode, and Deep standby STOP mode. *2 : Oscillation is stopped at STOP mode and Deep standby STOP mode. *3 : at timer mode. GPIO at RTC mode, STOP mode. *4 : at timer mode. Hi-Z/ at RTC mode, STOP mode. DS v01-76

79 LCTRICAL CHARACTRISTICS 1. Absolute Maximum Ratings Parameter Symbol Rating Min Max Unit Remarks Power supply voltage* 1, * 2 V CC V SS V SS V Analog power supply voltage* 1, * 3 AV CC V SS V SS V Analog reference voltage* 1, * 3 AVRH V SS V SS V voltage* 1 V V V SS CC I ( 6.5V) V V SS V SS V 5V tolerant Analog pin input voltage* 1 V IA V SS AV CC ( 6.5V) V Output voltage* 1 V O V SS V CC ( 6.5V) V 10 ma 4mA type "L" level maximum output current* 4 I OL - 20 ma 12mA type 39 ma P80/P81 4 ma 4mA type "L" level average output current* 5 I OLAV - 12 ma 12mA type 16.5 ma P80/P81 "L" level total maximum output current I OL ma "L" level total average output current* 6 I OLAV - 50 ma - 10 ma 4mA type "H" level maximum output current* 4 I OH ma 12mA type - 39 ma P80/P81-4 ma 4mA type "H" level average output current* 5 I OHAV ma 12mA type - 18 ma P80/P81 "H" level total maximum output current I OH ma "H" level total average output current* 6 I OHAV ma Power consumption P D mw Storage temperature T STG C *1 : These parameters are based on the condition that V SS = AV SS = 0V. *2 : V CC must not drop below V SS - 0.5V. *3 : nsure that the voltage does not exceed V CC V, for example, when the power is turned on. *4 : The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *5 : The average output current is defined as the average current value flowing through any one of the corresponding pins for a 100 ms period. *6 : The total average output current is defined as the average current value flowing through all of corresponding pins for a 100ms. <WARNING> Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings. 77 DS v01-

80 2. Recommended Operating Conditions (V SS = AV SS = 0.0V) Parameter Symbol Conditions Value Min Max Unit Remarks Power supply voltage V CC V Analog power supply voltage AV CC V AV CC = V CC Analog reference voltage AVRH AV CC V AVRL - AV SS AV SS V Smoothing capacitor C S μf For Regulator* Operating temperature Ta C * : See " C Pin" in " HANDLING DVICS" for the connection of the smoothing capacitor. <WARNING> The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. Any use of semiconductor devices will be under their recommended operating condition. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. DS v01-78

81 3. DC Characteristics (1) Current Rating (targeted value) Pin Parameter Symbol Conditions name Power supply current I CC I CCS VCC *1: Ta=+25,V CC = 3.3V *2: Ta=+105,V CC =5.5V *3: When all ports are fixed. *4: When setting it to 4MHz by trimming. Normal operation (PLL) Normal operation (built-in high-speed CR) Normal operation (sub oscillation) Normal operation (built-in low-speed CR) SLP operation (PLL) SLP operation (built-in high-speed CR) SLP operation (sub oscillation) SLP operation (built-in low-speed CR) Value Typ* 1 Max* 2 Unit 29 TBD ma 19 TBD ma 3.1 TBD ma 415 TBD µa 440 TBD µa 19 TBD ma 2.1 TBD ma 395 TBD µa 420 TBD µa Remarks CPU : 60MHz, Peripheral : 30MHz *3 CPU:60MHz, Peripheral clock stops *3 CPU/ Peripheral : 4MHz* 4 *3 CPU/ Peripheral : 32kHz *3 CPU/ Peripheral : 100kHz *3 Peripheral : 30MHz *3 Peripheral : 4MHz* 4 *3 Peripheral : 32kHz *3 Peripheral : 100kHz *3 79 DS v01-

82 Parameter Symbol Power supply current I CCH I CCT I CCR I CCHD I CCRD Pin name VCC Conditions STOP mode TIMR mode (sub oscillation) RTC mode (sub oscillation) Deep Standby STOP mode Deep Standby RTC mode (sub oscillation) Value Typ* 1 Max* 2 Unit 20 TBD μa - TBD μa 24 TBD μa - TBD μa 21 TBD μa - TBD μa 1.9 TBD μa 4.8 TBD μa 5.5 TBD μa - TBD TBD TBD μa μa μa 2.5 TBD μa 5.4 TBD μa 6.1 TBD μa - TBD TBD TBD μa μa μa Remarks Ta = + 25 C *3 Ta = C *3 Ta = + 25 C *3 Ta = C *3 Ta = + 25 C *3 Ta = C *3 Ta = + 25 C, When RAM is off *3 Ta = + 25 C, When RAM is on(16kb)* 4 *3 Ta = + 25 C, When RAM is on(32kb) * 4 *3 Ta = C, When RAM is off *3 Ta = C, When RAM is on(16kb) * 4 *3 Ta = C, When RAM is on(32kb) * 4 *3 Ta = + 25 C, When RAM is off *3 Ta = + 25 C, When RAM is on(16kb) * 4 *3 Ta = + 25 C, When RAM is on(32kb) * 4 *3 Ta = C, When RAM is off *3 Ta = C, When RAM is on(16kb) * 4 *3 Ta = C, When RAM is on(32kb) * 4 *3 *1: V CC =3.3V *2: V CC =5.5V *3: When all ports are fixed and LVD off. *4: For more information about RAM retention area, see " Memory Map (2)" in " MMORY MAP". DS v01-80

83 Low-Voltage Detection Current Parameter Symbol Pin name Conditions (V CC = 2.7V to 5.5V, V SS = 0V, Ta = - 40 C to C) Value Unit Remarks Min Typ Max Low-Voltage detection circuit (LVD) power supply current I CCLVD VCC At operation μa μa For occurrence of reset For occurrence of interrupt Flash Memory Current Parameter Flash memory write/erase current Symbol I CCFLASH Pin name VCC (V CC = 2.7V to 5.5V, V SS = 0V, Ta = - 40 C to C) Value Conditions Unit Remarks Min Typ Max At ROM0 Write/rase At ROM1 Write/rase TBD ma *1-9.5 TBD ma *1 *1: When programming or erase in flash memory, Flash Memory Write/rase current (ICCFLASH) is added to the Power supply current (I CC ). In addition, When programming or erase in flash memory ROM0 and ROM1 at the same time, Flash Memory Write/rase current (ICCFLASH) of both ROM0 and ROM1 are added to the Power supply current (I CC ). A/D Converter Current (V CC = AV CC = 2.7V to 5.5V, V SS = AV SS = AVRL = 0V, Ta = - 40 C to C) Pin Value Parameter Symbol Conditions Unit Remarks name Min Typ Max At 1unit TBD ma Power supply operation I current CCAD AVCC At stop TBD μa Reference power supply current (AVRH) I CCAVRH AVRH At 1unit operation AVRH=5.5V TBD ma At stop TBD μa D/A Converter Current Parameter Power supply current* 1 Symbol 2 IDDA* Pin name AVCC (V CC = AV CC = 2.7V to 5.5V, V SS = AV SS = 0V, Ta = - 40 C to C) Value Conditions Unit Remarks Min Typ Max At operation TBD μa AV CC =3.3V At operation AV CC =5.0V TBD μa IDSA At stop - - TBD μa *1: No-load *2: Generates the max current by the COD about 0x DS v01-

84 (2) Pin Characteristics (V CC = AV CC = 2.7V to 5.5V, V SS = AV SS = AVRL = 0V, Ta = - 40 C to C) Value Parameter Symbol Pin name Conditions Unit Remarks Min Typ Max CMOS "H" level hysteresis input - V input pin, CC V CC V voltage V IHS MD0, MD1 (hysteresis 5V tolerant input) - V input pin CC V SS V "L" level input voltage (hysteresis input) "H" level output voltage "L" level output voltage leak current Pull-up resistance value capacitance V ILS V OH V OL CMOS hysteresis input pin, MD0, MD1 5V tolerant input pin 4mA type 12mA type P80/P81 4mA type 12mA type P80/P81 - V SS V CC 0.2 V - V SS V CC 0.2 V V CC 4.5 V, I OH = - 4mA V CC < 4.5 V, I OH = - 2mA V CC 4.5 V, I OH = - 12mA V CC < 4.5 V, I OH = - 8mA V CC 4.5 V, I OH = ma V CC < 4.5 V, I OH = ma V CC 4.5 V, I OL = 4mA V CC < 4.5 V, I OL = 2mA V CC 4.5 V, I OL = 12mA V CC < 4.5 V, I OL = 8mA V CC 4.5 V, I OL = 16.5mA V CC < 4.5 V, I OL = 10.5mA V CC V CC V V CC V CC V V CC V CC V V SS V V SS V V SS V I IL μa R PU C IN Pull-up pin Other than VCC, VSS, AVCC, AVSS, AVRH, AVRL V CC 4.5 V V CC < 4.5 V kω pf DS v01-82

85 4. AC Characteristics (1) Main Clock Characteristics (V CC = 2.7V to 5.5V, V SS = 0V, Ta = - 40 C to C) Pin Parameter Symbol name Conditions Value Unit Remarks Min Max V CC 4.5V 4 48 When crystal oscillator MHz V frequency F CC < 4.5V 4 20 is connected CH When using external MHz clock When using external clock cycle t CYLH X0, ns clock X1 clock pulse PWH/tCYLH, When using external % width PWL/tCYLH clock clock rising t time and falling CF, When using external ns t time CR clock F CM MHz Master clock operating clock* 1 frequency operating clock* 1 cycle time F CC MHz Base clock (HCLK/FCLK) F CP MHz APB0 bus clock* 2 F CP MHz APB1 bus clock* 2 F CP MHz APB2 bus clock* 2 t CYCC ns Base clock (HCLK/FCLK) t CYCP ns APB0 bus clock* 2 t CYCP ns APB1 bus clock* 2 t CYCP ns APB2 bus clock* 2 *1: For more information about each internal operating clock, see "Chapter:Clock" in "FM3 Family PRIPHRAL MANUAL". *2: For about each APB bus which each peripheral is connected to, see " BLOCK DIAGRAM" in this data sheet. X0 83 DS v01-

86 (2) Sub Clock Characteristics (V CC = 2.7V to 5.5V, V SS = 0V, Ta = - 40 C to C) Parameter Pin Symbol name Conditions Value Min Typ Max Unit Remarks When crystal khz oscillator is frequency 1/ t CYLL connected* When using X0A, khz external clock X1A When using clock cycle t CYLL μs external clock clock pulse PWH/tCYLL, When using % width PWL/tCYLL external clock *: For more information about crystal oscillator, see " Sub crystal oscillator" in " HANDLING DVICS". X0A DS v01-84

87 (3) Built-in CR Oscillation Characteristics Built-in High-speed CR (V CC = 2.7V to 5.5V, V SS = 0V, Ta = - 40 C to C) Parameter Symbol Conditions Value Min Typ Max Unit Remarks Ta = + 25 C, 3.6V < V CC 5.5V Ta = 0 C to + 85 C, 3.6V < V CC 5.5V Ta = -40 C to C, V < V CC 5.5V When trimming* 1 Ta = + 25 C, V V Clock frequency F CC 3.6V CRH MHz Ta = - 20 C to + 85 C, V V CC 3.6V Ta = - 20 C to C, 2.7V V CC 3.6V Ta = -40 C to C, 2.7V V CC 3.6V Ta = - 40 C to C When not trimming Frequency t stability time CRWT μs *2 *1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency/temperature trimming. *2: Frequency stable time is time to stable of the frequency of the High-speed CR. clock after the trim value is set. After setting the trim value, the period when the frequency stability time passes can use the High-speed CR clock as a source clock. Built-in Low-speed CR Parameter Symbol Conditions (V CC = 2.7V to 5.5V, V SS = 0V, Ta = - 40 C to C) Value Unit Remarks Min Typ Max Clock frequency F CRL khz 85 DS v01-

88 (4-1) Operating Conditions of Main PLL (In the case of using main clock for input of PLL) (V CC = 2.7V to 5.5V, V SS = 0V, Ta = - 40 C to C) Parameter Symbol Value Min Typ Max Unit Remarks PLL oscillation stabilization wait time* 1 (LOCK UP time) t LOCK μs PLL input clock frequency F PLLI 4-16 MHz PLL multiplication rate multiplier PLL macro oscillation clock frequency F PLLO MHz Main PLL clock frequency* 2 F CLKPLL MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see "Chapter: Clock" in "FM3 Family PRIPHRAL MANUAL". (4-2) Operating Conditions of Main PLL (In the case of using built-in high-speed CR for input clock of main PLL) (V CC = 2.7V to 5.5V, V SS = 0V, Ta = - 40 C to C) Parameter Symbol Value Min Typ Max Unit Remarks PLL oscillation stabilization wait time* 1 (LOCK UP time) t LOCK μs PLL input clock frequency F PLLI MHz PLL multiplication rate multiplier PLL macro oscillation clock frequency F PLLO MHz Main PLL clock frequency* 2 F CLKPLL MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see "Chapter: Clock" in "FM3 Family PRIPHRAL MANUAL". Note: Make sure to input to the main PLL source clock, the high-speed CR clock (CLKHC) that the frequency has been trimmed. DS v01-86

89 (5) Reset Characteristics Parameter Symbol Pin name (V CC = 2.7V to 5.5V, V SS = 0V, Ta = - 40 C to C) Value Conditions Unit Remarks Min Max Reset input time t INITX INITX ns (6) Power-on Reset Timing Parameter Power supply rising time Symbol Tr Pin name (V CC = 2.7V to 5.5V, V SS = 0V, Ta = - 40 C to C) Value Unit Remarks Min Max 0 - ms Power supply shut down time Toff VCC 1 - ms Time until releasing Power-on reset Tprt TBD TBD ms VCC_minimum VCC VDL_minimum 0.2V Tr 0.2V 0.2V Tprt Toff RST RST Active Release CPU Operation start Glossary VCC_minimum : Minimum V CC of recommended operating conditions LVDL_minimum : Minimum detection voltage of Low-Voltage detection reset See "6. Low-Voltage Detection Characteristics" 87 DS v01-

90 (7) xternal Bus Timing xternal bus clock output characteristics (V CC = 2.7V to 5.5V, V SS = 0V, Ta = - 40 C to C) Value Parameter Symbol Pin name Conditions Unit Min Max V Output frequency t CYCL MCLKOUT* CC 4.5V - 50 MHz V CC < 4.5V - 32 MHz *: The external bus clock (MCLKOUT) is a divided clock of HCLK. For more information about setting of clock divider, see "Chapter: xternal Bus Interface" in "FM3 Family PRIPHRAL MANUAL". MCLK 0.8 Vcc 0.8 Vcc t CYCL xternal bus signal input/output characteristics (V CC = 2.7V to 5.5V, V SS = 0V, Ta = - 40 C to C) Parameter Symbol Conditions Value Unit Remarks Signal input characteristics Signal output characteristics V IH 0.8 V CC V V IL 0.2 V CC V - V OH 0.8 V CC V V OL 0.2 V CC V signal VIH VIL VIH VIL Output signal VOH VOL VOH VOL DS v01-88

91 Separate Bus Access Asynchronous SRAM Mode (targeted value) (V CC = 2.7V to 5.5V, V SS = 0V, Ta = - 40 C to C) Parameter Symbol Pin name Conditions Value Min Max Unit MOX V t Min pulse width OW MOX CC 4.5V V CC < 4.5V MCLK n-3 - ns MCSX Address MCSX[7:0], V t CC 4.5V output delay time CSL AV MAD[24:0] V CC < 4.5V ns MOX MOX, V t CC 4.5V MCLK m+9 Address hold time OH - AX 0 MAD[24:0] V CC < 4.5V MCLK m+12 ns MCSX V t CC 4.5V MCLK m-9 MCLK m+9 MOX delay time CSL - OL MOX, V CC < 4.5V MCLK m-12 MCLK m+12 ns MOX MCSX[7:0] V t CC 4.5V MCLK m+9 MCSX time OH - CSH 0 V CC < 4.5V MCLK m+12 ns MCSX MCSX, V t CC 4.5V MCLK m-9 MCLK m+9 MDQM delay time CSL - RDQML MDQM[1:0] V CC < 4.5V MCLK m-12 MCLK m+12 ns Data set up MOX, V t CC 4.5V 20 - MOX time DS - O MADATA[15:0] V CC < 4.5V 38 - ns MOX MOX, V t CC 4.5V Data hold time DH - O MADATA[15:0] V CC < 4.5V 0 - ns MWX V t Min pulse width WW MWX CC 4.5V V CC < 4.5V MCLK n-3 - ns MWX Address MWX, V t CC 4.5V MCLK m+9 output delay time WH - AX 0 MAD[24:0] V CC < 4.5V MCLK m+12 ns MCSX V t CC 4.5V MCLK n-9 MCLK n+9 MWX delay time CSL - WL MWX, V CC < 4.5V MCLK n-12 MCLK n+12 ns MWX MCSX[7:0] V t CC 4.5V MCLK m+9 MCSX delay time WH - CSH 0 V CC < 4.5V MCLK m+12 ns MCSX MCSX, V t CC 4.5V MCLK n-9 MCLK n+9 MDQM delay time CSL-WDQML MDQM[1:0] V CC < 4.5V MCLK n-12 MCLK n+12 ns MCSX MCSX, V t CC 4.5V MCLK-9 MCLK+9 Data output time CSL-DV MADATA[15:0] V CC < 4.5V MCLK-12 MCLK+12 ns MWX MWX, V t CC 4.5V Data hold time WH - DX MADATA[15:0] V CC < 4.5V 0 MCLK m+12 ns Note: When the external load capacitance C L = 30pF (m = 0 to 15, n = 1 to 16). 89 DS v01-

92 t CYCL MCLK MCSX[7:0] t OH-CSH t WH-CSH MAD[24:0] t CSL-AV t OH-AX Address t CSL-AV Address t WH-AX t CSL-OL MOX tcsl-rdqml t OW t CSL-WDQML MDQM[1:0] t CSL-WL MWX MADATA[15:0] t DS-O RD t DH-O Invalid t WW WD t WH-DX t CSL-DV DS v01-90

93 Separate Bus Access Synchronous SRAM Mode (targeted value) (V CC = 2.7V to 5.5V, V SS = 0V, Ta = - 40 C to C) Parameter Symbol Pin name Conditions Value Min Max Unit Address delay time t AV MCLK, V CC 4.5V MAD[24:0] V CC < 4.5V 1 12 ns MCSX delay time t CSH 1 V CC < 4.5V 12 ns t CSL V CC 4.5V 9 1 MCLK, V CC < 4.5V 12 ns MCSX[7:0] V CC 4.5V 9 MOX delay time t RL V CC 4.5V 9 1 MCLK, V CC < 4.5V 12 ns t RH MOX V CC 4.5V 9 1 V CC < 4.5V 12 ns Data set up MCLK, V t CC 4.5V 19 MCLK time DS MADATA[15:0] V CC < 4.5V 37 - ns MCLK MCLK, V CC 4.5V Data hold time t DH MADATA[15:0] V CC < 4.5V 0 - ns MWX delay time t WL V CC 4.5V 9 1 MCLK, V CC < 4.5V 12 ns t WH MWX V CC 4.5V 9 1 V CC < 4.5V 12 ns V t CC 4.5V 9 MDQM[1:0] DQML 1 MCLK, V CC < 4.5V 12 ns delay time MDQM[1:0] V t CC 4.5V 9 DQMH 1 V CC < 4.5V 12 ns MCLK MCLK, V t CC 4.5V MCLK+18 Data output time ODS MCLK+1 MADATA[15:0] V CC < 4.5V MCLK+24 ns MCLK MCLK, V t CC 4.5V 18 Data hold time OD 1 MADATA[15:0] V CC < 4.5V 24 ns Note: When the external load capacitance C L = 30pF. t CYCL MCLK MCSX[7:0] t CSL t CSH MAD[24:0] t AV Address t AV Address MOX t RL t RH MDQM[1:0] t DQML tdqmh t DQML t DQMH MWX MADATA[15:0] t DS RD t DH Invalid t WL WD t WH t OD t ODS 91 DS v01-

94 Multiplexed Bus Access Asynchronous SRAM Mode (targeted value) (V CC = 2.7V to 5.5V, V SS = 0V, Ta = - 40 C to C) Parameter Symbol Pin name Conditions Value Min Max Unit Multiplexed V t CC 4.5V +10 address delay time AL-CHMADV 0 MAL, V CC < 4.5V +20 ns Multiplexed MADATA[15:0] V t CC 4.5V MCLK n+0 MCLK n+12 address hold time CHMADH V CC < 4.5V MCLK n+0 MCLK n+20 ns Note: When the external load capacitance C L = 30pF (m = 0 to 15, n = 1 to 16). MCLK MCSX[7:0] MAL MAD [24:0] MOX MDQM [1:0] MWX MADATA[15:0] DS v01-92

95 Multiplexed Bus Access Synchronous SRAM Mode (targeted value) (V CC = 2.7V to 5.5V, V SS = 0V, Ta = - 40 C to C) Parameter Symbol Pin name Conditions Value Min Max Unit Remarks MAL delay time t CHAL V CC 4.5V 9 ns 1 MCLK, V CC < 4.5V 12 ns t CHAH AL V CC 4.5V 9 ns 1 V CC < 4.5V 12 ns MCLK V CC 4.5V Multiplexed t CHMADV Address delay time MCLK, V CC < 4.5V 1 t OD ns MCLK MADATA[15:0] V CC 4.5V Multiplexed t CHMADX Data output time V CC < 4.5V 1 t OD ns Note: When the external load capacitance C L = 30pF. MCLK MCSX[7:0] MAL MAD [24:0] MOX MDQM [1:0] MWX MADATA[15:0] 93 DS v01-

96 NAND Flash Memory Mode (targeted value) (V CC = 2.7V to 5.5V, V SS = 0V, Ta = - 40 C to C) Parameter Symbol Pin name Conditions Value Min Max Unit MNRX V t Min pulse width NRW MNRX CC 4.5V V CC < 4.5V MCLK n-3 - ns Data setup MNRX, V t CC 4.5V 20 - MNRX time DS NR MADATA[15:0] V CC < 4.5V 38 - ns MNRX MNRX, V t CC 4.5V Data hold time DH NR MADATA[15:0] V CC < 4.5V 0 - ns MNAL MNAL, V t CC 4.5V MCLK m-9 MCLK m+9 MNWX delay time ALH - NWL MNWX V CC < 4.5V MCLK m-12 MCLK m+12 ns MNAL MNAL, V t CC 4.5V MCLK m-9 MCLK m+9 MNWX delay time ALL - NWL MNWX V CC < 4.5V MCLK m-12 MCLK m+12 ns MNCL MNCL, V t CC 4.5V MCLK m-9 MCLK m+9 MNWX delay time CLH - NWL MNWX V CC < 4.5V MCLK m-12 MCLK m+12 ns MNWX MNCL, V t CC 4.5V MCLK m+9 MNCL delay time NWH - CLL 0 MNWX V CC < 4.5V MCLK m+12 ns MNWX V t Min pulse width NWW MNWX CC 4.5V V CC < 4.5V MCLK n-3 - ns MNWX MNWX, V t CC 4.5V Data output time NWL DV MADATA[15:0] V CC < 4.5V ns MNWX MNWX, V t CC 4.5V MCLK m+11 Data hold time NWH DX 0 MADATA[15:0] V CC < 4.5V MCLK m+12 ns Note: When the external load capacitance C L = 30pF (m=0 to 15, n=1 to 16). DS v01-94

97 NAND Flash Memory Read MCLK MNRX MADATA[15:0] Read NAND Flash Memory Address Write MCLK MNAL MNCL MNWX MADATA[15:0] Write 95 DS v01-

98 NAND Flash Memory Command Write MCLK MNAL MNCL MNWX MADATA[15:0] Write DS v01-96

99 xternal Ready Timing (targeted value) (V CC = 2.7V to 5.5V, V SS = 0V, Ta = - 40 C to C) Value Parameter Symbol Pin name Conditions Unit Remarks Min Max MCLK MRDY input setup time When RDY is input t RDYI MCLK, MRDY V CC 4.5V 19 V CC < 4.5V 37 - ns MCLK Original MOX MWX Over 2cycles t RDYI MRDY When RDY is released MCLK 2 cycles xtended MOX MWX t RDYI MRDY 0.5 V CC 97 DS v01-

100 (8) Base Timer Timing Timer input timing (V CC = 2.7V to 5.5V, V SS = 0V, Ta = - 40 C to C) Value Parameter Symbol Pin name Conditions Unit Remarks Min Max TIOAn/TIOBn t pulse width TIWH, (when using as - 2t t CYCP - ns TIWL CK, TIN) CK t TIWH t TIWL TIN V IHS V IHS V ILS V ILS Trigger input timing (V CC = 2.7V to 5.5V, V SS = 0V, Ta = - 40 C to C) Value Parameter Symbol Pin name Conditions Unit Remarks Min Max TIOAn/TIOBn t pulse width TRGH, (when using as - 2t t CYCP - ns TRGL TGIN) t TRGH t TRGL TGIN V IHS V IHS V ILS V ILS Note: t CYCP indicates the APB bus clock cycle time. About the APB bus number which the Base Timer is connected to, see " BLOCK DIAGRAM" in this data sheet. DS v01-98

101 (9) CSIO Timing (targeted value) Synchronous serial (SPI = 0, SCINV = 0) (V CC = 2.7V to 5.5V, V SS = 0V, Ta = - 40 C to C) Parameter Pin Symbol name Conditions V CC < 4.5V V CC 4.5V Min Max Min Max Unit Serial clock cycle time t SCYC SCKx 4t CYCP - 4t CYCP - ns SCK SOT delay time t SLOVI SCKx, SOTx shift ns SIN SCK setup time t IVSHI SCKx, clock SINx operation ns SCK SIN hold time t SHIXI SCKx, SINx ns Serial clock "L" pulse width t SLSH SCKx 2t CYCP - 2t - CYCP ns Serial clock "H" pulse width t SHSL SCKx t CYCP + t - CYCP ns SCKx, SCK SOT delay time t SLOV xternal shift ns SOTx clock SCKx, SIN SCK setup time t IVSH operation ns SINx SCK SIN hold time t SHIX SCKx, SINx ns SCK falling time tf SCKx ns SCK rising time tr SCKx ns Notes: The above characteristics apply to CLK synchronous mode. t CYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function Serial is connected to, see " BLOCK DIAGRAM" in this data sheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed. When the external load capacitance CL = 30pF. 99 DS v01-

102 tscyc SCK VOH VOL VOL SOT t SLOVI VOH VOL SIN VIH VIL tivshi tshixi VIH VIL MS bit = 0 tslsh tshsl SCK VIH tf VIL t SLOV VIL VIH tr VIH SOT VOH VOL SIN tivsh VIH VIL MS bit = 1 tshix VIH VIL DS v01-100

103 Synchronous serial (SPI = 0, SCINV = 1) (V CC = 2.7V to 5.5V, V SS = 0V, Ta = - 40 C to C) Parameter Pin Symbol name Conditions V CC < 4.5V V CC 4.5V Min Max Min Max Unit Serial clock cycle time t SCYC SCKx 4t CYCP - 4t CYCP - ns SCK SOT delay time t SHOVI SCKx, SOTx shift ns SIN SCK setup time t IVSLI SCKx, clock SINx operation ns SCK SIN hold time t SLIXI SCKx, SINx ns Serial clock "L" pulse width t SLSH SCKx 2t CYCP - 2t - CYCP ns Serial clock "H" pulse width t SHSL SCKx t CYCP + t - CYCP ns SCKx, SCK SOT delay time t SHOV xternal shift ns SOTx clock SCKx, SIN SCK setup time t IVSL operation ns SINx SCK SIN hold time t SLIX SCKx, SINx ns SCK falling time tf SCKx ns SCK rising time tr SCKx ns Notes: The above characteristics apply to CLK synchronous mode. t CYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function Serial is connected to, see " BLOCK DIAGRAM" in this data sheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed. When the external load capacitance CL = 30pF. 101 DS v01-

104 tscyc SCK VOH VOH VOL SOT t SHOVI VOH VOL SIN VIH VIL tivsli tslixi VIH VIL MS bit = 0 tshsl tslsh SCK tr VIL VIH t SHOV tf VIH VIL VIL SOT VOH VOL tivsl tslix SIN VIH VIH VIL VIL MS bit = 1 DS v01-102

105 Synchronous serial (SPI = 1, SCINV = 0) (V CC = 2.7V to 5.5V, V SS = 0V, Ta = - 40 C to C) Parameter Pin Symbol name Conditions V CC < 4.5V V CC 4.5V Min Max Min Max Unit Serial clock cycle time t SCYC SCKx 4t CYCP - 4t CYCP - ns SCK SOT delay time t SHOVI SCKx, SOTx ns SIN SCK setup time t IVSLI SCKx, shift SINx clock ns SCK SIN hold time t SLIXI SCKx, operation SINx ns SOT SCK delay time t SOVLI SCKx, 2t CYCP - 2t - CYCP - SOTx ns Serial clock "L" pulse width t SLSH SCKx 2t CYCP - 2t - CYCP ns Serial clock "H" pulse width t SHSL SCKx t CYCP + t - CYCP ns SCKx, SCK SOT delay time t SHOV xternal shift ns SOTx clock SCKx, SIN SCK setup time t IVSL operation ns SINx SCK SIN hold time t SLIX SCKx, SINx ns SCK falling time tf SCKx ns SCK rising time tr SCKx ns Notes: The above characteristics apply to CLK synchronous mode. t CYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function Serial is connected to, see " BLOCK DIAGRAM" in this data sheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed. When the external load capacitance CL = 30pF. 103 DS v01-

106 tscyc SCK tsovli VOL VOH tshovi VOL SOT VOH VOL VOH VOL tivsli tslixi SIN VIH VIL VIH VIL MS bit = 0 tslsh tshsl SCK VIH VIH VIH VIL VIL SOT * VOH VOL tf tr tshov VOH VOL tivsl tslix SIN VIH VIL VIH VIL *: Changes when writing to TDR register MS bit = 1 DS v01-104

107 Synchronous serial (SPI = 1, SCINV = 1) (V CC = 2.7V to 5.5V, V SS = 0V, Ta = - 40 C to C) Pin Parameter Symbol name Conditions V CC < 4.5V V CC 4.5V Unit Min Max Min Max Serial clock cycle time t SCYC SCKx 4t CYCP - 4t CYCP - ns SCK SOT delay time SIN SCK setup time SCK SIN hold time SOT SCK delay time t SLOVI t IVSHI t SHIXI t SOVHI SCKx, SOTx SCKx, SINx SCKx, SINx SCKx, SOTx Serial clock "L" pulse width t SLSH SCKx Serial clock "H" pulse width t SHSL SCKx shift clock operation ns ns ns 2t CYCP t CYCP - 10 t CYCP t CYCP t CYCP - 10 t CYCP ns - ns - ns SCKx, SCK SOT delay time t SLOV xternal shift ns SOTx clock SCKx, SIN SCK setup time t IVSH operation ns SINx SCK SIN hold time t SHIX SCKx, SINx ns SCK falling time tf SCKx ns SCK rising time tr SCKx ns Notes: The above characteristics apply to CLK synchronous mode. t CYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function Serial is connected to, see " BLOCK DIAGRAM" in this data sheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed. When the external load capacitance C L = 30pF. 105 DS v01-

108 tscyc SCK VOH VOL VOH tsovhi tslovi SOT VOH VOL VOH VOL tivshi tshixi SIN VIH VIL VIH VIL MS bit = 0 SCK tr tshsl tslsh tf VIL VIH VIH VIL VIL VIH SOT VOH VOL tslov VOH VOL tivsh tshix SIN VIH VIL VIH VIL MS bit = 1 xternal clock (XT = 1) : asynchronous only (V CC = 2.7V to 5.5V, V SS = 0V, Ta = - 40 C to C) Value Parameter Symbol Conditions Unit Remarks Min Max Serial clock "L" pulse width t SLSH t CYCP ns Serial clock "H" pulse width t SHSL t C L = 30pF CYCP ns SCK falling time tf - 5 ns SCK rising time tr - 5 ns SCK tr tshsl tslsh V IH V IH V IH V IL V IL V IL tf DS v01-106

109 (10) xternal Timing (V CC = 2.7V to 5.5V, V SS = 0V, Ta = - 40 C to C) Parameter Symbol Pin name Conditions Value Unit Min Max Remarks ADTG A/D converter trigger input FRCKx - 2t CYCP * 1 - ns Free-run timer input clock pulse width t INH, ICxx capture t INL DTTIxX - 2t CYCP * 1 - ns Waveform generator INT00 to INT23, 2t - CYCP + 100* 1 - ns xternal interrupt, NMIX 500* 2 - ns NMI WKUPx - 500* 3 - ns Deep standby wake up *1 : t CYCP indicates the APB bus clock cycle time except stop when in stop mode, in timer mode. About the APB bus number which the A/D converter, Multi-function Timer, xternal interrupt are connected to, see " BLOCK DIAGRAM" in this data sheet. *2 : When in stop mode, in timer mode. *3 : When in Deep standby RTC mode, in Deep standby STOP mode. 107 DS v01-

110 (11) Quadrature Position/Revolution Counter timing (V CC = 2.7V to 5.5V, V SS = 0V, Ta = - 40 C to C) Parameter Symbol Conditions Value Min Max Unit AIN pin "H" width t AHL - AIN pin "L" width t ALL - BIN pin "H" width t BHL - BIN pin "L" width t BLL - Time from AIN pin "H" PC_Mode2 or t level to BIN rise AUBU PC_Mode3 Time from BIN pin "H" PC_Mode2 or t level to AIN fall BUAD PC_Mode3 Time from AIN pin "L" PC_Mode2 or t level to BIN fall ADBD PC_Mode3 Time from BIN pin "L" PC_Mode2 or t level to AIN rise BDAU PC_Mode3 Time from BIN pin "H" PC_Mode2 or t level to AIN rise BUAU PC_Mode3 Time from AIN pin "H" PC_Mode2 or t level to BIN fall AUBD PC_Mode3 Time from BIN pin "L" PC_Mode2 or t level to AIN fall BDAD PC_Mode3 Time from AIN pin "L" PC_Mode2 or t level to BIN rise ADBU PC_Mode3 2t CYCP * - ns ZIN pin "H" width t ZHL QCR:CGSC="0" ZIN pin "L" width t ZLL QCR:CGSC="0" Time from determined ZIN level to AIN/BIN rise and t ZAB QCR:CGSC="1" fall Time from AIN/BIN rise and fall time to determined ZIN level t ABZ QCR:CGSC="1" *: t CYCP indicates the APB bus clock cycle time except stop when in stop mode, in timer mode. About the APB bus number which the Quadrature Position/Revolution Counter is connected to, see " BLOCK DIAGRAM" in this data sheet. tahl tall AIN taubu tbuad tadbd tbdau BIN tbhl tbll DS v01-108

111 tbhl tbll BIN tbuau taubd tbdad tadbu AIN tahl tall ZIN ZIN AIN/BIN 109 DS v01-

112 (12) I 2 C Timing (V CC = 2.7V to 5.5V, V SS = 0V, Ta = - 40 C to C) Parameter Symbol Conditions Standard-mode Fast-mode Unit Remarks Min Max Min Max SCL clock frequency F SCL khz (Repeated) START condition hold time t HDSTA μs SDA SCL SCLclock "L" width t LOW μs SCLclock "H" width t HIGH μs (Repeated) START condition setup time t SUSTA μs SCL SDA Data hold time SCL SDA t HDDAT C L = 30pF, R = (Vp/I OL )* * * 3 μs Data setup time SDA SCL t SUDAT ns STOP condition setup time SCL SDA t SUSTO μs Bus free time between "STOP condition" and "START condition" t BUF μs 8MHz 2 t t CYCP 40MHz CYCP * t CYCP * 4 - ns *5 Noise filter t SP 40MHz < 3 t t CYCP 60MHz CYCP * t CYCP * 4 - ns *5 60MHz < 4 t t CYCP 72MHz CYCP * t CYCP * 4 - ns *5 *1 :R and C L represent the pull-up resistor and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up resistor and I OL indicates V OL guaranteed current. *2 :The maximum t HDDAT must satisfy that it does not extend at least "L" period (t LOW ) of device's SCL signal. *3 :A high-speed mode I 2 C bus device can be used on a standard mode I 2 C bus system as long as the device satisfies the requirement of "t SUDAT 250 ns". *4 :t CYCP is the APB bus clock cycle time. About the APB bus number that I 2 C is connected to, see " BLOCK DIAGRAM" in this data sheet. To use Standard-mode, set the APB bus clock at 2 MHz or more. To use Fast-mode, set the APB bus clock at 8 MHz or more. *5 :The number of the steps of the noise filter can be changed to 2, 3 and 4 steps by register settings. Change the number of the noise filter steps according to APB2 bus clock frequency. SDA SCL DS v01-110

113 (13) TM Timing (targeted value) (V CC = 2.7V to 5.5V, V SS = 0V, Ta = - 40 C to C) Value Parameter Symbol Pin name Conditions Unit Remarks Min Max TRACCLK, V CC 4.5V 2 10 Data hold t TMH ns TRACD[3:0] V CC < 4.5V 2 15 TRACCLK frequency TRACCLK clock cycle 1/ t TRAC t TRAC TRACCLK Note: When the external load capacitance C L = 30pF. V CC 4.5V - 40 MHz V CC < 4.5V - 20 MHz V CC 4.5V 25 - ns V CC < 4.5V 50 - ns HCLK TRACCLK TRACD[3:0] 111 DS v01-

114 (14) JTAG Timing (targeted value) (V CC = 2.7V to 5.5V, V SS = 0V, Ta = - 40 C to C) Value Parameter Symbol Pin name Conditions Unit Remarks Min Max TMS, TDI setup TCK, V CC 4.5V t time JTAGS 15 - ns TMS, TDI V CC < 4.5V TCK, V TMS, TDI hold time t CC 4.5V JTAGH 15 - ns TMS, TDI V CC < 4.5V TCK, V CC 4.5V - 25 TDO delay time t JTAGD ns TDO V CC < 4.5V - 45 Note: When the external load capacitance C L = 30pF. TCK TMS/TDI TDO DS v01-112