FPGA Entering the Era of the All Programmable SoC

Transcription

1 FPGA Entering the Era of the All Programmable SoC Ivo Bolsens, Senior Vice President & CTO Page 1

2 Moore s Law: The Technology Pipeline Page 2

3 Industry Debates on Cost Page 3

4 Design Cost Estimated Chip Design Cost, by Process Node, Worldwide, 2011 Design cost ($M) Mask cost ($M) 28/22-nm 32-nm Embedded software ($M) Yield ramp-up cost ($M) 45-nm 65-nm 90-nm 130-nm 28nm = 2x 45nm cost > $170 M 180-nm ($ Million) Page 4

5 Internet

6 Don t believe everything you read on the Internet Abraham Lincoln, US President Photo Source: Wikipedia Page 6

7 More Intelligence in Every System SMART Data Center Revolution New Opportunities to Control Costs and Increase Strategic Advantage MACHINES THAT UNDERSTAND Smart wireless networks to the rescue Carriers are turning toward more intelligent network management Smart Factories For factory management in the future, it will become essential to strive to implement smart capabilities The Next Big, Digital Economy; Smart Energy The energy market is undergoing a major transformation From Dumb Pipes to Smart Networks Page 7 Page 7

8 Trend Wired Infrastructure: Software Defined Networks Slide credit: From Virtualizing the Net by Jon Turner (2004) Page 8

9 Trend Wireless Infrastructure: Scalable Platforms Capacity Indoor Outdoor Macrocell Macrocell + Active Antennas Microcell Picocell Residential Femto 4-16 Users <100mW Home Enterprise Femto Users <250mW Office Users <1W Dense Indoor (Malls, Transport Hubs) Urban Infill ~200 Users <1-10W Single Sector Wide Area ~200 Users/ sector W Multi-Sector Wide Area 2-3x Data Capacity of RRU Coverage Page 9

10 Trend Data Center Infrastructure: Cloud Computing Big Data Increasing Volume, Velocity, and Variety Low power Reduce operation and cooling costs Security Both outside and inside Page 10

11 Industry Mandates Programmable Imperative Programmable Systems Integration Insatiable Intelligent Bandwidth Page 11

12 The Era of All Programmable SoC Page 12

13 CPU + FPGA Evolution PCIe FSB QPI PCIe PCIe GBit/s Bandwidth Equal BW: FSB vs PCIe FSB/QPI: 2x PCIe BW PCIe IO Device Cache Flush In-Socket Accelerator Direct Cache Access PCIe FSB/QPI Device Driver Call Shared Memory Function Page 13

14 Extended Processing: Embedded ARM Processor System boots first Separate power for PL* Peripherals alive before PL configuration Processor controls PL configuration Multiple security levels supported Boot in secure or non-secure mode Download PL image via network, SD, USB Multiple AXI interfaces to PL Processor System can access IP in PL PL IP has access to Processor System peripherals and memory system at full BW *PL = Programmable Logic Page 14

15 Programmable Platform Opportunity Metric Bandwidth Latency > Double 4x lower Soft IP Soft IP Soft IP Soft Accelerator Soft Accelerator Major Leap in Cost and Performance Page 15

16 FPGA/CPU Use Models FPGA 0 Pipelined datapath HDL programmed Control Processor FPGA 1 Pipelined datapath with SW control CPU sets register values CPU Memory 2 CPU + FPGA co-processing FPGA part of explicit address space FPGA CPU FPGA Virtual Virtual $ $ Cache Coherency Memory 3 CPU + FPGA peer processing Cache Coherency Page 16

17 Programmable Platform: CPU + FPGA Peer Processing Core Core Accel Accel Logic L1 Cache L1 Cache L1 Cache L1 Cache Shared L2 Cache Coherency Engine Capabilities Coherent Caches for HW Coherency Engine Over NOC Interconnect Coherent Caches for SW Coherency Management DDR MemCon SRAM I/O Device DMA Coherency Benefits: Peer Processing: Direct Cache-2-Cache data movement Latency: Very low latency access to CPU (FPGA) data Usability: No SW cache flush needed Page 17

18 Design Flow Overview Software Design Flow Software Refinement Software Development Profiling SW/HW Partitioning Vivado HLS Refinement SW Compiler HW Synthesis Executable Bit Stream Page 18

19 Programming High Level Programming Accelerators : from C2FPGA C/C++ Serial application on standard processor C/C++ Source Dynamic library call C Inner Loop Compile directly from C to FPGA- ISA High-performance interconnect Parallel algorithm On FPGA Page 19

20 Programming Accelerators from C/C++ Enables software programmers to target Xilinx FPGAs Software-programmability Portability: 7 series, Zynq Report C/C++ Algorithm Vivado HLS Directives Delivers productivity increase for RTL designers C/C++ level verification and testbench reuse Earlier area/latency reports Software-driven design exploration RTL Design Vivado (ISE/EDK) Bitstream More Turns Per Day (Verification and Architecture Exploration) Page 20

21 Quality From of Results C Algorithm to FPGA Implementation Video frames/second FPGA resources DSP C2FPGA 2 0 RTL C2FPGA FPGA: >38 times better performance than DSP video processor QOR: C2FPGA equal to or better than RTL synthesis Ease-of-use: C2FPGA 2x fewer lines of C code than DSP processor Page 21

22 Vivado IP Integrator Enabling Reuse and Delivering Fully Functional IP Subsystems IP Packager Source (C, RTL, IP) Simulation models Documentation Example Designs Test bench Standardized IP-XACT IP Subsystem Xilinx IP 3 rd Party IP User IP Uses multiple plug-and-play forms of IP to implement functional subsystem Includes software drivers and API Accelerates integration and productivity Page 22

23 Vivado IP Integrator Intelligent IP Integration Co-Optimized for platforms Target platform aware Supports All Programmable Zynq and 7 series kits HP C (J2 2) LP C (J2 ) PCIE(P1) Co-Optimized for silicon IP aware automated AXI Interconnects for maximum performance or area Automated interface, device driver & address map generation for Zynq and MicroBlaze Page 23

24 Vivado IP Integrator Intelligent IP Integration System Hierarchy View Interface Connections with Live DRCs Hierarchy Support Correct-by-construction Extensible IP repository Real-time DRCs and parameter propagation/resolution TCL Console Extensible IP Repository Automated IP Subsystems Block automation for rapid design creation One click IP customization Page 24

25 Zynq in Wireless Digital Front End Cost and power reduction by integrated solution Performance increase by exploiting the massive compute power of multi-core processors and programmable logic Page 25

26 Programmable Digital Pre-Distortion x z y Pre- 0 PA Distorter HW SW + Accelerators Coefficients (A) LS Estimator Alignment CC AMC y DPD negates PA non-linearity PAs consume massive static power DPD improves PA efficiency by ~35-40% Page 26

27 HW Acceleration Update Time (ms) x speed-up for VW Cholesky VW Alignment 320ms 0 Original Optimized NEON PL Accelerator 3% ZC7020 Algorithm optimization A9 SW optimization Vivado HLS optimization Page 27

28 HW Accelerator Resources DSP FF LUT Accelerated Unroll=1 Unroll=2 Unroll= MicroBlaze Zynq Page 28

29 DPD Architecture Data Movement FF LUT ARM CoreSight Multi-core & Trace Debug NEON /FPU Engine Cortex -A9 MP Core 32/32 KB I/D Caches NEON /FPU Engine Cortex -A9 MP Core 32/32 KB I/D Caches AXI Infrastructure ~300 ~300 Accelerator KB L2 Cache Timers / Counters General Interrupt Controller Snoop Control Unit (SCU) 256 KB On-Chip Memory DMA Configuration Accelerator s Memory AMBA Switches AXI FIFO s m AXI4 Lite Interconnect m Reduced Resources Because of AXILite Infrastructure Page 29

30 DPD Architecture Data Movement FF LUT ARM CoreSight Multi-core & Trace Debug NEON /FPU Engine Cortex -A9 MP Core 32/32 KB I/D Caches NEON /FPU Engine Cortex -A9 MP Core 32/32 KB I/D Caches AXI Infrastructure >3000 >3000 Accelerator KB L2 Cache Snoop Control Unit (SCU) Timers / Counters General Interrupt Controller 256 KB On-Chip Memory DMA Configuration s Accelerator Memory AMBA Switches AXI DMA m m AXI4 Lite Interconnect AXI4 Interconnect s High Throughput Because of DMA Infrastructure Page 30

31 Hardware/Software Boundary Software Hardware Function1 Function2 Function3 Execution time Low Medium High Cost comm Low Medium High ARM is idle Simple FIFO 300 LUTs Complex DMA 3000 LUTs Optimal cut point depends on execution times and cost of communication Implement different cut points is a time consuming task Goal: Maximize Throughput and Reduce Area Resources Page 31

32 Software Integration SW Comm HW Run time SW Comm HW Accelerator implementation Data motion network Optimal drivers Smart Software Driver is Necessary Page 32

33 HW/SW Design Flow CPU FPGA C-compiler Concurrent SW C-synthesis Application SW-drivers Middleware Libraries Platform AXI Hardware Wires CPU Memory Data Movement Interconnect Video Codec Encryption LTE Modem Page 33

34 HW/SW Design Flow: SW Programmer CPU FPGA C-compiler Concurrent SW C-synthesis Application SW-drivers Middleware Libraries AXI Hardware Wires CPU Memory Data Movement Interconnect Video Codec Encryption LTE Modem Page 34 Application Programming

35 Video Acceleration C/C++ Software Program Main program; Setup input; Setup Output; Image filter; Edge Detect; Motion Detect Difference; Draw on screen; Processing System Common Peripherals Memory Interfaces ARM Dual Cortex-A9 MPCore System 7 series Fabric Video In Video Out 1 frame per 13 seconds Page 35

36 Processor + Fabric Solution on Zynq-7000 AP SoC C/C++ Software Program Main program; Setup input; Setup Output; Image filter; Edge Detect; Motion Detect; Difference; Draw on screen; Processing System Common Peripherals Memory Interfaces ARM Dual Cortex-A9 MPCore System Image processing Accelerators 7 series Fabric Video IN Video Out Software video processing functions compiled onto FPGA fabric 60 frames per second, 700x speedup Page 36

37 FPGA/CPU Use Models FPGA 0 Pipelined datapath HDL programmed Control Processor FPGA 1 Pipelined datapath with SW control CPU sets register values CPU Memory 2 CPU + FPGA co-processing FPGA part of explicit address space FPGA CPU FPGA Virtual Virtual $ $ Cache Coherency Memory 3 CPU + FPGA peer processing Cache Coherency Page 37

38 Towards Heterogeneous Multi-core OpenCL Hardware / Software partitioning & interfacing C Compile / Debug ARM Processor HS-SW Interfacing Domain Specific API C-HLS Accelerator synth FPGA A9 A9 Commercial Software Ecosystem Video codec Encryption Packet Processing FFT Application-Specific Search Page 38

39 Opportunities for SoC Education Zynq OS Area Priority Research Teaching Embedded Systems Lab Comp Arch, SoC Linux DSP Projects Embedded Standalone Other OS Open Source Community CROME* *Controls, RObotics and MEchatronics Page 39

40 ZED Board ZED Board Zynq Evaluation and Development Kit Low cost Zynq based community board (XC7Z020) Partnership between Avnet, Digilent, Xilinx Digilent will fulfill academic market for Xilinx University Program ZEDboardorg Open source SW and IP Linux Eclipse based IDE Vivado HLS: C to FPGA Reference designs Page 40

41 Target Teaching Platform (TTP) Turn key solution for teaching labs on Digital Logic Digital Signal Processing Embedded System Design Principle of Microcomputers Embedded Operating Systems Xilinx updates the kit as and when required Slides Textbook Labs and instructions SW/IP/Tools XUP boards Page 41

42 ZED Block Diagram & Features Page 42

43 Targeted Teaching Platform (TTP) Initial version of the Smart Car TTP: ZynqBot Mark1 Controlled wirelessly by Android cell phone app Page 43

44 Conclusions Modern FPGA is an All Programmable SoC Software Centric Design Flow Unmatched Performance/Watt Towards Heterogeneous Multi-Core Targeted Teaching Platform Page 44