VLSI Digital Signal Processing

Transcription

1 VLSI Digital Signal Processing EEC 28 Lecture Bevan M. Baas Tuesday, January 9, 28

2 Today Administrative items Syllabus and course overview My background Digital signal processing overview Read Programmable DSP Architectures, Part I by E. A. Lee EEC 28, B. Baas 3

3 Course Communication Urgent announcements Web page Office hours After lecture Tuesday Tentatively Wednesday afternoon After lecture Thursday EEC 28, B. Baas 4

4 Course Workload 4 unit graduate course This course requires significant effort and time Multi-disciplinary field coverage DSP algorithms Digital processor architectures Arithmetic Utilizes robust industry-standard CAD tools (but we will make use of only the core essential features) Verilog Synthesis tool Matlab EEC 28, B. Baas 5

5 Course Overview EEC 28 web page contents Reading materials and references Hwk/Project descriptions Handouts edu/~bbaas/28/ EEC 28, B. Baas 6

6 Course Overview Canvas Grades posted here Let me know if you ever see a score different than you expect Upload electronic portions of hwk/projects here Syllabus Posted on course web page EEC 28, B. Baas 7

7 Lectures Ask questions at any time Please hold conversations outside of class Please silence phones Integrated Solid-State Circuits Conference (ISSCC) February 2 4 Quiz and guest lecture on Tue, Feb 3; or possibly a special make-up lecture EEC 28, B. Baas 8

8 Letter Grade Assignments I assign a letter grade only for the final course grade I look at the final exams and course record of the class and assign two key dividing points: the A/A+ and (probably B/B+) boundaries, and assign course grades from there using equallysized intervals No required numbers of any particular letter grades Absolute scores are not important; the boundaries shift according to the difficulty of the exams in any quarter Ignore any letter grades you might see on canvas A/A+ Example with hypothetical data: B/B+ B B+ A A+ EEC 8A, B. Baas 9

9 Critical Challenges Facing Industry Energy Efficiency Performance Software development cost and time Hardware development cost and time Opportunity: Critical workloads sometimes/frequently have relatively simple tasks as critical kernels (e.g., machine learning, digital signal processing, multimedia, data record processing, pattern matching, etc.) Embedded (e.g., IoT) Mobile Datacenter B. Baas 9

10 Number of Processors on a Single Die vs. Year Academic Industry Note: Each processor capable of independent program execution 23

11 Processor Eras Transistor Era: the Intel 44 was the first commercial single-chip microprocessor and it contained 23 hand-drawn transistors Single/Multi-Processor Era: focus on components of single processors and multi-processors, which generally scale well to only small numbers of processors -Processor Era: focus on making systems scalable and working with processors as building blocks. The 32 nm -processor KiloCore chip would contain approximately processors if its area were the same as a 32 nm Intel Core i7 processor, or, processors if its area were the same as an Nvidia GP B. Baas 24

12 Future Fabrication Technologies Basic trends Number of available devices: continually increasing Energy dissipation per operation: decreasing too slowly VDD2 VDD3 VDD There are a lot of ways to place and connect a billion transistors The most efficient implementations (throughput, energy, area) will have: Processor sizes that capture computational kernels with few excess circuits Optimized clock frequencies and supply voltages matched to dynamic workloads EEC 28, B. Baas 25

13 Optimal Computational Tile Size The most efficient implementations (energy, throughput, chip area) have: Processor sizes that capture computational kernels with few excess circuits ~ ~~ ~ ~~ Interprocessor interconnect Unused or low benefit-per-cost circuits Energy Effic. Clock rate Area Effic. Tile Size 26

14 27 Some Benefits of Fine-Grain Many-Core Die drawn approximately to scale Single Processor Cores per area of ARM A9 22 mw/ghz per.55 mm^2 area ARM Cortex-A9 643 mw/ghz Intel Atom Clover Trail.5 2 mw/ghz ARM Cortex-A mw/ghz MIT RAW mw/ghz UC Davis KiloCore mw/ghz ARM Cortex-A9 Intel Atom Clover Trail Saltwell ARM Cortex-A5 MIT RAW UC Davis KiloCore

15 KiloCore Chip Technology 32nm IBM PDSOI CMOS Num. Procs. 8 mm 7.82 mm Num. Mems. 2 Num. Oscs. 22 Die Area 64 mm 2 Array Area 6 mm mm 8 mm Transistors C4 Bumps Package 62 Million 564 (62 I/O) 676 Pad Flip-Chip BGA Slide 28

16 KiloCore Chip 29

17 Advancing CMOS Technologies Moore s Law (Observation) was made in 965 and notes that transistor density ~doubles every year (every.5 years now) "Cramming more components onto integrated circuits," Gordon Moore, Electronics, April 9, 965. EEC 28, B. Baas 3

18 Transistors (thousands) Number of Logical Cores Original data up to the year 2 collected and plotted by M. Horowitz, F. Labonte, O. Shacham, K. Olukotun, L. Hammond, and C. Batten New plot and data collected for 2-25 by K. Rupp New data added by B. Baas B. Baas 32

19 Digital Signal Processing Digital Discrete time Discrete valued Signal, 2, 3, dimensional Processing Analysis Synthesis Enhancement EEC 28, B. Baas 33

20 DSP Workloads Often real-time Data producer and consumer can not be paused or held up Examples: antenna, controller, camera, video monitor, Very strict minimum performance levels Performance above that minimum is often of little value Data producer DSP system Data consumer EEC 28, B. Baas 34

21 DSP Workloads Analysis. Ex: anti-lock brakes Data producer Maybe MSamples/sec DSP system Maybe Sample/sec Synthesis. Ex: music keyboard DSP system Data consumer EEC 28, B. Baas 35

22 DSP Workloads Data stream can be considered infinite duration Length of data stream >> any buffering Ex: high-pass filter, automotive collision-detection radar distance measurement system DSP system EEC 28, B. Baas 36

23 DSP Workloads Digital signal processing Typically very numerically intensive Lots of +, -, x DSP system EEC 28, B. Baas 37

24 DSP Compared with Analog Processing Digital signal processing Compare with analog signal processing If possible in analog domain (at required precision), analog processing will likely require far fewer devices If possible in analog domain, either domain may produce the most energy-efficient solution Many algorithms are possible only with DSP (arbitrarily high precision, non-causal, ) DSP arithmetic is completely stable over process, temperature, and voltage variations Ex: = 5. will always be true as long as the circuit is functioning correctly EEC 28, B. Baas 38

25 DSP Compared with Analog Processing Digital signal processing Compare with analog signal processing DSP energy-efficiencies are rapidly increasing Once a DSP processor has been designed in a portable format (gate netlist, HDL, software), very little effort is required to port (re-target) the design to a different processing technology. Analog circuits typically require a nearly-complete re-design. DSP capabilities are rapidly increasing Analog A/D speed x resolution product doubles every 5 years Digital processing performance doubles every 8-24 months (6x to x every 5 years) EEC 28, B. Baas 39

26 Common DSP Applications Early applications Instrumentation Radar Communication Imaging Current applications Consumer audio, video Networking Telecommunications Machine learning Imaging Many many more EEC 28, B. Baas 4

27 Consumer Products Trends Analog based Digital based Music records, tapes CDs, MP3s Video VHS, 8mm DVD, Blu-ray, H.264, H.265 Telephony analog mobile (G) digital (4G, LTE, ) Television NTSC/PAL digital (DVB, ATSC, ISDB, ) Many products use digital data and speak digital: computers, networks, digital appliances Impacts Processing Transmission Storage etc. EEC 28, B. Baas 4

28 Future Applications Very limited power budgets Require significant digital signal processing EEC 28, B. Baas 42

29 Key Design Metrics ) Performance a) Throughput (high); e.g., 25 MSamples/sec b) Latency (low); e.g., 2.7 µsec from first sample in -> first out c) Numerical precision 2) Chip area (cost); e.g., mm 2 die area, area of standard cell netlist 3) Energy dissipation per workload, e.g., Joules per JPEG image 4) Design complexity Design time = lower performance Software more important as systems become more complex 5) Suitability for future fabrication technologies Many transistors Faulty devices i) During manufacturing process ii) device wear out due to effects such as NBTI EEC 28, B. Baas 43