Serial Input/Output. Lecturer: Annie Guo. S1, 2006 COMP9032 Week13 1

Transcription

1 Serial Input/Output Lecturer: Annie Guo S1, 2006 COMP9032 Week13 1

2 Serial communication Concepts Standards USART in AVR Lecture overview S1, 2006 COMP9032 Week13 2

3 Why Serial I/O? Problems with Parallel I/O: Needs a wire for each bit. When the source and destination are more than a few feet the parallel cable can be bulky and expensive. Susceptible to reflections and induced noises for long distance communication. Serial I/O overcomes these problems. S1, 2006 COMP9032 Week13 3

4 Serial Communication System Structure Data From Source n Data To Destination n Transmit Data Buffer Received Data Buffer T clock Parallel In/Serial Out Shift Register Serial Data Serial In/Parallel Out Shift Register R clock TRANSMITTER RECEIVER S1, 2006 COMP9032 Week13 4

5 Serial Communication System Structure (cont.) At the communication source: The parallel interface transfers data from the source to the transmit data buffer. The data is loaded into the Parallel In Serial Out (PISO) register and T clock shifts the data bits out from the shift register to the receiver. S1, 2006 COMP9032 Week13 5

6 Serial Communication System Structure (cont.) At the communication destination: R clock shifts each bit received into the Serial In Parallel Out (SIPO) register. After all data bits have been shifted, they are transferred to the received data buffer. The data in the received data buffer can be read by an input operation via the parallel interface. S1, 2006 COMP9032 Week13 6

7 Serial Communication There are two basic types of serial communications synchronous asynchronous S1, 2006 COMP9032 Week13 7

8 Synchronous VS Asynchronous Synchronous Transmitter and receiver are synchronized Need extra hardware for clock synchronization Having faster data transfer rate Asynchronous Transmitter and receiver use different clocks. No clock synchronization is required. Used in many applications such as keyboards, mice, modems The rest of this lecture focuses on Asynchronous communication S1, 2006 COMP9032 Week13 8

9 UART The device that implements both transmitter and receiver in a single integrated circuit is called a UART (Universal Asynchronous Receiver/Transmitter). UART uses least significant first order The least significant bit of data is transferred first Data are transmitted asynchronously. Clocks on both sides are not synchronized But receivers have a way to synchronise the data receiving operation with data transmission operation UART is the basis for most serial communication hardware. S1, 2006 COMP9032 Week13 9

10 UART Structure Data Bus T clock1 Transmitter Receiver R clock2 Data Bus R clock1 Receiver Transmitter T clock2 UART UART S1, 2006 COMP9032 Week13 10

11 UART Data Formats Before transmission, data should be encoded Many encoding schemes, such as ASCII Each encoded data is encapsulated with two bits Start bit and stop bit Mark and space: the logic one and zero levels are called mark and space. When the transmitter is not sending anything, it holds the line at mark level, also called idle level. Least Significant Optional Stop Bit Parity Bit Bit Mark Space Start Bit Data Bits S1, 2006 COMP9032 Week13 11

12 UART Data Formats (cont.) Typical bits in data transmission: Start bit: When the transmitter has data to send, it first changes the line from the mark to the space level for one bit time. This synchronises the receiver with transmitter. When the receiver detects the start bit, it knows to start clocking in the serial data bits. Data bits: representing a data, such as a character Parity bit: used to detect errors in the data For odd parity: the bit makes the total number of 1s in the data odd For even parity: the bit makes the total number of 1s in the data even. Stop bit: added at the end of data bits. It gives one bit-time between successive data. Some systems require more than one stop bit. S1, 2006 COMP9032 Week13 12

13 Data Transmission Rate The rate at which bits are transmitted is called baud rate. It is given in bits per second Standard data rates Baud: 110, 150, 300, 600, 900, 1200, 2400, 4800, 9600, 14400, 19200, 38400, S1, 2006 COMP9032 Week13 13

14 Communication System Types Three ways that data can be sent in serial communication system: Simplex system Full-duplex (FDX) system Half-duplex (HDX) system S1, 2006 COMP9032 Week13 14

15 Simplex System Data are sent in one direction only For example, computer to a serial printer. Simple If the computer does not send data faster than the printer can accept it, no handshaking signals are required. Two signal wires are needed for this system. Computer Printer S1, 2006 COMP9032 Week13 15

16 Full-Duplex (FDX) System Data are transmitted in two directions. It is called four-wire system, although only two signal wires and a common ground are sufficient. Terminal Computer S1, 2006 COMP9032 Week13 16

17 Half-Duplex (HDX) System Data are transmitted in two directions with only one pair of signal lines. Additional hardware and handshaking signals must be added to an HDX system. Computer Computer S1, 2006 COMP9032 Week13 17

18 DTE & DCE There are two typical devices in communications DCE Data Communications Equipment DTE Provides a path for communication Data Terminal Equipment Connects to a communication line S1, 2006 COMP9032 Week13 18

19 DTE & DCE example A communication system for internet access PC and Internet provider server are DTEs Two modems are DCEs phone line PC modem modem Provider server S1, 2006 COMP9032 Week13 19

20 Modem A modulator/demodulator It converts logic levels into tones to be sent over a telephone line. At the other end of the telephone line, a demodulator converts the tones back to logic levels. S1, 2006 COMP9032 Week13 20

21 Standards for the Serial I/O Interface Interface standards are needed to allow different manufacturers equipment to be interconnected Must define the following elements: Handshaking signals Direction of data flow Types of communication devices. Connectors and interface mechanical considerations. Electrical signal levels. S1, 2006 COMP9032 Week13 21

22 Standards for the Serial I/O Interface (cont.) Popular standards include RS-232-C, RS- 422, RS-423 and RS-485. RS-232-C standard is used in most serial interface. If the signals must be transmitted farther than 50 feet or greater than 20 Kbits/second, another electrical interface standard such as RS-422, RS- 423 or RS-485 should be chosen. For RS-422, RS-423 and RS-485, handshaking, direction of signal flow, and the types of communication devices are based on the RS-232- C standard. S1, 2006 COMP9032 Week13 22

23 Two RS232-C Connectors DE9 pin assignments DB25 pin assignments S1, 2006 COMP9032 Week13 23

24 RS-232-C Signal Definitions DE9 DB25 Signal Purpose 1 PG Protective ground: this is actually the shield in a shielded cable. It is designed to be connected to the equipment frame and may be connected to external grounds. 3 2 TxD Transmitted data: Sourced by DTE and received by DCE. Data terminal equipment cannot send unless RTS, CTS, DSR and DTR are asserted. 2 3 RxD Received data: Received by DTE, sourced by DCE. 7 4 RTS Request to send: Sourced by DTE, received by DCE. RTS is asserted by the DTE when it wants to send data. The DCE responds by asserting CTS. S1, 2006 COMP9032 Week13 24

25 RS-232-C Signal Definitions (cont.) DE9 DB25 Signal Purpose 8 5 CTS Clear to send: Sourced by DCE, received by DTE. CTS must be asserted before the DTE can transmit data. 6 6 DSR Data set ready: Sourced by DCE and received by DTE. Indicates that the DCE has made a connection on the telephone line and is ready to receive data from the terminal. The DTE must see this asserted before it can transmit data. 5 7 SG Signal ground: Ground reference for this signal is separate from pin 1, protective ground. S1, 2006 COMP9032 Week13 25

26 RS-232-C Signal Definitions (cont.) DE9 DB25 Signal Purpose 1 8 DCD Data carrier detect: Sourced by DCE, received by DTE. Indicates that a DCE has detected the carrier on the telephone line. Originally it was used in half-duplex systems but can be used in full-duplex systems, too DTR Data terminal ready: Sourced by DTE and received by DCE. Indicates that DTE is ready to send or receive data RI Ring indicator: Sourced by DCE and received by DTE. Indicates that a ringing signal is detected. S1, 2006 COMP9032 Week13 26

27 RS-232-C Interconnections When two serial ports are connected, the data rate, the number of data bits, whether parity is used, the type of parity, and the number of stop bits must be set properly and identically on each UART. Proper cables must be used. There are four kinds of cables from which to choose, depending on the types of devices to be interconnected. Full DTE DCE cable Minimal DTE DCE cable DTE DTE null modem cable Minimal null modem cable S1, 2006 COMP9032 Week13 27

28 RS-232-C Interconnections (cont.) DE9 DB25 DB25 DE9 DTE DTE DCE DCE TxD TxD RxD RxD SG SG RTS RTS CTS CTS DCD DCD DSR DSR DTR DTR Full DTE DCE cable S1, 2006 COMP9032 Week13 28

29 RS-232-C Interconnections (cont.) DE9 DB25 DB25 DE9 DTE DTE DCE DCE TxD TxD RxD RxD SG SG RTS RTS CTS CTS DCD DCD DSR DSR DTR DTR Minimal DTE-DCE cable S1, 2006 COMP9032 Week13 29

30 RS-232-C Interconnections (cont.) DE9 DB25 DB25 DE9 DTE DTE DTE DTE TxD TxD RxD RxD SG SG RTS RTS CTS CTS DCD DCD DSR DSR DTR DTR DTE DTE null modem cable S1, 2006 COMP9032 Week13 30

31 RS-232-C Interconnections (cont.) DE9 DB25 DB25 DE9 DTE DTE DTE DTE TxD TxD RxD RxD SG SG RTS RTS CTS CTS DCD DCD DSR DSR DTR DTR Minimal null modem cable S1, 2006 COMP9032 Week13 31

32 RS-232-C Interface RS-232-C Logic levels: Mark -25 to 3 volts Space +25 to +3 volts TTL Logic levels D RS-232-C Logic levels R TTL Logic levels S1, 2006 COMP9032 Week13 32

33 RS-423 Standard Also a single ended system. Allows longer distance and higher data rates than RS-232-C. Allows a driver to broadcast data to 10 receivers. D R Up to 10 receivers R RS-423 Interface S1, 2006 COMP9032 Week13 33

34 RS-422 Standard RS-422 line drivers and receivers operates with differential amplifier. These drivers eliminate much of the commonmode noise experienced with long transmission lines, thus allowing the longer distances and higher data rates. D R Up to 10 receivers R RS-422 Interface S1, 2006 COMP9032 Week13 34

35 RS-485 Standard Similar to RS-422 in that it uses differential line drivers and receivers. Unlike RS-422, RS-485 provides for multiple drivers and receivers in a bussed environment. Up to 32 drivers/receivers pairs can be used together. D Up to 32 drivers R Up to 32 receivers D R RS-485 Interface S1, 2006 COMP9032 Week13 35

36 USB sbbus.pdf S1, 2006 COMP9032 Week13 36

37 Electus Distribution Reference Data Sheet: USBBUS.PDF (1) The USB or Universal Serial Bus In the latest PCs, many of the peripherals such as the keyboard, mouse, scanners, printers, modem and even external CD-ROM drives and CD-writers connect to the computer itself via a USB cable either directly or via a hub expander unit. Here s a brief introduction to the Universal Serial Bus or USB, which was developed expressly for this job. As personal computers became more and more powerful and began to be used to handle photographic images, audio, video and other bulky data, it became evident that existing communications buses were not going to be good enough to carry the data back and forth between the computers and their growing array of peripherals especially as users wanted the data to be moved around faster, rather than more slowly. So a group of leading computer and telecom firms including IBM, Intel, Microsoft, Compaq, Digital Equipment, NEC and Northern Telecom got together and developed USB. The USB is a medium-speed serial data bus designed to carry relatively large amounts of data over relatively short cables: up to about five metres long. It can support data rates of up to 12Mb/s (megabits per second), which is fast enough for most PC peripherals such as scanners, printers, keyboards, mice, joysticks, graphics tablets, low-res digital cameras, modems, digital speakers, low speed CD-ROM and CD-writer drives, external Zip disc drives and so on. The USB is an addressible bus system, with a seven-bit address code so it can support up to 127 different devices or nodes at once (the all zeroes code is not a valid address). However it can have only one host : the PC itself. So a PC with its peripherals connected via the USB forms a star local area network (LAN). On the other hand any device connected to the USB can have a number of other nodes connected to it in daisy-chain fashion, so it can also form the hub for a mini-star subnetwork. Similarly you can have a device which purely functions as a hub for other node devices, with no separate function of its own. This expansion via hubs is because the USB supports a tiered star topology, as shown in Fig.1. Each USB hub acts as a kind of traffic cop for its part of the network, routing data from the host to its correct address and preventing bus contention clashes between devices trying to send data at the same time. On a USB hub device, the single port used to connect to the host PC either directly or via another hub is known as the upstream port, while the ports used for connecting other devices to the USB are known as the downstream ports. This is illustrated in Fig.2. USB hubs work transparently as far as the host PC and its operating system are concerned. Most hubs provide either four or seven downstream ports, or less if they already include a USB device of their own. Another important feature of the USB is that it s designed to allow hot swapping : devices can be plugged into and unplugged from the bus without having to turn the power off and on again, re-boot the PC or even manually start a driver program. A new device can simply be connected to the USB, and the PC s operating system should recognise it and automatically set up the necessary driver to service it. Windows 98 and later versions of Windows 95 do this, as do the latest Macintosh operating systems. Power and data USB cables consist of two twisted pairs of wires, one pair used to carry the bidirectional serial data and the other pair 5V DC power. This makes it possible for low-powered peripherals such as a mouse, joystick or modem to be powered directly from the USB or strictly from the host PC (or the nearest hub) upstream, via the USB. Most modern PCs have two USB ports, and each can provide up to 500mA of 5V DC power for buspowered peripherals. Individual peripheral devices (including hubs) can draw a maximum of 100mA from their upstream USB port, so if they require less than this figure for operation they can be bus powered. If they need more, they have to use their own power supply such as a plug-pack adaptor. Hubs should be able to supply up to 500mA at 5V from Fig.1: The USB is a medium speed serial bus used to transfer data between a PC and its peripherals. It uses a tiered star configuration, with expansion via hubs (either separate, or in USB devices). Fig.2: The port on a USB device or hub which connects to the PC host (either directly or via another hub) is known as the upstream port, while hub ports which connect to additional USB devices are downstream ports. Downstream ports use Type A sockets, while upstream ports use Type B sockets.

38 Electus Distribution Reference Data Sheet: USBBUS.PDF (2) Fig.4: Most USB plugs have this distinctive marking symbol. Fig.3: Pin connections for the two different types of USB socket, as viewed from the front. each downstream port, if they re not bus powered. Serial data is sent along the USB in differential or push-pull mode, with opposite polarities on the two signal lines. This improves the signal-to-noise ratio (SNR), by doubling the effective signal amplitude and also allowing the cancellation of any common-mode noise induced into the cable. The data is sent in non-return-to-zero (NRTZ) format, with signal levels of 3.3V peak (i.e., 6.6V peak differential). USB cables use two different types of connector: Type A plugs for the upstream end, and Type B plugs for the downstream end. Hence the USB ports of PCs are provided with matching Type A sockets, as are the Fig.5: Examples of the various kinds of USB signalling and data packets. downstream ports of hubs, while the upstream ports of USB devices (including hubs) have Type B sockets. Type A plugs and sockets are flat in shape and have the four connections in line, while Type B plugs and sockets are much squarer in shape and have two connections on either side of the centre spigot. (Fig.3) Both types of connector are polarised so they cannot be inserted the wrong way around. Fig.3 shows the pin connections for both type of connector, with sockets shown and viewed from the front. Note that although USB cables having a Type A plug at each end are available, they should never be used to connect two PCs together, via their USB ports. This is because a USB network can only have one host, and both would try to claim that role. In any case, the cable would also short their 5V power rails together, which could cause a damaging current to flow. USB is not designed for direct data transfer between PCs. All normal USB connections should be made using cables with a Type A plug at one end and a Type B plug at the other, although extension cables with a Type A plug at one end and a Type A socket at the other can also be used, providing the total extended length of a cable doesn t exceed 5m. By the way, USB cables are usually easy to identify as the plugs have a distinctive symbol moulded into them see Fig.4. Data formats USB data transfer is essentially in the form of packets of data, sent back and forth between the host and peripheral devices. However because USB is designed to handle many different types of data, it can use four different data formats as appropriate. One of the two main formats is bulk asynchronous mode, which is used for transferring data that isn t time critical. This is the format used to transmit data from a scanner or digital scanner for example, or to a printer. The packets can be interleaved on the USB with others being sent to or from other devices. The other main format is isochronous mode, used to transfer data that is time critical such as audio data to digital speakers, or to/from a modem. These packets must not be delayed by those from other devices. The two other data formats are interrupt format, used by devices to request servicing from the PC/host, and control format, used by the PC/host to send token packets to control bus operation, and by all devices to send handshake packets to indicate whether the data they have just just received was OK ( ACK ) or had errors ( NAK ). Some of the data formats are illustrated in Fig.5. Note that all data packets begin with a sync byte (01hex), used to synchronise the PLL (phase-locked loop) in the receiving device s USB controller. This is followed by the packet identifier (PID), containing a four-bit nibble (sent in both normal and inverted form) which indicates the type of data and the direction it s going in (i.e., to or from the host). Token packets then have the 7-bit address of the destination device and a 4-bit end point field to indicate which of that device s registers it s to be sent to. On the other hand data packets have a data field of up to 1023 bytes of data following the PID field, while Start of Frame (SOF) packets have an 11-bit frame identifier instead and handshake packets have no other field. Most packets end with a cyclic redundancy check (CRC) field of either five or 16 bits, for error checking, except handshake packets which rely on the redundancy in the PID field. All USB data is sent serially, of course, and least-significant-bit (LSB) first. Luckily all of the fine details of USB handshaking and data transfer are looked after by the driver software in the PC and the firmware built into the USB controller inside each USB peripheral device and hub so normally all you have to do is hook it all together and perhaps supply a driver for a new device, when the PC s operating system can t find it. Most USB peripherals come with their driver on a floppy disk or CD-ROM. (Copyright Electus Distribution, 2001)

39 Firewire rewire.pdf S1, 2006 COMP9032 Week13 37

40 Jaycar Electronics Reference Data Sheet: FIREWIRE.PDF (1) IEEE 1394 (AKA FireWire & ilink ) Around 1986, Apple Computer Inc developed a very fast but relatively low cost serial interface for distributing digital audio and other bulk data between personal computers, and between computers and their peripherals. The new high speed serial interface was designed to replace the relatively expensive SCSI parallel interface, and Apple dubbed it FireWire (which is still an Apple trademark). Firewire was so successful that other manufacturers soon began using it under licence. In 1995 Sony released its DCR-VX1000 digital video camcorder, which featured essentially the same interface for input and output of digital video. Sony dubbed the interface ilink, and has gradually provided the interfaces on all of its digital camcorders and VCRs. (ilink is a Sony trademark.) It was soon realised that the FireWire/iLink interface was ideal not just for conveying digital video and audio, but for fast transfer of large amounts of any kind of digital data. Because of this the IEEE (Institution of Electrical and Electronics Engineers) established it in 1995 as an industry standard data interface, known as IEEE or IEEE 1394 for short. Nowadays IEEE 1394 interfaces are used on a very wide range of digital equipment, both in the computer and entertainment electronics industries. They re standard on the majority of digital camcorders and VCRs, as well as on video editing workstations and advanced computer graphics systems, and will probably be standard on the new DVD-RW and DVD-RAM video recorders. They re increasingly found even inside large workstations and servers, to interface peripherals like large hard disk drives and arrays, CD-writers and scanners. In fact it looks very much as if IEEE 1394 could well become the standard high speed interface for the coming era of digital convergence the merging of computers, communications and entertainment technology. Note that although there are some similarities between IEEE 1394 and the USB, there are quite a few differences. USB is slower and essentially designed for networks with a single host (the PC), whereas IEEE 1394 can be used for peer-to-peer communication. A digital camcorder can stream video and audio data to both a digital VCR and a DVD-RAM recorder simultaneously via an IEEE 1394 network, for example, with no need for assistance from a PC or other network controller device (after it has been allocated an isochronous channel for the transfer see later). Fast & powerful IEEE 1394 can transmit data at three rates: , and Mb/s (megabits per second), which are usually rounded to 100Mb/s, 200Mb/s and 400Mb/s and officially labelled S100, S200 and S400 respectively. As you can see even the lowest rate is nearly 10 times that of USB. Most consumer equipment like digital camcorders, VCRs and DVD-RAM recorders use the S100 rate, which is more than capable of handling a compressed video-and-audio data stream. The majority of PCI/IEEE 1394 interface adaptor cards for PCs will also support S200, while some can also support S400. Like USB, IEEE 1394 is designed to allow hot swapping. Devices can be connected and/or disconnected without turning off the power or resetting, etc. The device which is performing the bus manager role constantly monitors bus status, and reconfigures it dynamically whenever nodes are added or disconnected. Data is transferred on the IEEE 1394 bus in addressed packets, and is transaction-based. The transfers can be asynchronous or isochronous. Asynchronous transfers are used mainly for bus configuration, setting up transfers and handshaking, but are also used for bulk data transfer to and from hard disk drives, etc. Isochronous transfers are used for transporting timesensitive data like digital video and audio. IEEE 1394 data packets have a 64-bit address header, which is divided into a 10-bit network address, a 6-bit node address and the remaining 48 bits for data (or mode control) memory addresses at the receiving node. This gives IEEE 1394 the ability to address 1023 networks of 63 nodes, each with up to 281TB (terabytes) of data addresses. In practical terms this tends to mean up to 63 devices can be hooked up via IEEE 1394 cables as a network, with each device able to have tens or even hundreds of Fig.1: A fairly typical IEEE 1394 network used in a digital video editing studio. The PC would generally take the role of bus manager and isochronous resource manager. Fig.2: How the DS coding works. The Strobe signal is produced at the transmitting port, by exclsuive-oring the Data and Clock. Then at the receiving end the Clock is reconstructed by exclusive-oring the Data and Strobe signals.

41 Jaycar Electronics Reference Data Sheet: FIREWIRE.PDF (2) Fig.3: The Strobe and Data signals are sent along the IEEE 1394 bus via two shielded twisted-wire pairs, TPA and TPB. gigabytes of memory and plenty of room for more! Typically devices have three IEEE 1394 ports, but they can have up to 27. This allows networks to be as simple as a DV camcorder connected to a digital VCR, or more complicated like the setup shown in Fig.1. As you can see this shows a tree topology, taking advantage of the ability of each device to act as a bus repeater or mini hub. One device on the bus acts as bus manager, and can also act as isochronous resource manager. The latter allocates bus bandwidth for isochronous data transfers when devices request them. When there s a PC in the network, it usually performs the roles of bus manager and isochronous resource manager. As the IEEE 1394 bus uses time-domain multiplexing (TDM), the isochronous resource manager allocates each isochronous transfer a channel consisting of so many bandwidth allocation units (i.e., a guaranteed proportion of the total time slots). A bandwidth allocation unit is 20.3ns, so there are 6144 of them in a IEEE 1394 basic cycle of 125us. However 25us of every cycle is always reserved for asynchronous control data transfers, so a maximum of 4195 units is available for isochronous transfers. Typically a stream from a DV camcorder to a PC or digital VCR might need to be allocated a channel of say 1800 bandwidth units, for about 30Mb/s. Only one data packet can occur every basic cycle for a particular isochronous transfer channel, using that channel s allocated bandwidth units. However multiple isochronous transfers can take place at the same time, providing there s enough bandwidth available. The transfers can even be at different rates say one at S100 and another at S200. If there isn t enough bandwidth available when a device requests it, it waits until the bandwidth does become available. Asynchronous transfers can have multiple data packets per basic cycle, within the 25us reserved for this type of signalling. Data-Strobe coding All data is sent along the IEEE 1394 bus in serial four byte (32-bit) words, called quadlets. And the quadlets are encoded together with their clock signal onto two NRZ (non return to zero) bus signals, using a technique known as Data-Strobe (DS) coding. This improves transmission reliability by ensuring that only one of the two signals changes in each data bit period. Fig.2 shows how DS coding works. The top waveform shows the Data bits being sent, while the bottom waveform shows the Clock signal. At the transmitting node these two are fed to an exclusive-or gate to generate the Strobe signal, shown in the centre. It s this signal and the Data signal which are sent along the bus, and as you can see there s only one change in the pair every bit period. At the receiving device, though, the Data and Strobe signals are again fed to an exclusive-or gate. The output of this gate effectively reconstructs the Clock signal again, with its timing still accurately locked to the Data. The DS coding therefore avoids the need for IEEE 1394 receivers to have a PLL (phase-locked loop). Twisted pairs The IEEE 1394 Data and Strobe signals are sent on cables with two separately shielded twisted-wire pairs, called TPA (twisted pair A) and TPB (twisted pair B). Transfers in one direction have the Strobe signal on TPA and the Data signal on TPB, while those in the opposite direction have the Data signal on TPA and the Strobe signal on TPB. Fig.3 shows the idea. There are two different kinds of IEEE 1394 cable, with matching connectors. The primary type of cable has not only the two separately shielded wire pairs TPA and TPB, but also two DC power conductors the negative being grounded. A cross-section of this type of cable is shown in Fig.4, and as you can see there s also an outer shield and sleeve. The IEEE 1394 standard allows nodes to be supplied with DC power via the two power conductors. The power can be supplied at a voltage between 8V and 33V, and the current can be up to 1.5 amps. Fig.4: The primary type of IEEE 1394 cable has a pair of power conductors as well as the two shielded signal pairs TPA and TPB. The type of cable shown in Fig.4 is used for most mainstream IEEE 1394 applications, such as interfacing large hard disk arrays to DV editing workstations. The second type of cable used for IEEE 1394 has only the two shielded twisted pairs TPA and TPB, and can therefore only be used for signal transfer. This is the type of cable first used in Sony s ilink, and is now commonly used for digital video applications. Most DV camcorders and VCRs use this type of cable. Due to the high speed at which IEEE 1394 works, cables between device nodes should be no longer than 5m long to limit signal attenuation. There should also be no more than 16 cable hops separating any two nodes in an IEEE 1394 network. Connectors Just as there are two types of cable, there are two types of IEEE 1394 connector to match. Not surprisingly one type provides six connections and the other only four. Both of the plugs are shown in Fig.5, together with

42 Jaycar Electronics Reference Data Sheet: FIREWIRE.PDF (3) their pinouts. The corresponding sockets and their pinouts are complementary, of course. As you can see both plugs are polarised and fairly compact. But the inserting section of the primary 6-pin plug is much larger (11.3 x 6.2mm) than that of the 4-pin plug, which is very small indeed (6.45 x 3.5mm). The larger plug is polarised by a pair of chamfers at one narrow end, while the smaller one has an indent in the centre of one side. Normally all devices with IEEE 1394 ports are fitted with sockets, and the cables have plugs at each end. Adapter cables are available to allow data transfer between devices with 6-pin and 4-pin sockets, with appropriate plugs at each end. (There are also short adaptor cables with a plug and a socket, to mate with a standard like-to-like cable.) NOTE that in all standard IEEE 1394 cables, the connections to the two signal twisted pairs are transposed between the two ends. That is, in a 6-pin to 6-pin cable pins 4 and 3 at each end connect to pins 6 and 5 at the other, respectively. Similarly in a 4-pin to 4-pin cable pins 2 and 1 at each end connect to pins 4 and 3 at the other, respectively. Because of their complex construction and the small size and precision of their connectors, IEEE 1394 cables can be quite expensive. Because of this and the tiny size of the 4-pin connectors in particular, they should be treated with care to ensure that they provide reliable communication at the fast data rates involved. Fig.5: The two different types of IEEE 1394 plug, and their basic pin connections. But note that the TPA and TPB connections are transposed in all standard IEEE 1394 cables. (Copyright Jaycar Electronics, 2002) IEEE 1394/FireWire Cables stocked by Jaycar A range of standard IEEE 1394/Firewire/i.Link cables are now stocked by Jaycar Electronics stores and authorised dealers. Here s a quick rundown on the cables available and their catalogue numbers: 4-pin to 4-pin Cables 2m long 5m long Cat No. WC-7640 Cat No. WC pin to 6-pin Cables 2m long 5m long 6-pin to 4-pin Cables 2m long 5m long Cat No. WC-7644 Cat No. WC-7645 Cat No. WC-7647 Cat No. WC-7648 For more information, please refer to the latest Jaycar Engineering Catalogue or visit

43 Two USART units Unit 0 Unit 1 AVR USARTs Each unit can be configured for synchronous or asynchronous serial communication USART unit 0 is used on our lab board to receive program code downloaded from the PC host via USB S1, 2006 COMP9032 Week13 38

44 AVR USARTs (cont.) Support many serial frames. Have transmission error detection Odd or even parity error Framing error Three interrupts on TX Complete TX Data Register Empty RX Complete. S1, 2006 COMP9032 Week13 39

45 USART Block Diagram S1, 2006 COMP9032 Week13 40

46 AVR USART Structure The USART consists of three components: clock generator, transmitter and receiver Clock generator consists of synchronization logic for external clock input used by synchronous slave operation, and the baud rate generator. Transmitter consists of a single write buffer, a serial Shift Register, Parity Generator and Control Logic for handling different serial frame formats. S1, 2006 COMP9032 Week13 41

47 AVR USART Structure (cont.) Receiver The Receiver is the most complex part of the USART module due to its clock and data recovery units. The recovery units are used for asynchronous data reception. In addition to the recovery units, the Receiver includes a Parity Checker, Control Logic, a Shift Register and a Receive Buffer (UDR). The Receiver supports the same frame formats as the Transmitter, and can detect Frame Error, Data Over Run and Parity Error. S1, 2006 COMP9032 Week13 42

48 Up to 30 formats combinations of Example Frame Formats 1 start bit (St) 5, 6, 7, 8, or 9 data bits no, even or odd parity bit (P) 1 or 2 stop bits (Sp) S1, 2006 COMP9032 Week13 43

49 Parity Bit Used to check whether the received data is different from the sending data Two forms of the parity bit Even parity P d d d d even n n Odd parity 0 P d d d d odd n n Where d i in the two formulas is a data bit, n is the number of data bits. 1 S1, 2006 COMP9032 Week13 44

50 Control Registers Three control registers are used in USART operation: UCSRA for storing the status flags of USART for controlling transmission speed and use of multiple processors UCSRB for enabling interrupts, transmission operations for setting frame formats for bit extension UCSRC For operation configuration S1, 2006 COMP9032 Week13 45

51 UCSRA USART Control and Status Register A S1, 2006 COMP9032 Week13 46

52 UCSRA Bit Descriptions Bit 7 RXC: USART Receive Complete Set when the receive buffer is not empty The RXC flag can be used to generate a Receive Complete interrupt Bit 6 TXC: USART Transmit Complete Set when the entire frame in the Transmit Shift Register has been shifted out and there are no new data present in the transmit butter TXC is automatically cleared when a transmit complete interrupt is executed. TXC can generate a Transmit Complete interrupt S1, 2006 COMP9032 Week13 47

53 UCSRA Bit Descriptions (cont.) Bit 5 UDRE: USART Data Register Empty Set when the transmit buffer (UDR) is empty Can be used to generate a Data Register Empty interrupt Bit 4 FE: Frame Error Set when the next character in the receive buffer had a Frame Error when received. Bit 3 DOR: Data OverRun Set when a Data OverRun condition is detected. A Data OverRun occurs when the receive buffers are all full and a new start bit is detected. S1, 2006 COMP9032 Week13 48

54 UCSRA Bit Descriptions (cont.) Bit 2 UPE: USART Parity Error Set when the next character in the receive buffer had a Parity Error when received and the Parity Checking was enabled Bit 1 U2X: Double the USART Transmission Speed Set for doubling the transfer rate for asynchronous communication Bit 0 MPCM: Multi-processor Communication Mode If set, all the incoming frames received by the USART Receiver that do not contain address information will be ignored. S1, 2006 COMP9032 Week13 49

55 UCSRB USART Control and Status Register B S1, 2006 COMP9032 Week13 50

56 UCSRB Bit Descriptions Bit 7 RXCIE: RX Complete Interrupt Enable Set to enable interrupt on the RXC flag Bit 6 TXCIE: TX Complete Interrupt Enable Set to enable interrupt on the TXC flag Bit 5 UDRIE: USART Data Register Empty Interrupt Enable Set to enable interrupt on the UDRE flag. S1, 2006 COMP9032 Week13 51

57 UCSRB Bit Descriptions (cont.) Bit 4 RXEN: Receiver Enable Set the enable the USART receiver. The Receiver will override normal port operation for the RxD pin when enabled. Disable the Receiver will flush the receive buffer invalidating the FE, DOR and UPE flags. Bit 3 TXEN: Transmitter Enable Set to enable the USART Transmitter The Transmitter will override normal port operations for the TxD pin when enabled. The disabling of the Transmitter will not become effective until transmissions are complete. S1, 2006 COMP9032 Week13 52

58 UCSRB Bit Descriptions (cont.) Bit 2 UCSZ2: Character Size The bit combined with the UCSZ1:0 bits in UCSRC sets the number of data bits in a frame. Bit 1 RXB8: Receive Data Bit 8 The ninth data bit of the received character when operating with serial frames with nine data bits. Must be read before reading the low bits from UDR Bit 0 TXB8: Transmit Data Bit 8 The ninth data bit in the character to be transmitted when operating with serial frames with nine data bits. Must be written before writing the low bits to UDR S1, 2006 COMP9032 Week13 53

59 UCSRC USART Control and Status Register C S1, 2006 COMP9032 Week13 54

60 UCSRC Bit Descriptions Bit 6 UMSEL: USART Mode Select 0: Asynchronous Operation 1: Synchronous Operation Bit 5:4 UPM1:0: Parity Mode Set to enable Parity bit operation UPM1 UPM0 Parity Mode 0 0 Disabled 0 1 Reserved 1 0 Enabled, Even Parity 1 1 Enabled, Odd Parity S1, 2006 COMP9032 Week13 55

61 UCSRC Bit Descriptions (cont.) Bit 3 USBS: Stop Bit Select 0: 1-bit 1: 2-bit Bit 2:1 UCSZ1:0: Character Size Together with UCSZ2 to determine the number of bits for a character UCSZ2 UCSZ1 UCSZ0 Character Size bit bit bit bit Reserved Reserved Reserved bit S1, 2006 COMP9032 Week13 56

62 UCSRC Bit Descriptions (cont.) Bit 0 UCPOL: Clock Polarity UCPOL Transmitted Data Changed Received Data Sampled (Output of TxD Pin) (Input on RxD Pin) 0 Rising XCK Edge Failing XCK Edge 1 Failing XCK Edge Rising XCK Edge S1, 2006 COMP9032 Week13 57

63 USART Initialization Initialization process consists of Setting the baud rate, Setting the frame format; and Enabling the Transmitter or the Receiver For interrupt driven USART operation, the Global Interrupt Flag should be cleared when doing the initialization S1, 2006 COMP9032 Week13 58

64 Initialize USART 1 Sample Code USART_Init: ; Set baud rate, which is stored in r17:r16 sts UBRR1H, r17 sts UBRR1L, r16 ; Enable receiver and transmitter ldi r16, (1<<RXEN1) (1<<TXEN1) sts UCSR1B,r16 ; Set frame format: 8 bit data, 2 stop bits ldi r16, (1<<USBS1) (3<<UCSZ10) sts UCSR1C,r16 S1, 2006 COMP9032 Week13 59

65 Data Transmission The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRB Register. A data transmission is initiated by loading the transmit buffer with the data to be transmitted. The CPU can load the transmit buffer by writing to the UDR I/O location. The buffered data in the transmit buffer will be moved to the Shift Register when the Shift Register is ready to send a new frame. The Shift Register is loaded with new data if it is in idle state (no ongoing transmission) or immediately after the last stop bit of the previous frame is transmitted. When the Shift Register is loaded with new data, it will transfer one complete frame at the rate given by the baud register, U2X bit or by XCK depending on mode of operation. S1, 2006 COMP9032 Week13 60

66 Data Transmission Sample code The code below uses polling of the Data Register Empty (UDRE) flag. When using frames with less than eight bits, the most significant bits written to the UDR are ignored. USART_Transmit: ; Wait for empty transmit buffer lds r15, UCSR1A sbrs r15,udre1 rjmp USART_Transmit ; Put data (r16) into buffer, sends the data sts UDR1,r16 S1, 2006 COMP9032 Week13 61

67 Status of Data Transmission The USART Transmitter has two flags that indicate its state: USART Data Register Empty (UDRE) Set: when the transmit buffer is empty and ready to receiver new data Clear: when the transmit butter contains data to be moved into the shift register Transmit Complete (TXC) Set: when data in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer Clear: otherwise Both flags can be used for generating interrupts. S1, 2006 COMP9032 Week13 62

68 Data Reception The USART Receiver is enabled by writing the Receive Enable (RXEN) bit in the UCSRB Register The baud rate, mode of operation and frame format must be set up once before doing any transmissions. If synchronous operation is used, the clock on the XCK pin will be overridden and used as transmission clock. S1, 2006 COMP9032 Week13 63

69 Data reception Sample code USART_Receive: ; Wait for data to be received lds r10, UCSR1A sbrs r10, RXC1 rjmp USART_Receive ; Get and return received data from buffer lds r16, UDR1 S1, 2006 COMP9032 Week13 64

70 Status of Data Reception The Receive Complete (RXC) flag indicates if there are unread data present in the receive buffer. Set: when unread data exist in the receive buffer Clear: otherwise If the receiver is disabled (RXEN = 0), the receive buffer will be flushed and consequently the RXC bit will become zero. S1, 2006 COMP9032 Week13 65

71 Error Detection Three errors are checked on the receiver side: Frame error By checking whether the first stop bit is corrected received Parity error By checking whether the data received has the same (odd or even) number of 1 s as in the data from the tranmistter. Data OveRun error By checking if any data is yet read but is overwritten by incoming data frame. S1, 2006 COMP9032 Week13 66

72 Error Recovery Main sources of errors in asynchronous data transmission Data reception is out sync with transmission Noise added to the data S1, 2006 COMP9032 Week13 67

73 Error Recovery (cont.) AVR includes a clock recovery and a data recovery unit for handling errors in asynchronous transmission. The clock recovery logic is used for synchronizing the internally generated baud rate clock to the incoming asynchronous serial frames at the RxD pin. Based on the start bit The data recovery logic samples and low pass filters each incoming bit, thereby improving the noise immunity of the Receiver Based on multiple sampling and majority policy for each incoming bit S1, 2006 COMP9032 Week13 68

74 Error Recovery (cont.) The following figure gives an illustration The sample rate is 16 times the baud rate When the Clock Recovery logic detects a high (idle) to low (start) transition on the RxD line, it uses the samples 8, 9 and 10 to decide if it is a valid bit (namely, 0) If the majority of the three bits are 0, the bit is valid; data recovery is followed. If the majority of the three bits are 1, the bit is invalid; the circuit looks for next start bit. S1, 2006 COMP9032 Week13 69

75 Error Recovery (cont.) When the receiver clock is synchronized to the start bit, the data recovery can begin for each subsequent data bit. The decision of the logic level of the received bit is taken by doing a majority voting of the logic value to the three samples in the center of the received bit. S1, 2006 COMP9032 Week13 70

76 Reading Material Chapter 7: Computer Buses and Parallel Input and Output. Microcontrollers and Microcomputers by Fredrick M. Cady. Mega64 Data Sheet USART S1, 2006 COMP9032 Week13 71