DESIGN AND DEVELOPMENT OF MEMORY MANAGEMENT UNIT FOR MIL- STD-1750 PROCESSOR

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1 International Journal of Electronics and Communication Engineering & Technology (IJECET) Volume 7, Issue 3, May June 2016, pp , Article ID: IJECET_07_03_006 Available online at Journal Impact Factor (2016): (Calculated by GISI) ISSN Print: and ISSN Online: IAEME Publication DESIGN AND DEVELOPMENT OF MEMORY MANAGEMENT UNIT FOR MIL- STD-1750 PROCESSOR Prasad. S. and Dr Siva Yellampalli VTU Extension Centre, UTL Technologies Limited, Bangalore, Karnataka, India Naveen. V Control and Digital Electronics Group, ISAC, Department of Space, Bangalore, Karnataka, India ABSTRACT Processor Interface ASIC (PI ASIC) was widely used to provide processor interface logics for MAR31750 Processor along with MA31751 Memory Management Unit (MMU) chip. However with the diminishing availability of MA31750 processors, use of the Mil-Std processor of Honeywell make HX1750 as a replacement for the obsolete MAR Since HX-1750 processor does not have a compatible COTS MMU chip available, it was decided to functionality of the existing MMU chip (MA31751) onto an FPGA The remaining regular processor interface logics, similar to those in PI ASIC are also housed inside the Processor Interface FPGA. Considering the voluminous size of requirements, RTAX-1000S FPGA was chosen to implement the processor interface logics. With a system clock of 24MHz and an internal MMU inside the FPGA the cycle time for memory accesses has considerably been reduced. The embedded SRAM blocks of the RTAX-1000S FPGA are used as shared RAM between CPU and the 1553 device. Key words: MMU, FPGA, ASIC, BPU Cite this Article: Prasad. S. G, Dr Siva Yellampalli and Naveen. V, Design and Development of Memory Management Unit for MIL-STD-1750 Processor, International Journal of Electronics and Communication Engineering & Technology, 7(3), 2016, pp editor@iaeme.com

2 Design and Development of Memory Management Unit for MIL-STD-1750 Processor INTRODUCTION A memory management unit (MMU), sometimes called (PMMU) paged memory management unit. It is a computer hardware component for using accesses to memory requested by the CPU. First performing the translation of virtual memory addresses to physical addresses (i.e., virtual memory management), it is implemented as part of the central processing unit, but it can also be in the form of a separate integrated circuit. MMU is clearly performing the virtual memory management, bus arbitration, memory protection, cache control and bank switchin. ASIC VS FPGA Table 1 PI ASIC versus PI FPGA Processor Interface ASIC Designed for 12 MHz MMU external to ASIC Interface for Both Internal and External Shared RAMs Employs existing EDAC for RAMs Nature of Internal RAM : DP SRAM with 8K word of Memory I/O Decoding for some addresses not present EEPROM Interface logics absent Processor Interface FPGA Designed for 24 MHz MMU to address up to 1M locations Interface for Internal Shared RAM only Employs Core EDAC IP Core for Internal RAM and existing EDAC for External RAM Nature of Internal RAM : SRAM with single port, 8K word memory I/O Decoding for all I/O addresses present EEPROM Interface Logics provided NEED FOR MMU The HX-1750 processor can address a maximum of 64kB of memory through its address lines which falls short of 1MB of memory observed on onboard. Thus, the MMU caters to this need by providing extended addressing and making it possible for the processor address 1 MB of memory. DESIGN OF MMU Memory Management Unit is implemented in RTAX-1000 FPGA. The design of MMU is similar to that of the existing MA MMU chip [8]. The principal function of memory management unit is to provide extended addressing to the processor by means of address translation. The BPU of MA is not implemented in the memory management unit design. The MMU module is designed only to increase the memory addressing capability of the HX-1750 CPU. The processor inputs the 16 bit Address (ADDR_VALID [15:0]) and the Address State (AS [3:0]). The memory management unit performs address translation to output the Physical Page Address which is referred to by Extended Address (EA [7:0]). The extended 20 bit address is formed by the concatenation of EA [7:0] and the ADDR_VALID [11:0] as shown in the figure editor@iaeme.com

Prasad.S.G, Dr Siva Yellampalli and Naveen.V Figure 1 Generation of 20 bit Physical Address The main memory (SRAM) is divided in to 256 pages of size 4kB each.

The MMU decodes the incoming processor address to classify the command as either an operation on Instruction registers or Operand registers.

3 Prasad.S.G, Dr Siva Yellampalli and Naveen.V Figure 1 Generation of 20 bit Physical Address The main memory (SRAM) is divided in to 256 pages of size 4kB each. Therefore, the MMU may have an array of registers which contain the physical page addresses (PPA) of all the pages available within the memory. The MMU decodes the incoming processor address to classify the command as either an operation on Instruction registers or Operand registers. PAGE REGISTERS The main memory is divided into 256 pages of 4k words each. The MMU maps the system memory into these 4k word pages. A page is a block of physical page memory which is uniquely specified by the PPA [3]. A given address within any page is specified by the least significant twelve bits of the CPU address bus. Each page register is 8 bit wide and contains the physical page address of a page in the main memory. A total of 512 page registers divided into two groups of 256 registers each, one dedicated for Instruction memory space and one for Operand memory space. The MMU is initialized to provide a linear, one to one mapping of the PPA when system reset occurs. The CPU may change the mapping when it is in privileged instruction mode using XIO commands 5100 to 52FF as defined in MIL-STD Two register banks, one for instruction and one for operand are created. Each bank is implemented as an 8 bit word array of length 256. Write Operation The processor data is written into the specified 8 bit register address (REG_ADDR). Write operation into the file registers occurs during the rising edge of the IOWR (write clock (W_CLK)) and when the write enable (WE) is high. Read Operation Two 256 to 1 MUX are placed one outside each set of page registers (instruction and operand page registers). Depending on the selection lines (REG_ADDR), the 48 editor@iaeme.com

Design and Development of Memory Management Unit for MIL-STD-1750 Processor multiplexer selects the content of required page register and relays it to the 2 to 1 multiplexer as show in figure 2.

The MMU data for processor read is routed to the processor data bus in the data bus routing module when the enable MMU_DATA_CS is activated.

4 Design and Development of Memory Management Unit for MIL-STD-1750 Processor multiplexer selects the content of required page register and relays it to the 2 to 1 multiplexer as show in figure 2. The 2 to 1 MUX selects between the signals EA_INSTRUCTION and EA_OPERAND depending upon the selection line REG_ADDR to output MMU_DATA_OUT. The data for processor read is always available on EA [7:0]. The MMU data for processor read is routed to the processor data bus in the data bus routing module when the enable MMU_DATA_CS is activated. Figure 2 Read/write logic on Page registers Translation Two 256 to 1 multiplexers are placed one outside each set of page registers (instruction and operand page registers). Depending on the selection lines (TRANS_ADR), the multiplexer selects the contents of required page register and relays it to the 2 to 1 multiplexer. TRANS_ADR to the multiplexer is formed by the concatenation of AS [3:0] and ADDR_VALID [3:0]. MMU_TRANS_PORT always contains the contents of the register specified by TRANS_ADR. MMU_TRANS_PORT is either EA_INSTRUCTION or EA_OPERAND depending upon the bank which outputs MMU_TRANS_PORT. The 2 to 1 multiplexer in the right hand corner [9]. Depending upon the value of the selection line DI, either the EA_INSTRUCTION or the EA_OPERAND is selected and relayed as the required EA [7:0] as an output of the memory management unit module. Identical to read, the translation operation is asynchronous. EA [7:0] is always available outside the memory management unit module irrespective of any translation enable. To make use of EA [7:0], the processor asserts the IOM signal to logic low. The extended 20 bit address is formed by concatenation of EA [7:0] and the ADDR_VALID [11:0] editor@iaeme.com

Prasad.S.G, Dr Siva Yellampalli and Naveen.V SIMULATION AND RESULTS The simulated results obtained using ModelSim simulator and the device utilization obtained using Libero Microsemi.

5 Prasad.S.G, Dr Siva Yellampalli and Naveen.V SIMULATION AND RESULTS The simulated results obtained using ModelSim simulator and the device utilization obtained using Libero Microsemi. The VHDL code for memory management unit module was simulated for all combinations of Data, Address and Control signals. Figure 3 Write operation timing waveform Figure 4 Read operation timing waveform 50 editor@iaeme.com

6 Design and Development of Memory Management Unit for MIL-STD-1750 Processor Figure 5 the simulated result of the MMU SL. No Test case 1 Operand Register Read from Locations D200 to D2FF 2 Instruction Register Read from locations D100 to D1FF 3 Operand Register Write from Locations 5200 to 52FF 4 Instruction Register Write from Locations 5100 to 51FF 5 Operand Translation for TRANS_ADR values ranging from 00 to FF 6 Instruction Translate for TRANS_ADR values ranging from 00 to FF 7 Operand Register and Instruction Register Read with IOM =0 8 Operand and Instruction Translate with IOM=1 Table 2 List of FPGA Simulation Test Case CONCLUSION AND FUTURE WORK MMU for extending the 16 bit processor address to reference 1M words (20 bit address) with the use of 256 Instruction and Operand page register each has been designed, tested for implementation. This design work will optimize the board by limiting the need for a dedicated memory management unit device and also helps to tide over the obsolescence in the MIL-STD-1750 compatible MMU. Microsemi RTAX1000S FPGA is used to realize the logics. Design and implementation of the MMU will be done in Microsemi s Libero environment using VHDL language editor@iaeme.com

7 Prasad.S.G, Dr Siva Yellampalli and Naveen.V Future work can integrate the Block Protection Unit (BPU) for memory protection into the design as with the case of the dedicated Memory Management Unit. REFERENCES [1] ISRO ASIC /FPGA design and development guidelines. [2] John L. Hennsley and David A. Patterson, Computer Architecture A quantitative approach, 2 edition Morgan Kaufmanns publishers inc. San Francisco, California, [3] Memory management overview, Karl Ingström, Anders Daleby. Department of Computer Engineering, University of Mälardalen, Sweden, [4] K.C. Chang, Digital Design & Modeling with VHDL & Synthesis IEEE Computer society press. [5] Radiation-Hardended FPGAs Datasheet -Actel Corporation. See the Actel website for the latest version of the datasheet. V3.1. Radiation-Hardened FPGAs. Features [6] Processor Interface ASIC (PI-ASIC) design document. [7] Stefan Sjoholm, VHDL for Designers Pearson Prentice Hall. [8] MA User configurable, the MA31751 can perform as an MMU, a BPU or both MMU and BPU, conforming to MA31751 devices can be used to give 16M wordsoflogical. SOS/Datasheets/DNX_MA31751_Jul02.pdf. [9] Operating system concepts, 4ed, A. Silberschatz and P.B Galvin, ISBN , 1994, Addison-Wesley. [10] J.K. Kishore, A memory management unit for satellite recovery experiment, International Astronautical Congress [11] R. Revathi S. Sinthuja Dr. N. Manoharan and N. Rajendiran, Allocation of Power in Relay Networks for Secured Communication, International Journal of Advanced Research in Engineering & Technology, 6(8), 2015, pp [12] Dhanya Pushkaran and Neethu Bhaskar, AES Encryption Engine for Many Core Processor Arrays for Enhanced Security, International Journal of Electronics and Communication Engineering & Technology, 5(12), 2014, pp editor@iaeme.com

Chapter 5 Internal Memory

Chapter 5 Internal Memory Memory Type Category Erasure Write Mechanism Volatility Random-access memory (RAM) Read-write memory Electrically, byte-level Electrically Volatile Read-only memory (ROM) Read-only