Network on Chip round table European Space Agency, ESTEC Noordwijk / The Netherlands 17 th and 18 th of September 2009

Transcription

1 Network on Chip round table European Space Agency, ESTEC Noordwijk / The Netherlands 17 th and 18 th of September 2009 Ph. Armbruster Head of Data Systems Division European Space Agency - ESTEC 17 th of September 2009 NoC round table 1

2 The European Space Research and Technology Centre (ESTEC) 17 th of September 2009 NoC round table 2

3 17 th of September 2009 NoC round table 3

4 Overall goals : Avionics The Avionics sub-system corresponds to about 60% on the overall development costs for a satellite. Therefore, ESA is paying special attention to means allowing to decrease these costs by: Defining reference architectures, e.g. common to a series of missions, for instance Earth Observation, Science and Exploration missions Standardising interfaces, developing communication services and protocols Fostering re-use of building blocks Developing tools and methodologies for composing a system from already validated building blocks. 17 th of September 2009 NoC round table 4

5 System Services PUS library/ TMTC OBT Mgmt Context Mgmt SSMM Mgmt OBCP interpreter MTL services Equipment Mgmt Libraries: Math, Security, Payload, Software bus Application BB Plan/ Autonomy Framework Mission TL/ Mode mgmt Central FDIR AOCS Thermal Power P/L Manager Reference Architecture and Building Blocks Space Avionics Open Interface Architecture (SAVOIR) Devices Execution framework SOIS Application Suppport Layer Middleware services RTOS Standardized devices Sensors (Star Trackers, Sun sensors, Gyros, Earth sensors, magnetometers) Actuators (Reaction wheels, magneto torquers, thrusters, etc) Legacy devices Payloads & Instruments High Speed Telemetry Encryption Storage Compression TM/TC Security Unit SSMM Solid State Mass Memory File Mgt Compress Encrypt SOIS Layers OBC Hardware CAN MIL-1553 Subnetwork Layer HDSW RS422 SpW CPU/ NGmP RAM EEPROM BSP Boot PROM OBTimer SGM HW watchdog RTU/ Intelligent IO SOIS Layers ADCs / DACs Digital Sensorbus Standardized devices Sensor and actuators SOIS Layers Networks Payload Data Processing DSP Payload Control Computer SOIS Layers Onboard Communications H/W (e.g. MIL-STD-1553B, SpaceWire, CAN RS422) 17 th of September 2009 NoC round table 5

6 Reference Architectures: Modular Data Systems Already in the 90s, it appeared clearly that a generic interface would be very useful on-board spacecraft, in order to ease the interconnection of: Sensors Mass-memories Processing units, and Downlink telemetry sub-systems. High speed Serial links in contrast to parallel interfaces have been selected due to their potential of constituting an homogeneous solution to interconnect components, board and units. They allowed as well to define a reference architecture with native modularity and scalability. 17 th of September 2009 NoC round table 6

7 Reference Architectures: Modular Payload Data Handling System Architecture used by ESA as a reference for medium-range Data Handling Systems and the definition SpaceWire devices (SpW Router, SpW RTC, SMCS-SpW, ) Modules based on Hi-Rel components Modules based on COTS Optional Module Instrument Memory Module Memory banks Context Saving Memory Memory banks Data Compression Module Instrument HIVAC I/O Module SpW Router SpW Router Telemetry Formatter /Encryption Module Transmitter CCD/APS Camera RTC Control Processor module Dedicated Processor module DSP Processor module CAN bus Complex Instrument Instrument optional DPU Spacecraft control bus SpaceWire links Control bus/line 17 th of September 2009 NoC round table 7

8 Backplane PCB - front 17 th of September 2009 NoC round table 8

9 Backplane PCB - back 17 th of September 2009 NoC round table 9

10 Challenges of space VLSIs Make best use of DSM technologies, providing Higher speed Allow to integrate complex systems on one chip Bound development times Trend towards multi-year (2/3 5/7) development periods Define and validate new development paradigms SoCs based on IP cores Foster reuse of existing designs Architectural design and HW/SW co-design. While keeping reliability and availability figures highest 17 th of September 2009 NoC round table 10

11 Challenges of space SoCs SoC-ASIC developments: complex design flow ASIC FOUNDRY Wafer tests, die probe Masks, Si wafers manufacture Foundry Proto tests Dicing, packaging Tapeout Database bases Customer Proto tests System requirements Tested ASIC prototypes ASIC specs Feasibility, development plan More foundry feasibility Architectural design VHDL coding Functional simulations FPGA verification Synthesis => ASIC gates ASIC DESIGN HOUSE Post-layout Verification: simulations Structured Test func, time layout 17 th (scan, bist, JTAG) of September 2009 NoC round table 11