High Level Synthesis Re-usable model of AMBA AXI4 communication protocol for HLS based design flow developed using SystemC Synthesis subset
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1 High Level Synthesis Re-usable model of AMBA 4 communication protocol for HLS based design flow developed using Synthesis subset NASCUG, San Francisco, USA (June, 2014) Presenter Dinesh Malhotra, CircuitSutra AUTHORS Amaranatha reddy, PVS Phaneendra, Umesh Sisodia (CircuitSutra) High Level Synthesis - Overview Raising the abstraction of chip design above RTL Design Entry AMBA 4 High Level Synthesis Quick Start Package HLS-QSP From CircuitSutra Constraints Tech Lib HLS Tool Cadence Cynthesizer Low Power FPGA Xilinx RTL Less Area FPGA Altera High Perf ASIC Same Model Can be used to generate RTL for different requirements RTL 90 nm 45 nm 22 nm 1 Presented during DAC 51 in San Francisco, CA Page 1 of 7
2 4 Overview 4 (Advanced extensible ) is latest of AMBA(Advanced Microcontroller Bus Architecture) bus protocols that is useful for on-chip bus designs in SoCs channels channels Module 1 Write Address Write Data Write Response Read Address Read Data Bus / Interconnect Module 1 Module 2 Module 2 HLS-QSP for Module 4 b_transport (trans) Sample Bus Module 4 Decoder APIs Memory bus_monitor_slave() Reusable s Configurable for address width, data width Configurable for abstraction: PIN / TLM Can be used to design compliant IP Sample bus For demo and testing of sockets instantiation & binding In Module : axi_master_socket<...> In Module : axi_slave_socket<...> axi_master_port; axi_slave_port; Add both sockets to Axi bus : axi_bus->add_master(_module->axi_master_port); axi_bus->add_slave(_module->axi_slave_port); Initiating transaction in ::_payload trans; trans.set_streaming_width(1); trans.set_command(::_read_command); trans.set_address(read_addr); trans.set_data_length(16*4); trans.set_data_ptr((unsigned char*)data); found=axi_master_port.b_transport(trans); 2 Presented during DAC 51 in San Francisco, CA Page 2 of 7
3 Design FIFO1 THREADS WA (cynw_p2p_direct_out) b_transport() Mem_FIFO1 write resp signal WD (cynw_p2p_direct_out) WR (cynw_p2p_direct_in) FIFO2 RA (cynw_p2p_direct_out) Mem_FIFO2 read resp signal RD (cynw_p2p_direct_in) Design WA (cynw_p2p_direct_out) get() WD (cynw_p2p_direct_out) WR (cynw_p2p_direct_in) get() put() bus_monitor _slave Write data to decoder of slave module RA (cynw_p2p_direct_out) RD (cynw_p2p_direct_in) get() put() Read data from decoder of slave module 3 Presented during DAC 51 in San Francisco, CA Page 3 of 7
4 Features Supported protocol features All burst types INCR, FIXED,WRAP Narrow transfers Unaligned transfers Setting strobes at master, checking strobes at slave during write Variable data transfer size (AxSIZE) Multiple outstanding transactions at slave, master Features not Supported ACE protocol signals: AxCACHE, AxUSER, AxPROT,AxLOCK Verification Setup DMA Sample Bus Memory 1 Same test suite used for: 4 4 design ( Simulator) Resultant Verilog design (Verilator + simulator) Source 4 4 Sink Debug Memory Presented during DAC 51 in San Francisco, CA Page 4 of 7
5 Design productivity Benefits Less amount of code Less efforts for development & maintenance Less probability of bugs Same code can be used to generate the RTL for different applications Verification productivity Bulk of functional verification can be done at behavioral level Faster simulation results in faster verification Less code results in fewer bugs related to functionality HLS Quick Start Package (QSP) for AMBA Re-usable master & slave sockets for designing compliant IP blocks Designers focus on functionality of their IP. Need not worry about implementing complex protocol IP designs are protocol independent. sockets can be replaced by the sockets of other bus (eg.. OCP-IP) Smaller Code Size Lines of code method_processing=synthesize --sched_aggressive_2=off --method_processing=translate --sched_aggressive_2=off --method_processing=synthesize --sched_aggressive_2=on --method_processing=translate --sched_aggressive_2=on Verilog More than 5x code size reduction Further benefits can be realized by using same code to generate RTL for different applications 5 Presented during DAC 51 in San Francisco, CA Page 5 of 7
6 Faster Simulation 500 Simulation Time (Seconds) Run1 Run2 Run3 Run4 Verilog More than 4x faster simulation Future Roadmap Integrate with UVM based verification flow Optimization Optimize the code further for specific applications HLS-QSP Add new portfolio of re-usable HLS models and modeling infrastructure OCP-IP bus sockets Hardware accelerators for widely used algorithms 6 Presented during DAC 51 in San Francisco, CA Page 6 of 7
7 Transforming Semiconductors Transforming Electronics Thank You Presented during DAC 51 in San Francisco, CA Page 7 of 7 7
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