The Architects View Framework: A Modeling Environment for Architectural Exploration and HW/SW Partitioning

Transcription

1 1 The Architects View Framework: A Modeling Environment for Architectural Exploration and HW/SW Partitioning Tim Kogel European SystemC User Group Meeting,

2 Outline 2 Transaction Level Modeling Overview Problem Statement MP-SoC Design Flow Terminology and Standardization: The 4 TLM Views Architects View Framework Virtual Architecture Mapping technology Tooling

3 MP-SoC Platform Design Challenge Application Task 7 3 Task 1 Task 2 Task 3 Task 4 Task 5 Task 6 Task 8 Memory Spatial & Temporal Mapping NoC IP IP mc IP Multi-Processor System-on-Chip Mem IP

4 Multi-level level SoC Design System application design domain specific algorithm design esw design Magarshak/Paulin, DAC03 4 MP-SoC platform design specification, assembly and configuration of existing IP spatial & temporal mapping of application to MP-SoC platform esw verification and profiling reference model for HW verification TLM domain High-level IP block design embedded Processors: RISC, DSP, ASIPs interconnect: busses, NoC standard I/O: PCI, SPIx, DDR/QDR, Technology & basic IP memories heterogeneous technologies: edram, eflash, RF,...

5 TLM based MP-SoC design flow 5 Application/Algorithm Functional View HW mapping SW Software Programmers View extraction Platform Architects View refinement SW Implementation Verification View refinement

6 TLM Standardization Matrix 6 OSCI TLM standard bidirectional blocking Transport (SW centric) unidirectional non/blocking FIFO (HW centric) functional FV TL3 timed PV AV TL2 cycle accurate VV TL1 CoWare Classification OCP-IP

7 Outline 7 Transaction Level Modeling Overview Problem Statement MP-SoC Design Flow Terminology and Standardization Architects View Framework Workflow Virtual Architecture Mapping technology Tooling

8 Architects View Framework 8 User Models Architecture Models simulation results configuration files.xml SystemC Simulation

9 Modular Architects View Framework Task Task2 Task Task1 synchronization debugging, analysis configuration Memory Memory 9 Task Taskn AV Simulator Interconnect Structure Definition Memory Memory Master Modules P2P model Bus model Router model Slave Modules STBus CoreConnect AMBA2.0 Æthereal

10 Implicit Timing Annotation 10 Initiator Network Target sendreq(t, D t delay ) D t delay reqstart getreq(t) D t pending sendreq(t) reqstart getreq(t, D t init ) reqend acceptreq() D t transfer D t init reqend

11 Virtual Processing Unit 11 Task 1 init busy request response busy request VPU swap swap Processor Memory Memory init busy finish Memory Memory swap NoC init busy Task 2 init busy request response busy request swap swap finish

12 AV Framework Libraries 12 Component Toolbox (CTB) Simulation Toolbox (STB) User Models Stimuli Stimuli Memory Cache Network Interface Bridge Task A Task B Architects View API Virtual Processing Unit Architects View API On-Chip Communication

13 AV based Architecture Exploration and Partitioning 13 Task TaskA1 A1 Task TaskA2 A2 Task TaskA3 A3 Task TaskB1 B1 Task TaskB2 B2 VPU A local scheduler VPU B local scheduler memory memory cache cache Communication Architecture global Memory global Memory Memory Memory global scheduler

14 Message Sequence Chart Trace 14 SystemC modules Time Communication Events

15 ConvergenSC Analysis Memory Reads/Writes 15 port/memory analysis based on PlatformCreator address map bus analysis all NoC nodes instrumented trace views statistical views Contention Transaction Counts

16 Summary Architects View Value Proposition high abstraction level simulation speed, modeling efficiency generic synchronization protocol, declarative xml based configuration modularity, flexibility comprehensive set of debugging and analysis tools scales to upcoming complexity challenges Network-on on-chip Multi-Processor SoC OSCI TLM and OCP TL2 standard compliant Part of CoWare ConvergenSC Family leverage Platform Creator, debugging, analysis, and fast simulator seamless refinement to cycle-level level TLM and RTL IP library: processors, buses 16

17 17 Thank You!