Place Your Logo Here. K. Charles Janac

Transcription

1 Place Your Logo Here K. Charles Janac President and CEO

2 Arteris is the Leading Network on Chip IP Provider Multiple Traffic Classes Low Low cost cost Control Control CPU DSP DMA Multiple Interconnect Types Memory Scheduler Memory Scheduler CPU DSP DMA Initiator Initiator Initiator Initiator Initiator CPU CPU Local Local Local Local High High throughput throughput Latency Latency critical critical CPU DSP DMA Top level CPU DSP DMA Target Target Target Target Target Target Memory scheduler Memory scheduler Local Local Local Local Low Low cost cost Control Control Peripheral Peripheral SubSystem SoC Interconnect Type Arteris Product Peripheral interconnect: Arteris Peripheral DAC Announcement Top level interconnect: Arteris Solution IP(Block) level interconnect: Arteris Solution Multiple Dies in SIP: InterChip Link

3 Arteris s Enable Better Performing SoCs Technology Advantages Show up as Improved User Experience Separation of IP & IP Communications Higher SoC Quality Routing friendly layout Less then half global wires Low power <1mW idle power for 500K gate IP at 65nm LP High speed up to 750Mhz using 65nm TSMC Library High bandwidth links scalable from 8 to 1024 bits Deliver better SoCs faster, with higher margins & lower risk Rapid design & verification for 105 IP, 90nm SoC in < 1 week IP reuse & Automated generation accelerate SoC schedules Multiple services such as QoS, Security, Power Mgmt & GALS are available Lowering SoC Unit and project costs by millions per project

4 Arteris IP Elements Lego Box Approach A instance consists of parameterizable IP elements, Enhances SoC Scalalability, low power and high performance Network Interfaces AXI TM,AHB TM, APB TM,OCP TM, proprietary Transport Switches, FIFOs, Converters, Security, etc. QoS Bandwidth limiter and regulator Memory scheduler Domain Management Clock/Voltage/Power domains support Software configuration Low cost Service Network Debug On-Chip performance monitoring & debug Customer specific elements

5 Arteris Tools Accelerate SoC Delivery ARTERIS explorer IP ARTERIS library Application Requirements ARTERIS compiler IP ARTERIS RTL library RTL, Scripts, Test bench x x x x x ARTERIS Generated Instance ARTERIS verifier Arteris VM M top level RTL to GDSII Synopsys Verification IP Scenario: Connectivity Thorough Random Register Map Latency Throughput Power User Bit Silicon Debug Statistic s Colle ctor Sideband Config R stn Stimulus generator SNPS VIP master O CP / AXI / AHB / APB Arteris VIP Pwr Ctrl / P wr Disc C lk En / R s tn / In put Manager Dispatches Arteris & User tests Callback Helper VIP Monitor Functions Functions OCP / AXI / AHB / AP B Scoreboard VIP Monitor Power Power Assertions AIP Arteris bench e nvironm ent & Arteris scena rios Helper Functions: Reset Config Access Init# to Target# Access Target Conf: Err/F ast/rnd In stru m e n te d N o C Assertion IP VIP Monitor O CP / A XI / AH B / APB Response VIP Monitor generator Power SNPS VIP slave O C P / AX I / A H B / A PB AIP Arteris VIP Pw r D is c / R s tn / O utp ut Clk Gen

6 Arteris Peripheral Solution Application Connection of lower-performance peripheral IP cores Timers, Interrupt controller I2C GPIO UART USB 1.1 I2S Connection of IP register interfaces Programming ports of IP interfaces

7 Peripheral Interconnect Issues and Requirements Large number of interface ports Tens to hundreds of interface ports Interface ports are physically distributed ib t d over SoC Peripheral IPs are distributed around pad-ring IP Programming ports are distributed over SoC area Latency and throughput requirements Not as stringent as Main Interconnect, but Latency and throughput affect: Boot time Interrupt service routines performance SoC state reprogramming High performance eliminates need for shadow registers

8 Arteris Peripheral Solution Features Comprehensive Native IP Protocol Support -enabled Flexible Topology Concurrency Embedded AHB/APB busses User-defined pipelining pp Asynchronous and divided clocks Error Reporting and Error Logging Security/Firewall features

9 Arteris P- TM Addresses the need for low cost based interconnect Fewest wires Fewest gates Ring topology Optimized for few initiators and many target architectures Cuts design time, wire congestion and die area Completes Arteris Product Line

10 Measuring our Success by SoC Tapeouts R&D fully dedicated to technology deployment and evolution Continued innovation and roadmap Growing Patent portfolio, 200 man years of investment One of the largest and most experienced teams dedicated to interconnect technology development In-depth technical collaboration with SoC makers Many generic customer driven features implemented Ability to add customer unique features Arteris, the best way to Integrate Complex SoCs

11 Thank you Explore more about Arteris Inc. and related IP at ChipEstimate.com Use the Arteris IP to plan your next chip! Please stay and talk with Shawn Hurt, Senior Application Engineer 11