PADded Cache: A New Fault-Tolerance Technique for Cache Memories

Transcription

1 PADded Cache: A New Fault-Tolerance Technique for Cache Memorie Philip P. Shirvani and Edward J. McClukey Center for eliable Computing, Stanford Univerity Abtract Thi paper preent a new fault-tolerance technique for cache memorie. Current fault-tolerance technique for cache are limited either by the number of fault that can be tolerated or by the rapid degradation of performance a the number of fault increae. In thi paper, we preent a new technique that overcome thee two problem. Thi technique ue a pecial Programmable Addre Decoder (PAD) to diable faulty block and to re-map their reference to healthy block. Simulation reult how that the performance degradation of direct-mapped cache with PAD i maller than the previou technique. However, for et-aociative cache, the overhead of PAD i primarily advantageou if a relatively large number of fault i to be tolerated. The area overhead wa etimated at about 10% of the overall cache area for a hypothetical deign and i expected to be le for actual deign. The acce time overhead i negligible. 1. Introduction High level of reliability, availability and erviceability (AS) are key deign goal of high-end computer ytem. High availability i achieved by uing high quality component (fault avoidance) and deign technique that allow on-line detection and recovery from hard and oft failure (fault tolerance). Minimizing the downtime i very important in ytem with high availability. When continuou operation i required, an on-line repair mechanim diable or replace a faulty component without human interaction and thereby eliminate the downtime for ervice. On-line repair i alo required for ytem that are not acceible for repair, a in pace application [1]. In ome fault-tolerance technique, the ytem continue it operation at a poibly lower performance level (graceful degradation) under the preence of fault. In thi paper, we preent a new technique for tolerating permanent fault in cache memorie during their lifetime. All high performance microproceor ue a hierarchy of cache memorie to hide the low acce to the main memory [2]. With each new generation of integrated circuit (IC) technology, feature ize hrink, creating room for more functionality on one chip. We ee a fat growth in the amount of cache that deigner integrate into a microproceor to gain higher performance. Hence, cache occupy a ubtantial area of a microproceor chip and contain a high percentage of the total number of tranitor in the chip. Conequently, the reliability of the cache ha a big impact on the overall chip reliability. The new fault-tolerance technique preented in thi paper addree thi iue by exploiting the architectural feature of cache. We propoe a reconfiguration technique that can keep the cache operational at a high level of performance (low mi rate) even in the preence of a large number of fault. Our technique provide a way to do the reconfiguration to iolate the faulty part; it aume the ytem i equipped with appropriate error detection and error recovery mechanim. In Sec. 2, we review the previou work on faulttolerance technique for memorie and cache. In Sec. 3, we preent the PADded cache Ñ cache with Programmable Addre Decoder. To evaluate the performance of PADded cache, we carried out imulation. The reult are explained in Sec. 4. The hardware overhead of PADded cache i etimated in Sec. 5. We dicu ome implementation iue and the advantage of our technique in Sec. 6 and conclude in Sec Previou Work Cache are ued to bridge the peed gap between microproceor and main memory. Without them, the proceor can till operate correctly but at a ubtantially lower performance. Many architecture are deigned uch that the proceor can operate without a cache under certain circumtance. Therefore, the obviou olution to a faulty cache i to totally diable it. In et-aociative cache, a le extreme olution i to diable one unit (way) of the cache [3]. Mot of the tranitor in a cache are in memory cell. Hence, the probability that a given defect i in a memory cell (a bit in the data or tag field) i higher than the probability of it being in the logic circuitry. If the fault i in a data or tag bit, only the block containing that bit need to be diabled. For marking a cache block a faulty, an extra bit can be added to the et of flag bit aociated with each block [4]. If thi bit i zero, the block i non-faulty and will do it normal function. If the bit i one, it will indicate that the block i faulty. In cae of a direct-mapped cache, if the faulty block i acceed, it will alway caue a cache mi. In cae of a etaociative cache, the aociativity of the et that include that block i reduced by one. In thi paper, we refer to

2 thi extra bit a the FT-bit (fault-tolerance bit). Other name ued in literature are: availability bit [5], purge bit [6], and the econd valid bit [7]. Adding the FT-bit wa initially uggeted for yield enhancement [4]. Yield model have been derived in [8] for proceor with partially good on-chip cacheñchip with up to faulty cache block. It i hown that maximum yield can be achieved with mall. Diabling faulty block i done even when the cache i protected by ingle-error correcting, double-error detecting (SEC-DED) code [9]. For example, Cache Line Delete (CLD) i a elf-diagnotic feature in high-end IBMä proceor cache that automatically detect and delete the cache block with permanent fault [10]. A detailed invetigation of the effect of faulty cache block on mi rate wa firt preented in [5] and then extended in [7]. Cache block were randomly choen and marked a faulty. It wa hown that for direct-mapped cache, the mi rate increae linearly with the fraction of faulty block. For a et-aociative cache, the increae i low for a few fault and become fater a the number of fault increae. eplacement technique, uch a extra row and column, are alo ued in cache for yield enhancement [11] and for tolerating lifetime failure [9] [12]. With replacement technique, there i no performance lo in cache with fault. However, the number of extra reource limit the number of fault that can be tolerated uing thee technique. A replacement cheme called the Memory eliability Enhancement Peripheral (MEP) i preented in [13]. The idea i to have a et of pare word each of which can replace any faulty word in the memory. A technique imilar to MEP i preented for cache in [14]. A very mall fully aociative pare cache i added to a direct-mapped cache that erve a a pare for the diabled faulty block. The difference between thi technique and MEP i that there can be more faulty block than there are pare block. The imulation reult in [14] how that one or two pare block are ufficient to avoid mot of the extra mie caued by a few (le than 5%) faulty block. However, a the number of fault increae, a few pare block i not very effective. Cache memorie have an inherent redundancy that can be exploited to increae thi limit. 3. PADded Cache In thi ection, we preent a new technique that ha much le performance lo in cache a the number of faulty block increae. Figure 3.1 how a imple block diagram of a direct-mapped cache. The mapping of block addree to the block in the cache i done by a decoder which i hown a a dark rectangle in the diagram. We modify thi decoder to make it programmable uch that it can implement different mapping function uitable to our technique. No pare block are added for tolerating fault. Intead, we exploit the exiting non-faulty block a ubtitute for the faulty one. Block Addre Tag Index D E C O D E Block Offet V Tag Data =? Mux Hit / Mi Data Out Figure 3.1 Block diagram of a direct-mapped cache. a 2 a 2 T6 T7 a 1 T4 T5 a 0 a 0 T0 T1 T2 T3 Figure 3.2 Circuit diagram of a imple decoder. Figure 3.2 how part of the lat three tage of a imple decoder. Thi type of decoder may not be ued in peed-critical circuit. However, it i eaier to illutrate our re-mapping procedure uing thi decoder. The ame procedure applie to decoder that ue gate intead of pa tranitor a will be hown later. In Fig. 3.2, each block i output i a word line that elect a block in the cache. For example, when a 2 =000, i elected, when a 2 =001, i elected, and o forth. Now aume that i faulty. We modify the control input of tranitor T0 and T1 uch that, when i marked faulty, T0 i alway off and T1 i alway on. That i, all the reference to are re-mapped to. Therefore, the addree that map to are till cacheable and will only uffer from conflict mie with. Since one addre bit information i lot due to thi re-mapping, one bit i augmented to the tag bit to ditinguih the addree that may be mapped to the ame block when fault are preent. Similarly, if i faulty, T0 will be alway on, T1 will be alway off, and all the reference to are re-mapped to. Figure 3.3 how the modified decoder. Similar to the FT-bit, an extra bit i added to each block to mark it a faulty or non-faulty (the f i Õ in Fig. 3.3). Thee flip-flop can be connected a a hift regiter and loaded uing pecial intruction. The control input of the pa tranitor are modified a hown. For example, the control for T0 i changed from to f 0 + f 1. Therefore, T0 i alway on if i faulty (f 0 =0, f 1 =1) and i alway off if i faulty (f 0 =1, f 1 =0).

3 a 2 a 2 T6 T7 a 1 T4 T5 f 0 a 0 + f 1 T0 f 1 + f 0 T1 f 2 a 0 + f 3 T2 f 3 + f 2 T3 Figure 3.3 A imple Programmable Addre Decoder (PAD). We call two block adjacent if their addree differ only in the addre bit that i decoded lat. For example, in Fig. 3.2, and are adjacent and and are adjacent. Depending on the reliability requirement of the application, the probability of adjacent faulty block may be low enough that the programmability i done only for the lat level a hown in Fig However, the cheme can be applied to multiple level to tolerate adjacent faulty block and to meet the deired level of fault tolerance. For example, the control of tranitor T4 can be changed to g 0 + g 1, where g 0 = f 0 f 1 and g 1 = f 2 f 3. In a cae where both block 2 and are faulty (g 0 =0 and g 1 =1), T4 and T5 will alway be on and off, repectively. Therefore, the reference to and 3 will be re-mapped to and 1, repectively. In thi cae, the tag portion ha two extra bit. There are two point to notice here. In the lat example, tranitor T2 and T3 will be alway on. However, thi will not caue any problem becaue T5 will be off and hence and 3 will never be elected. Second, if one of the or 1 i alo faulty, the correponding f i will be 1 and all the reference to the 3 faulty block will be re-mapped to the one healthy block. The ame procedure can be applied to all level. Thi technique can be imilarly applied to a etaociative cache. Typically, in a phyical deign, there i a eparate memory array for each way of a et-aociative cache. The decoder can be hared between the array, or it may be duplicated due to floor-planning or circuit iue. For example, conider a 4-way et-aociative cache with one decoder for each way. Our technique can be independently applied to each decoder, i.e., re-mapping in one array will not affect mapping of the other array. Figure 3.4(a) illutrate a cae where a et ha a faulty block Ñ we call thi et the faulty et. With a PAD, the faulty block i mapped to a non-faulty block. We call the et that contain thi non-faulty block, the congruent et of the faulty et (in cae of a direct-mapped cache, each et ha only one block). Becaue the re-mapping doe not affect the other block in the et, one healthy block of the congruent et will be hared between the faulty et and the congruent et and the ret of the block are ued a before. If there are two decoder, one for each pair of array, the f 0 f 1 f 2 f 3 healthy block that hare a decoder with the faulty block will alo be marked faulty and two block will be hared between the two et. Thi i illutrated in Fig. 3.4(b). Faulty Shared Unued Faulty Shared Shared Faulty Set Congruent Set Faulty Set Congruent Set (a) (b) Figure 3.4 Block haring between a faulty et and it congruent et in a 4-way et-aociative cache: (a) with 4 decoder, (b) with 2 decoder. The conflict mie that occur between a et and it congruent et can be reduced by pecial ordering of the addre bit in the decoder. Cache exploit the patial locality of the memory accee. If we make a et and it congruent et far apart in the addre pace, there will be le conflict due thi patial locality. Since the order of the input to the decoder i not important in the function of the cache, we ue the index bit in the revere order. That i, the mot ignificant bit (mb) of the array index i connected to the leat ignificant input bit (lb) of the decoder. The imulation reult how that thi deign ha better performance than a direct connection (normal order). A mentioned before, the tag portion of the array i widened by one bit for each level of programmability. Thee bit will have contant value when there i no faulty block and will tart changing when the block become a ubtitute for a faulty block. Notice that thee tag bit will tore the ame bit that are ued for indexing the cache array. For example, if the cache i virtuallyindexed phyically-tagged, the normal tag bit will contain phyical addree and the extra tag bit will contain virtual addree. The tag comparator i alo widened by the ame number of bit. 4. Simulation eult In thi ection, we dicu our imulation etup for evaluating the performance of PADded cache and preent the reult. Trace-driven imulation i the mot popular method for evaluating the performance of cache memorie. We ued thi method to compare the mi rate of cache with two fault-tolerance technique, the imple block deletion uing the FT-bit, and our new PAD technique. In the ret of the paper, we refer to the firt technique a FTB. We modified the Dinero IV cache imulator ([15]) to imulate thee two technique. We ued different value for the following parameter: cache ize (2, 4, 8, 16, and 32KB), block ize (8, 16 and 32 byte) and aociativity (1, 2 and 4). The imulated cache are write-through, allocate-on-write-mi, with no prefetching and no ub-blocking, and ue the LU replacement protocol. We aume that the decoder are replicated for each way of the cache, and they are programmable for all level. The fault are injected at random location and mi rate are calculated for different number of faulty block. Since the location of the fault affect the mi rate, each imulation wa run

4 everal time and the minimum, maximum and average mi rate were recorded. We collected many et of trace for our imulation. Some of them are: the ATUM trace [16], trace from SPEC92 and SPEC95 benchmark, and the IBS trace (alo called the Monter trace) [17]. The total number of reference in each trace vary from about 300,000 for the ATUM trace, up to more than a billion for the IBS trace. The mi rate for one et of trace, e.g., the ATUM trace, i calculated by taking the weighted average of the mi rate of each trace in the et Ñ weighted by the number of reference in each trace. In thi paper, we preent a election of the imulation reult. More reult and detail are preented in [18]. The average mi rate of the ATUM trace i hown in Fig. 4.1(a) for both the FTB and PAD technique. Thi graph how the reult for an 8KB cache with 16-byte block and with aociativitie: direct-mapped (DM), 2- way et-aociative (SA2), and 4-way et-aociative (SA4). The mi rate of PADded cache tay relatively flat and increae lowly toward the end. Simulation of cache with different ize how that when half of the block are faulty, the mi rate of a PADded cache i almot the ame a a healthy cache of half the ize. Thi indicate that in PADded cache, the full capacity of healthy block i utilized and the performance decreae with almot minimum poible degradation. Figure 4.1(b) how the lower left corner of Fig. 4.1(a). Notice that for a mall percentage of faulty block, both technique perform equally well for the etaociative cache. Another advantage of our technique i hown in Fig. 4.1(c). Thi figure how the minimum and maximum mi rate of the ATUM trace for different fault location, in a direct-mapped cache. The mi rate of FTB ha a noticeably big range (a wa hown in [7]) while the mi rate of PAD remain almot unchanged. Thi how that PADded cache are very inenitive to the location of fault. Notice that we did not do an exhautive earch for the minimum and maximum mi rate; thee are the range oberved in our imulation. 5. Hardware Overhead In thi ection, we look at the circuit implementation of PADded cache to etimate the area and delay overhead of our technique. A typical decoder for a cache i implemented uing everal pre-decode tage and logic gate. Let u conider a mall decoder for the ake of implicity. For example, a 4-to-16 bit decoder i hown in Fig To emphaize the importance of uing the mb of the addre bit for the lat tage of decode, the addre bit are ued in the revere order in thi example (a 3 a 2, i the real index addre with a 3 a the mb). Similar to the decoder in Sec. 3, we intercept the addre bit to diable or enable the output of the gate. The modified decoder i hown in Fig The three input gate F i, G i and H i implement function imilar to thoe in Fig. 3.3: M i a t e 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 20% M i 15% 10% a t e 5% M i a t e Cache Size=8KB, Block Size=16byte FTB, DM FTB, SA2 FTB, SA4 PAD, DM PAD, SA2 PAD, SA4 0% 0.0% 12.5% 25.0% 37.5% 50.0% 62.5% 75.0% 87.5% 100.0% Percentage of Faulty Block 25% (a) Cache Size=8KB, Block Size=16byte FTB, DM FTB, SA2 FTB, SA4 PAD, DM PAD, SA2 PAD, SA4 0% 0.0% 3.1% 6.3% 9.4% 12.5% Percentage of Faulty Block 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% (b) Cache Size=8KB, Block Size=16byte FTB, DM PAD, DM 0% 0.0% 12.5% 25.0% 37.5% 50.0% 62.5% 75.0% 87.5% 100.0% Percentage of Faulty Block (c) Figure 4.1 Average mi rate of the ATUM trace: (a) different aociativitie, (b) lower left corner of Fig. 4.1(a), (c) min. and max. mi rate for a DM cache. F 0 = f 0 a 3 + f 1, F 1 = f 1 a 3 + f 0, F 2 = f 2 a 3 + f 3, F 3 = f 3 a 3 + f 2, G 0 = g 0 a 2 + g 1, G 1 = g 1 a 2 + g 0, H 0 = h 0 + h 1, etc.

5 where g 0 = f 0 f 1, g 1 = f 2 f 3, h 0 = g 0 g 1 and h 1 = g 2 g 3. If only one level of programmability i required, then only the F i function would be required. Notice that the f i, g i, h i and their complement change only during reconfiguration and are contant the ret of the time. Therefore, the correponding gate (NAND and inverter) can ue minimum ize tranitor. Furthermore, thee contant value form two of the three input of the function F i, G i and H i. The gate for F i, G i and H i add one extra logic tage to the decoder and are in the critical path for acceing the cache. To reduce the gate delay of thee AOI (AND-O-Invert) function, the tranitor that are connected to the contant input are made 3 to 4 time the ize of the tranitor connected to the variable input. The delay overhead of adding thee gate can be made negligible by chooing proper ize for the tranitor in the decoding tage. Since the number of tag bit increae in PAD, the width of the tag comparator alo increae. However, the delay of the comparator will increae by at mot one gate delay. Therefore, the delay overhead of adding PAD to a cache i cloe to one gate delay of an inverter driving an identical inverter. a 0 a 2 a 2 a 3 a 3 Predecode a 1 a 0 a a 1 0 a 1 Figure 5.1 A decoder implemented by logic gate. J 1 H 3 H 2 J 0 H 1 H 0 a 2 a 2 a 3 a 3 F 0 G 0 F 1 G 1 F 2 F 3 Figure 5.2 Modified verion of the decoder in Fig. 5.1 for PAD. For example, let u conider 6KB direct-mapped cache with 16 byte block. A typical decoder for thi cache take about 5% of the total cache area. We f 0 f 1 f 2 f 3 etimated that the decoder would grow by 60% after modification for PAD. That i 3% increae in total cache area. With a 32-bit addre, the tag will be 18 bit wide (aume all addree are phyical). Conidering two bit for flag, each block will be =148 bit long. For a PADded cache with full programmability, 10 bit will be added to each block, which i a 7% increae. The FT-bit will roughly take another extr%. Therefore, the total area overhead i 3+7+1=11%. Mot of thi overhead i in the extra tag bit. Therefore, a deigner may decide to make jut a few of the level programmable. Another way to reduce the area overhead, i to make the decoder programmable tarting at the decoding level before the lat. An FT-bit i added for each pair of block, i.e., each two block are diabled together, regardle of whether they are both faulty or only one i faulty. A can be een, our technique i very flexible and the overhead can be adjuted according to the reliability requirement. In a cache with multiple independent port, there are a many decoder a there are port. Thee decoder hould provide the exact ame mapping in the preence of fault. Therefore, the FT-bit and the f i (g i, etc.) function can be hared between the decoder and conequently, the overall area overhead will be le for thi type of cache. 6. Dicuion In thi ection, we dicu ome implementation iue and other advantage of our technique over FTB. The advantage of FTB over PAD i low hardware overhead (we donõt have overhead number for FTB and other technique to do a better comparion). Adding an extra bit to each cache block will impoe a relatively mall area overhead. In ome cache, thi extra phyical bit can be avoided by uing an unued combination of the available flag bit in cache. For example, in a write-back cache, the combination dirty=1 and valid=0 can be ued to mark a block a faulty. The FTB technique relie on the availability of a path to bypa the cache when a faulty et i being acceed. Some cache organization require block to be loaded into the cache before they are read by the CPU [4]. With FTB, a data that reide in an addre that i mapped to a et with all faulty block, doe not have a place to go in the cache and ha to bypa the cache. The ame problem exit for write-back cache where tore intruction write to the data cache and the new data i written into the memory when the block i replaced. For a faulty et, the tore ha to be executed in a write-through fahion. Similar problem exit for cache with allocate-on-writemi policy. Therefore, hardware hould be added to make the reference to the faulty et behave like reference to non-cacheable addree. However, with PAD, the data i alway cacheable a long a there i a non-faulty block in the cache, o there i no need for extra hardware.

6 7. Concluion In thi paper, a novel fault-tolerance technique for cache i introduced. Thi technique ue graceful degradation to tolerate permanent fault in cache block. It can be ued for on-line repair in ytem for high reliability and availability. The main advantage of our technique i it low degradation of performance a the number of fault increae. Thi increae the lifetime of a chip and ubequently, the availability of a ytem, becaue there will be le downtime for component replacement. The PAD technique can alo be ued for yield enhancement. However, a mentioned earlier, the analyi in [8] how that maximum yield can be achieved by accepting a few faulty block. The FTB technique can provide acceptable performance for a few faulty block. Therefore, if yield enhancement i the goal, FTB i probably the better choice. The PAD technique provide a better olution when: the total number of faulty block that have to be tolerated (i.e., the manufacturing fault and the fault that occur during the lifetime of the cache) i more than a mall percentage of total number of block, utaining the peak performance i very critical, or the performance hould be predictable. The lat cae i jutified by the fact that FTB ha a big range for the mi rate depending on the location of the faulty block, but PAD ha a very mall range. In real-time application, the ytem ha to execute a pecified program within a certain amount of time, i.e., the performance ha to be predictable to a pecified level. A fault-tolerant cache that can maintain it etimated mi rate for that pecified program under different condition, will be the better choice. We etimated the area overhead of PAD for a hypothetical deign at about 10%; the acce time overhead wa negligible. However, the area overhead depend on the parameter of the cache, the level of programmability in the decoder, and layout optimization. Therefore, we expect the area overhead to be le for real deign. Our technique provide a ingle olution for all type of cache with different policie. No extra hardware ha to be added for write-back or allocate-on-write-mi cache. Application of PAD for cache that are ued in multi-level cache ytem and in multi-proceor ytem i an area for future reearch. Acknowledgment Thi work wa upported in part by the Ballitic Miile Defene Organization, Innovative Science and Technology (BMDO/IST) Directorate and adminitered through the Department of the Navy, Office of Naval eearch under Grant No. N J-1782 and N The author wih to thank Nirmal Saxena, Samy Makar, Subhaih Mitra, Mehrdad Hehami and David Harri for their review and valuable comment. The author alo thank Timothy Slegel for helpful dicuion. eference [1] Siewiorek, D.P., and.s. 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