Exercise 1: Cache Architecture I

Size: px

Start display at page:

Download "Exercise 1: Cache Architecture I"

Egbert Chambers
5 years ago
Views:

Exercise 1: Cache Architecture I Assuming a cache miss on line 19 of the code. a. What could a system designer implement to reduce the number of lost cycles?

1 Exercise 1: Cache Architecture I Assuming a cache miss on line 19 of the code. a. What could a system designer implement to reduce the number of lost cycles? You chose this processor system because it features an open cache architecture, as opposed to a general purpose processor, like the ones found in a PC. b. What could your cache system look like if you want a miss rate of zero? Assume a permanent input stream of new packets. Exercises 6 - Microprocessors Seite 1

2 Code 1: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 2: ; Subroutine: Correct New Packet ; 3: ; Parameters: Packet Source address: esi ; 4: ; Destination address: edi ; 5: ; Registers: CX (16-bit), eax, MM0-MM6 (32-bit each) ; 6: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 7: 8: New_Packet: 9: MOV CX <- 4 ; Loop counter, a packet has 4x4 words 10: Inner_Loop: 11: 12: ; Read packet and check words from memory 13: MOVs MM0 <- [esi] ; Get 1st word and increment 14: MOVs MM1 <- [esi] ; source pointer 15: MOVs MM2 <- [esi] ; Get 3rd word 16: MOVs MM3 <- [esi] ; Get 4th word 17: MOVs MM4 <- [esi] ; Get 1st check word 18: MOVs MM5 <- [esi] ; Get 2nd check word 19: MOVs MM6 <- [esi] ; Get 3rd check word 20: 21: ; Re-construct parity bits 22: XOR MM4 <- MM0 ; 1st check word 23: XOR MM4 <- MM1 24: XOR MM4 <- MM2 25: XOR MM5 <- MM1 ; 2nd check word 26: XOR MM5 <- MM2 27: XOR MM5 <- MM3 28: XOR MM6 <- MM0 ; 3rd check word 29: XOR MM6 <- MM1 30: XOR MM6 <- MM3 31: 32: ; Detect and correct errors:... ; Correct 1st..3rd word (omitted here) ; (Code is quite similar to 4th word s code) 53: ; Correct 4th word: 54: MOV eax <- MM4 ; Generate toggle mask 55: NOT eax 56: AND eax <- MM5 57: AND eax <- MM6 58: XOR MM3 <- eax ; Apply toggle mask to 4th word 59: MOVs [edi] <- MM3 ; Write to destination 60: 61: ; Loop four times using the loop counter 62: DEC CX ; Have all 4x4 words been read? 63: JNZ Inner_loop ; If not, loop through packet 64: 65: done: RET ; Return to caller Exercises 6 - Microprocessors Seite 2

Exercise 2: Pipelining No memory delay is assumed for this exercise. a. How many processor cycles are required to handle one packet? Let constants be

3 Exercise 2: Pipelining No memory delay is assumed for this exercise. a. How many processor cycles are required to handle one packet? Let constants be fetched like a memory word? b. How do you need to change the sequences to pipeline the instructions? The processor has one instance of IF, ID, MR, EX and MW units each. c. Draw a figure of the pipeline contents for the code of lines : MOVs MM4 <- [esi] ; Get 1st check word 18: MOVs MM5 <- [esi] ; Get 2nd check word 19: MOVs MM6 <- [esi] ; Get 3rd check word d. Register contents are required in ID and written after EX. What happens in lines 54-56? What could help? 54: MOV eax <- MM4 55: NOT eax 56: AND eax <- MM5 Exercises 6 - Microprocessors Seite 3

4 54: MOV eax <- MM4 55: NOT eax 56: AND eax <- MM5 e. What happens in lines 62-65? What could help? 62: DEC CX 63: JNZ Inner_loop 64: 65: done: RET OR 10: Inner_Loop: 11: 12: ; Read packet and check words from memory 13: MOVs MM0 <- [esi] ; Get 1st word and increment f. Suppose a 20% probability of a one-cycle stall. How many processor cycles are required for one packet now? g. What is the advantage and what is the drawback of a deep pipeline over a plain pipeline? Find a real life example for both. Exercises 6 - Microprocessors Seite 4

5 Intel CPU Microarchitectures (CISC) Source: RISC-V Microarchitecture (RISC) Sources: Exercises 6 - Microprocessors Seite 5

6 Exercises 6 - Microprocessors Seite 6

Exercise 3: Instruction Set Extension We now add two extra instructions to aid Hamming ECC: a. Make use of the two new instructions where possible. Change the program accordingly. b.

7 Exercise 3: Instruction Set Extension We now add two extra instructions to aid Hamming ECC: a. Make use of the two new instructions where possible. Change the program accordingly. b. How many clock cycles are required for each packet? c. Let s go crazy and implement the whole error correction into one instruction ECC0..ECC3 for each of the four words to be corrected. Change the program accordingly. d. How many clock cycles are required for each packet? Exercises 6 - Microprocessors Seite 7

8 Code 1: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 2: ; Subroutine: Correct New Packet with Extended Instruction Set; 3: ; Parameters: Packet Source address: esi ; 4: ; Destination address: edi ; 5: ; Registers: CX (16-bit), eax, MM0-MM6 (32-bit each) ; 6: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 7: 8: New_Packet: 9: MOV CX <- 4 ; Loop counter, a packet has 4x4 words 10: Inner_Loop: 11: 12: ; Read packet and check words from memory 13: MOVs MM0 <- [esi] ; Get 1st word and increment 14: MOVs MM1 <- [esi] ; source pointer 15: MOVs MM2 <- [esi] ; Get 3rd word 16: MOVs MM3 <- [esi] ; Get 4th word 17: MOVs MM4 <- [esi] ; Get 1st check word 18: MOVs MM5 <- [esi] ; Get 2nd check word 19: MOVs MM6 <- [esi] ; Get 3rd check word 20: 21: ; Re-construct parity bits 22: CCC MM4 <- MM0, MM1, MM2 23: CCC MM4 <- MM1, MM2, MM3 24: CCC MM4 <- MM0, MM1, MM3 25: 26: ; Detect and correct errors:... ; Correct 1st..3rd word (omitted here) ; (Code is quite similar to 4th word s code) 53: ; Correct 4th word: 54: ACC MM3 <- MM4', MM5, MM6 55: MOVs [edi] <- MM3 ; Write to destination 56: 57: ; Loop four times using the loop counter 58: DEC CX ; Have all 4x4 words been read? 59: JNZ Inner_loop ; If not, loop through packet 60: 61: done: RET ; Return to caller Exercises 6 - Microprocessors Seite 8

9 Code 1: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 2: ; Subroutine: Correct New Packet with Crazy Extended Instruction Set; 3: ; Parameters: Packet Source address: esi ; 4: ; Destination address: edi ; 5: ; Registers: CX (16-bit), eax, MM0-MM6 (32-bit each) ; 6: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 7: 8: New_Packet: 9: MOV CX <- 4 ; Loop counter, a packet has 4x4 words 10: Inner_Loop: 11: 12: ; Read packet and check words from memory 13: MOVs MM0 <- [esi] ; Get 1st word and increment 14: MOVs MM1 <- [esi] ; source pointer 15: MOVs MM2 <- [esi] ; Get 3rd word 16: MOVs MM3 <- [esi] ; Get 4th word 17: MOVs MM4 <- [esi] ; Get 1st check word 18: MOVs MM5 <- [esi] ; Get 2nd check word 19: MOVs MM6 <- [esi] ; Get 3rd check word 20:... 53: ; Re-construct parity bits, detect and correct errors 54: ECC3 [edi] 55: DEC CX ; Have all 4x4 words been read? 56: JNZ Inner_loop ; If not, loop through packet 57: 58: done: RET ; Return to caller Exercises 6 - Microprocessors Seite 9

10 Exercise 4: Cache Architecture II Someone wants to suggest that you use a general purpose 4 GHz Pathlium processor instead. It features two pipelines, each of which is capable of executing any instruction in one cycle. It also has the new instructions we constructed in Exercise 3c. It has plenty of data cache running at full processor speed. A data cache line holds 32 bytes which can be filled in one memory burst. The main memory (DDR-SDRAM) is connected to the cache with a bus speed of 200 MHz. The bus width is 32 -bits. The access pattern is 12-1 bus clock periods. a. What raw CPI does it achieve? Is it realistic? b. Why do you tell him to go away with that idea, although your platform only runs at 400 MHz? What is the CPI value for the program on the Pathlium? Exercises 6 - Microprocessors Seite 10

11 c. This problem was addressed with the introduction of a new processor command in the ISSE (Internet Stream instruction Set Extension) introduced in the PIII. Find the instruction in an Intel or AMD data book. Exercises 6 - Microprocessors Seite 11

INTEL Architectures GOPALAKRISHNAN IYER FALL 2009 ELEC : Computer Architecture and Design

INTEL Architectures GOPALAKRISHNAN IYER FALL 2009 GBI0001@AUBURN.EDU ELEC 6200-001: Computer Architecture and Design Silicon Technology Moore s law Moore's Law describes a long-term trend in the history