About the Instructor

Transcription

1 About the Instructor Kwang-Ting (Tim) Cheng PhD, 1988, Univ. of California, Berkeley : AT&T Bell Labs 1993-Present: Professor, Dept. of ECE, Univ. of California, Santa Barbara : Director, Computer Engineering Program, UCSB : Chair, Dept. of ECE, UCSB July-Dec. 2008: Visiting Professor, Univ. of Tokyo Research areas: VLSI test, validation and verification; multimedia computing (image and video content analysis) 1 2

2 UCSB s SoC Design and Test Lab Research directions: Test techniques for heterogeneous SOC Functional and timing verification Post-silicon debug and validation Current projects: Models and coverage metrics for effective post-silicon validation Low-cost on-line checking for consumer electronics Self-test and error resilience for high-speed IO and RF systems Test, yield and reliability analysis for multi-core systems with spares Design and test for flexible electronics 3 Class Website 4

3 5 Outline - Overview Overview of IC Testing Types of Testing at IC level IC Production Test Process Burn-in Board, System and Field Testing Costs of Testing The Testing Problems 6

4 Verification vs. Testing Verification Verifies correctness of design. Performed by simulation, hardware emulation, or formal methods. Performed once prior to manufacturing. Responsible for quality of design. *from M. Bushnell/V. Agrawal Testing Verifies correctness of manufactured hardware. Two-part process: 1. Test generation: software process executed once during design 2. Test application: electrical tests applied to hardware Test application performed on every manufactured device. Responsible for quality of devices. 7 Testing Process Is Never Perfect Based on analyzable fault models, which may not map on real defects. Incomplete coverage of modeled faults due to high complexity. Some good chips are rejected. The fraction (or percentage) of such chips is called the yield loss. Some bad chips pass tests. The fraction (or percentage) of bad chips among all passing chips is called the defect level. 8

5 Testing as Filter Process Good chips Prob(good) = y Fabricated chips Defective chips Prob(bad) = 1- y Prob(pass test) = high Prob(fail test) = low Prob(pass test) = low Prob(fail test) = high Mostly good chips Mostly bad chips Ack: Bushnell and Agrawal, Essential of Electronic Testing, Types of Testing Characterization testing, or design debug Verifies correctness of design & of test procedure data will be used for final spec. data can be used to identify area in which processing can be helped for increased yield test time is not important Manufacturing testing/production testing Factory testing of all manufactured chips for parametric faults and for random defects Ack: Bushnell and Agrawal, Essential of Electronic Testing,

6 Characterization Test Worst-case test Choose test that passes/fails chips Select statistically significant sample of chips Repeat test for every combination of 2+ environmental variables Plot results in Shmoo plot Diagnose and correct design errors Continue throughout production life of chips to improve design and process to increase yield Ack: Bushnell and Agrawal, Essential of Electronic Testing, Shmoo Plot 12

7 Types of Manufacturing Tests Wafer sort or probe test done before wafer is scribed and cut into chips Packaged device tests 13 Where Does Probe Fit In? Design Photomask Wafer Fabrication Wafer Test Package Final Test 14

8 Bad Die Inker Reservoir of ink Plunger or fish line dispenses one drop onto each bad die Plunger is electromagnetically or pneumatically driven 15 Inked Wafer 16

9 Typical Probe Test Cell Automatic Test Equipment Stimulus, Response Wafer Good/Bad Test Head Load Board Spring Assy Probe Card Prober X & Y Location 17 Probe Test Cell ATE Prober Interface Board Spring Contactor Assembly Probe Card Prober 18

10 Production IC Probe Floor 19 Probe Card Provides the primary electrical contact between the tester and each device-under-test (DUT) on the wafer Needles on the probe card contact the device I/O pads on the die (same pads are used for package interconnects; often called bond pads) There is usually a different, custom probe card for every circuit design The cards are delicate and fragile 20

11 Cantilever Needle, Epoxy Ring Probe Card Technology Printed Circuit Board (Probe Card) Needle Epoxy Ring Needle soldered to PCB 21 Cantilever Needle Card 22

12 Multi Level Cantilever Needles 23 Vertical Cards for Area Array Space Transform DUT Board Insulator DUT Board Vertical Needles WAFER IBM Buckling Beam Cobra, Patented in

13 Vertical Card (3500 Needles) 25 Where Does Final Test Fit In? Design Photomask Wafer Fabrication Wafer Test Package Final Test 26

14 Production Testing for Packaged Devices ContactTest To screen out assembly related failures. To insure that the tester interface is in contact with the device. Burn-In Test To screen out infant mortalities Functional Test DC Parametric Test Steady state tests AC Parametric Test To ensure that state changes occur at the right time 27 Why Do We Burn-In? Burn-in stress required to meet IM induces early wearout for die size >400 mils Source: Intel 28

15 Burn-in Testing Correlations have been made between life span at room temperature & life span at elevated temperature. Charts of these correlations have been made for each technology Put the device in a furnace for a certain length of time at an elevated temperature and voltage By applying high voltage to the IC s pins, burn-in accelerates the time-to-failure of oxide defects (weak oxide, pin holes, uneven layer growth, etc) typically found in MOS devices High temperature accelerates these and other defects, such as ionic contamination and silicon defects 29 An Example of IC Failure Rate vs. System Operating Time With and Without Burn-in 100,000 10,000 1, C burn-in No burn-in C burn-in Time (hr) 30

16 . Problem of Burn-In: Leakage Dominates Burn-In Power Thermal runaway A destructive positive feedback condition during BI Test sockets can be destroyed 31 Functional Testing for Digital Circuits Test Vectors Digital Circuit Circuit Response True Response Comparator Test Result 32

17 DC Parametric Testing Tests are done by Parametric Measurement Unit (PMU) Leakage test Threshold V il & V ih test Output drive current test Power consumption test Output short current test 33 AC Parametric Testing To ensure that value/state changes occur at the right time Some of AC parametric tests are mainly for characterization and may not be necessary for production test. Test for rise and fall times of an output signal Tests for setup and hold times Tests for time to tri-state Tests for measuring delay times» E.g. tests for memory access time Functional at-speed tests (speed sorting) 34

18 Mov00100.mpg 35 Board Level Testing Shorts testing In-circuit testing Check devices already mounted on a board An external tester applies patterns directly to the inputs of the device & observe the outputs The tester must be capable of electronically isolating the IC under test from the board environment Functional Board Testing 36

19 System Testing Final test in the manufacturing process Checking the right assembly of components such as boards, backplanes, cables and peripherals It also involves checking of component interactions and HW/SW functionality Very long test times required 37 Field Testing Necessary for commissioning and faultfinding the system as a whole in a fieldservice environment Both analog and digital test equipment is needed, issues of Portability Ease of use Range of functions 38

20 Testing Costs are Composed of: Test equipment costs Analog & digital signal and measuring instrumentation Test head (pin electronics, drivers and cables) Test controller (computer & storage) Test development costs Test planning, test program development and debugging Testing-time costs time using the equipment to support testing Test personnel costs training working time 39 Types of ATE IC Device ATE Memory, Logic, Mixed-signal, Analog Environmental Test - Burn-In Board-Level ATE Bare-Board Testers (Assembly Fault Testers) Manufacturing Defects Analyzers In-circuit Testers Functional Board Testers Combinational Board Testers Systems Testers Field Service Testers 40

21 Cost of Manufacturing Testing in 2000AD GHz, analog instruments, 1,024 digital pins: ATE purchase price = $1.2M + 1,024 x $3,000 = $4.272M Running cost (five-year linear depreciation) = Depreciation + Maintenance + Operation = $0.854M + $0.085M + $0.5M = $1.439M/year Test cost (24 hour ATE operation) = $1.439M/(365 x 24 x 3,600) = 4.5 cents/second 41 Tremendous Cost Pressure The price to performance ratio of semiconductors continues to decline $ per MIP or $ per bit follow Moore s Law Test equipment cost increases Tester cost increase 10 X in 30 years Prober cost increase 20 X in 30 years Test costs don t scale with geometry We must test all the individual parts We must test them more thoroughly And the parts get more complicated! 42

22 Summary Types of IC Testing Characterization testing vs. Production testing Production testing: Wafer probe vs. Packaged device testing Production testing for packaged devices: Contact test Burn-in Functional testing DC & AC parametric testing 43 Cost Of Testing - The Rule of Tens 1000 Cost Per Fault (Dollars) IC Test Board Test System Test Warranty Repair 44

23 In-Field Failures are Common and Costly Xbox:16.4% failure rate Additional warranty and refund will cost Microsoft $1.15B ($86 per $300-item) More than financial cost: reputation and market loss Non-trivial failure rate 15% in average failure-rates-worse-than-most-consumer-electornics.html 45 The Testing Problems Q1: Which faults to target? Fault Modeling Q2: How is test derived? Manually Automatic Test Pattern Generation (ATPG) Q3: How is test quality measured? Fault coverage vs. product quality Fault simulation Q4: How are tests applied? Test Engineering, Test programming Automatic test equipment (ATE) Wafer probe 46

24 The Testing Problems (Cont d) Q5: How to make sure high quality test can be derived and applied? Design for testability Built-in self-test Q6: How to identify the source of errors, if any? Fault Diagnosis 47