trend: embedded systems Composable Timing and Energy in CompSOC trend: multiple applications on one device problem: design time 3 composability

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1 Eindhoven University of Technology This research is supported by EU grants T-CTEST, Cobra and NL grant NEST. Parts of the platform were developed in COMCAS, Scalopes, TSA, NEVA, MESA. trend: embedded s phones, game consoles, cars, refrigerators, buildings,... interaction with physical world è real-time requirements Composable Timing and Energy in Kees Goossens & the team Kees Goossens <k.g.w.goossens@tue.nl> Group Electrical Engineering Faculty audio, video, graphics, games, artificial intelligence, internet,... different application domains have diverse requirements methodologies independent vendors use cases problem: design time s are complex time is short + money trend: multiple applications on one device it takes too long getting worse time start start design selling first profit end of life monolithic verification after integration, multiple applications circular verification who to blame for errors? goal & approach 4 reduce SOC design effort 5 virtual platform per application, time, energy budgets independent design, verification, and execution per application application as the unit of verification & re-use design, verify, execute in a virtual platform no interference when integrating or switching use cases è inter-dependent N x N x N x N è 4 independent N + N + N + N

2 Eindhoven University of Technology 6 & 7 time-division multiplex virtual platforms no interference, time, energy programming model, scheduling, power management per application for T use predictable schedulers, and associated real-time formalism FT radio virtual platform ST video virtual platform FT radio virtual platform ST video virtual platform intra-application scheduling & power management inter-application scheduling: hypervisor, TOS, inter-application scheduling 8 9 applications, tasks, transactions s,, memories SAM DAM SAM DAM 0 code & data fit in memories no cache NOC dependencies, etc. NOC is one resource P C S no task migration use for remote loads P C S task X X transaction over NOC transaction SAM DAM SAM DAM

3 Eindhoven University of Technology preemption scheduling interval, period time-division multiplexing (TDM) no interference between applications resources have different service units, periods cost of preemption GALS, DVFS small service units non-determinism application scheduling SAM DAM SAM DAM 4 5 on only separated scheduling & power management trusted inter-app untrusted -defined intra-app time, energy, and power budgets application application intra-application task scheduling application scheduling SAM DAM 6 7 application application application application CompOSe TOS CompOSe TOS CompOSe TOS CompOSe TOS tck PMU (controller) network on chip

4 Eindhoven University of Technology worst-case execution time of a request on the unshared resource WCET = fn(request,resource) compositional P C S model the application, resources, dependencies, binding,... WCET = fn(request,resource) SAM DAM SAM DAM 0 worst-case response time takes resource sharing into account WCT =~ WCET(t,r) * period / budget compositional WCT takes inter-app and intra-app resource sharing into account WCT =~ WCET(t,r) * app_period / app_budget * task_period / task_budget t WCT =~ WCET(t,r) * 4/ WCT =~ WCET(t,r) * 4/ * 4/ SAM DAM SAM DAM use the WCT of each actor cyclo-static dataflow scenario aware application CompOSe TOS application CompOSe TOS SAM DAM network on chip 4

5 Eindhoven University of Technology CompOSe TOS application application CompOSe TOS 00 buffer sizes & flow control latency-rate models of NOC, DAM application throughput = /MCM MCM=max. cycle mean task task NOC task 0 network on chip 6 7 application application CompOSe TOS CompOSe TOS buffer sizes & flow control latency-rate models of NOC, DAM application throughput = /MCM (controller) /O task task NOC DAM task network on chip design flow 8 tools, tools, tools,... 9 the SDF dataflow framework automatic generation of : s, NOC, controllers for cyclo-static dataflow applications configurations: actor-resource binding, buffer sizes, TOS scheduling interval, scheduler settings (TDM slots, CCSP priorities, etc.),... drivers: to run-time load the configurations on the end-to-end application throughput and latency analysis multi-fpga prototype Legend file Existing Tool Missing Tool Application flow NLP (C) Compaan/LIACS CSDF + C esource req. Analysis WCET Actor req. Code compilation Binary code Config data Mapping SDF Mapping flow Communication Architecture flow Hardware & arb. configuration (C) VHDL Hardware flow Compose make EMSOFT bootable tutorial Xilinx files Aenoclib Xilinxproj 9 5

6 Eindhoven University of Technology 6 salient points: & CompOSe TOS 0 salient points: & CompOSe TOS tracking of time, progress, energy, power, & slack fast DVFS, e.g. NXP [Pineda] or CEA/LETI [Vivet] constant scheduling interval tracking of time, progress, energy, power, & slack fast DVFS, e.g. NXP [Pineda] or CEA/LETI [Vivet] constant scheduling interval variation is removed variation is removed f max f WCET of OS f max f f IS + OS halt f interrupt ET program halt clock WCET interrupt ET f 0 WCET salient points: NOC salient points: Predator DAM controller global distributed scheduler (TDM) single pipelined resource fewer, smaller buffers one level of scheduling best cost : performance trade-off latency-rate dataflow model, incl. end-to-end flow control. predictable patterns. credit-controlled static priority (CCSP) decoupled latency & rate decoupled allocation granularity & latency no over-allocation CCSP scheduler pattern-based command generator salient points: Predator DAM controller 4 (current) limitations 5 predictable composable delay ET of responses to WCT WCT CCSP scheduler arrival time pattern-based command generator controller multiple use cases fully supported by NOC only supported programming models cyclo-static & variable-rate dataflow Kahn process networks data and code must fit in memories no caches, or else flush on preemption no I/O virtualisation no external interrupts interrupt reserved for TOS pre-emptive intra-application task scheduling prototyped no protection time, energy, and power budgets, but no budget DVFS simulated on FPGA 6

7 Eindhoven University of Technology 7 conclusions 6 the team 7 reduce SOC design effort independent design, verification, and execution per application application as the unit of verification & re-use application-specific scheduling & power management any mix of NT, ST, FT design flow (SDF, ) VHDL prototype used in teaching MSc embedded s lab Eindhoven university of technology Benny Akesson adu Stefan Sven Goossens Manil Dev Gomony Delft university of technology Anca Molnos Arnaldo Azevedo Karthik Chandrasekar Davit Mirzoyan Ashkan Beyranvand Nejad Andrew Nelson Pavel Zaykov in close collaboration with the dataflow research (SDF) at TU/e Sander Stuijk Martijn Koedam Marc Geilen and many others This research is supported by EU grants T-CTEST, Cobra and NL grant NEST. Parts of the platform were developed in COMCAS, Scalopes, TSA, NEVA, MESA. more information 8 end 9, in Multi System-on-Chip. Huebner (ed), Springer, 00 real-time NOC, DAC 0 Predator real-time DAM controller, DATE CompOSe TOS, MICPO composable power management, SAMOS SDF, DAC 06 Stuijk, et al. for further information Kees Goossens <k.g.w.goossens@tue.nl> Group Electrical Engineering Faculty abstract 40 This presentation will overview of the platform that enables multiple applications to be implemented, verified, and executed independently. Any mix of best-effort, soft and firm real-time applications can be integrated, without any interference between them. Composability holds for functional behaviour, but also for timing, energy, and power. Every application has its own time budget on s, network on chip, on-chip memories, and SDAM off-chip, enabling end-toend performance guarantees for real-time applications. Energy and power budgets per application on each allow each application to have its own (real-time) power manager, without causing interference. 7