The CompSOC Design Flow for Virtual Execution Platforms

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1 NEST COBRA CA104 The CompSOC Design Flow for Virtual Execution Platforms FPGAWorld Sven Goossens*, Benny Akesson*, Martijn Koedam*, Ashkan Beyranvand Nejad, Andrew Nelson, Kees Goossens* *

2 Introduction 2/23 Embedded system complexity is increasing Power budget is limited: Resource sharing Heterogeneous multiprocessor architectures Some applications on the system have real time requirements, others do not Mixed time criticality systems

3 Introduction: The Verification Problem 3/23 Without special measures: Resource sharing makes functional and timing behavior interdependent Verification effort grows exponentially with the number of applications Can only be done after integration (and may need to be repeated!) Non real time applications App 3 App 1 App 4 map SoC Core 1 Core 2 Real time applications App 2 App 5 Peripherals SDRAM Verification scenarios: Time = Use case switch App 1 App 2 App 3 App 4 App 3 App 5

4 Introduction: Virtual Execution Platforms 4/23 Isolation between applications to reduce the number of verification scenarios: Performance isolation (resource budgets): Predictable virtual platforms E.g.: you get 30/100 cycles Complete cycle level temporal isolation: Composable virtual platforms E.g.: you always get cycle 0 30 in every 100 cycles period, independent of other virtual platforms Virtual platform 1 Core SDRAM Core Applications run in their own virtual platform The physical SoC resources are designed to eliminate interference Allows independent application development and verification The CompSOC platform template demonstrates this design philosophy Physical SoC Core 1 Core 2 Peripherals SDRAM

5 Contributions 5/23 Overview of the CompSOC FPGA tool flow: 1. Hardware flow: High level platform description synthesized implementation 2. System software flow: Generates software stack, including micro kernel, resource managers, drivers, and virtual platform boot loader 3. Application flow: Maps data flow applications, generates virtual platform configuration Goal: Reduce design and verification effort reduce the time to market Integration of individual elements of CompSOC project

6 Outline 6/23 Introduction CompSOC Platform Template Hardware Flow System Software Flow Application Flow Example Conclusions

7 CompSOC Platform Components 7/23 CompSOC has a library of hardware and software components Software Processing Drivers runs on μblaze Timer / Interrupt (TIFU) S(D)RAM IMEM CMEM DMEM Resource managers (RM) uses connects to Composable Micro Kernel (CoMik) Communication DMA Adapters Mux / Demux Peripherals TFT UART Speaker Buttons Software stack Processor tile Communication core mapped peripheral

8 CompSOC Platform Template 8/23 Components are combined into a template, used to create instances Application 1 Application 2 RM CoMik RM CoMik Drivers SDRAM Peripheral Drivers Processor Tile 1 μblaze TIFU DMA SDRAM controller Peripheral controller Processor Tile n μblaze TIFU DMA Communication Core

9 Outline 9/23 Introduction CompSOC platform template Hardware Flow System Software Flow Application Flow Example Conclusions

10 High-level Input Files 10/23 Architecture Communication 5x processor Tile 2 x DMA + 4 kb SDRAM 5x processor Tile DMA 3x 4 x CMEM x 16 kb 128 kb IMEM TFT CMEM 2x 64 kb DMEM 3x2 mesh SDRAM 5x High level description of IPs: Dimensioning (i.e. 2 DMAs per tile) elements / sizes Their master/slave ports Protocol, data /address width Clock domains dimensions TFT 1x Fan in and fan out of ports Select Direct or based connection

11 Overview of Hardware Flow Tools Typical run time: Architecture Communication IP Expansion xml Add implicit components, default parameters and interfaces 11/23 < 1 min Communication Core Generation Completed Architecture Generate, (de) multiplexers, Protocol adapters, width converters, clock domain crossings HDL Instantiation Xilinx Project Generation Gather HDL code, create top level file, wrap in Xilinx PCore 3 hours Synthesize Platform Bitstream make Generate Xilinx platform description (MHS file) + constraints

12 Resulting Instance 12/23 No user input is required after the initial specification at the top of the flow* Tile Processor tile 1 DMEM IMEM CMEMIN CMEMIN Micro Blaze CMEMOUT CMEMIN TIFU DMA Clock generator... (...) SDRAM Processor tile n Reset assertion / synchronization reset SDRAM reset Multiple clock domains Communication core front end Arbiter front end CDC Width converter front-end Arbiter CDC Width converter front-end SDRAM back-end map Width converter front-end map TFT controller TFT peripheral Protocol adapter Run-time configurable * Note: this is a research tool, garbage in, garbage out applies to some extent

13 Outline 13/23 Introduction CompSOC platform template Hardware Flow System Software Flow Application Flow Example Conclusions

14 Flow Dependencies Hardware Flow System Software Flow 14/23 Architecture Communication CoMik Resource Man. + Drivers Boot Code Tile 1 IP Expansion Xilinx libgen Compile Communication Core Generation libxil rmlib Completed Architecture Compile HDL Instantiation ELF Tile 1 Xilinx Project Generation Hardware Specification Data2Mem Synthesize Platform Bitstream Bootable bitstream

15 Overview of System Software Flow 15/23 Hardware Specification Micro kernel: temporal isolation, stack / heap, tile HW API (timers, interrupts) CoMik Xilinx libgen libxil Resource Man. + Drivers Compile rmlib Compile ELF Tile 1 Completed Architecture Boot Code Tile 1 Which components exist (address map) Initial platform setup, virtual platform boot loader, system application Data2Mem Bitstream Bootable bitstream

16 Resource Managers Processor tile 1 DMEM CMEMIN front end IMEM Arbiter Micro Blaze CMEMIN CMEMOUT front end Bandwidth allocation > virtual memory resource Arbiter CDC TIFU DMA Width converter front-end... SDRAM back-end Processor tile n map CDC Width converter front-end TDM allocation > virtual processor map mapping Paths, TDM allocation Access granularity Run-time configurable Physical SoC Core 1 Core 2 SDRAM Virtual conn. 16/23

17 Outline 17/23 Introduction CompSOC platform template Hardware Flow System Software Flow Application Flow Example Conclusions

18 (Per-) Application Flow 18/23 Data flowbased design space exploration Entry point for other models of computation Find resource configuration satisfying the requirements Completed Architecture Application CSDF graph Mapping (SDF 3 ) Mapping & budget requirements Allocation VP Configuration Wrapper Generation Compile application bundle Annotated with real time requirements Connect actor functions to communication API Application source code Virtual Platform description + app. binary Application Bundle To SDRAM

19 Outline 19/23 Introduction CompSOC platform template Hardware Flow System Software Flow Application Flow Example Conclusions

20 Hardware Flow, 5-Tile Platform 20/23 Small example to demonstrate the output of the hardware flow: 5x processor Tile 2 x DMA + 4 kb 4 x CMEM x 16 kb 128 kb IMEM 64 kb DMEM Monitor Tile Architecture SDRAM TFT 3x2 mesh 128 kb MEM UART Communication 5x processor Tile DMA CMEM SDRAM TFT 1x 3x 2x 5x Tool flow 400 lines of XML 56k lines of C++ 42k lines of vhdl + verilog 3 hours (mostly synthesis)

5-Tile Platform 21/23 Virtex 6 LX240T FPGA ML605 Board Clock domain per tile 100 MHz SDRAM controller and TFT controller run at 150 MHz Utilization: 19 % registers 59 % LUTs 87

21 5-Tile Platform 21/23 Virtex 6 LX240T FPGA ML605 Board Clock domain per tile 100 MHz SDRAM controller and TFT controller run at 150 MHz Utilization: 19 % registers 59 % LUTs 87 % BRAMs Communication Core: 8 % registers 25 % LUTs (includes buffers) (Image generated using Xilinx PlanAhead tool) Placement is driven by the BRAM locations (horizontal stripes)

22 Conclusions 22/23 More functionality is integrated in single SoCs Resource sharing leads to behavioral / timing interdependence of applications Both temporal and behavioral Increases design and verification time, which increases time to market CompSOC tool flow reduces development and verification time by: Providing tools to the system designer: Hardware flow (high level description to synthesized design) System software flow (software stack) Application flow (mapping, code generation, virtual platform dimensioning) Based on CompSOC platform template, using virtual execution platforms: Enables verification in isolation Avoid re verification

23 23/23 For further information: Sven Goossens Benny Akesson Martijn Koedam Andrew Nelson Ashkan Beyranvand Kees Goossens Electronic Systems Group Electrical Engineering Faculty Eindhoven University of Technology Computer Engineering Group Faculty of Engineering, Mathematics and Computer Science Delft University of Technology

trend: embedded systems Composable Timing and Energy in CompSOC trend: multiple applications on one device problem: design time 3 composability

trend: embedded systems Composable Timing and Energy in CompSOC trend: multiple applications on one device problem: design time 3 composability Eindhoven University of Technology This research is supported by EU grants T-CTEST, Cobra and NL grant NEST. Parts of the platform were developed in COMCAS, Scalopes, TSA, NEVA,