Kees Goossens Electronic Systems TM 3218 PPMA TPBC T-PIC MBS AICP1 AICP2 VMPG VIP1 VIP2 MSP1 MSP2 MSP3 S S R W M S M S M S M S M S M S

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Alban Nicholson
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EJTAG FPBC -PIC DBG PBC GLOBAL IIC x CLOCK EET T_DBG BOOT P90 -Bridge -PI Bus F-PI Bus F-Gate DE PCI -Gate DA CAD UAT x UB 9 emory Controller C-Bridge PPA B AICP AICP VPG V V P P P T-Gate T 8 T-PI

nl> overview The Æthereal NOC after Ten Years Goals, Evolution, Lessons, and Future Æthereal NOC application domain concepts the hype curve past, present, future Kees Goossens <k.g.w.goossens@tue.

1 EJTAG FPBC -PIC DBG PBC GLOBAL IIC x CLOCK EET T_DBG BOOT P90 -Bridge -PI Bus F-PI Bus F-Gate DE PCI -Gate DA CAD UAT x UB 9 emory Controller C-Bridge PPA B AICP AICP VPG V V P P P T-Gate T 8 T-PI Bus TPBC T-PIC PDIO AIO AIO AIO I GPIO TDA <k.g.w.goossens@tue.nl> overview The Æthereal NOC after Ten Years Goals, Evolution, Lessons, and Future Æthereal NOC application domain concepts the hype curve past, present, future Kees Goossens <k.g.w.goossens@tue.nl> Electronic ystems Group Electronic ystems application domain & problem statement consumer electronics set-top boxes tethered, high-performance. physical back-end problems ("timing closure") # wires, length of wires, GAL. cost of designing real-time performance ("performance closure") integration of s, subsystems, software. logical scalability problems broadcast busses, central arbiters, DA bottleneck NB no low power Electronic ystems concepts for a real-time NOC. rate-controlled service: ango large output buffers, or circuit buffering (ango) as many virtual channels as virtual circuits. circuit switching: OCBU, olkotte,... no wire sharing D = TD with slot. FD circuit switching: optical NOCs photons are phast and hard to buffer: not pipelined. TD (virtual) circuit switching: aoc, Æthereal, Nostrum pipelined virtual circuit switching: use packets instead of data Electronic ystems concept of TD circuit switching big mistake NIs & s have common notion of time with global schedule global arbitration implemented with distributed local handshaking TD is not work conserving best effort traffic uses unallocated & unused capacity real-time performance is intuitive # allocated slots / total # slots implementations meso/a/synchronous no contention s are for free virtual-circuit buffers & state in NIs no arbitration, only synchronisation pipeline 0 cheap fast 0 utilisation is irrelevant performance : cost matters bits/sec : mm bits/sec : att BE and G only share the links wormhole low-priority BE has bad performance G has 0x better performance : cost ratio than G+BE Electronic ystems Electronic ystems

2 use cases & composability 6 use cases & composability 7 robustness no can break the system budgets use case combination of applications robustness use case composability the behaviour of an application is not affected by the presence or absence of other applications virtual platform per application Electronic ystems Electronic ystems cost of designing modular building s automated tool chain NOC generation NOC configuration performance verification simplified back end quicker to hardware (TL) quicker to software (drivers) quicker to correctness reduced time to market + 8 NOC, NOC, who's there? the application-level performance verification application, resources, mapping NOC, shared memories, processors, TO, DAs, DVF, at least half the total Ætherel effort was on the design flow 9 Kloc TL, 6 Kloc C++ Electronic ystems <k.g.w.goossens@tue.nl> Electronic ystems Group 0 Electronic ystems Electronic ystems

3 Electronic ystems Electronic ystems Electronic ystems Electronic ystems 00 so much more than a NOC programming & memory models low power virtualisation security 00 D / optical NOCs will save your business... really! 009 6, as we lived it Philips esearch team many PhD and c students 000 beyond concept for real-time NOC 7 Electronic ystems 00 so much more than a NOC programming & memory models low power virtualisation security Electronic ystems

GQ BQ application s topology selection mapping NOC hardware configuration NOC software validation verification simulation test chip / virtual tape out s main issues: 8 network interfaces pinning 9

lived it 00- venture capital explorations ''but how large is the market?" "will system integrators relinquish critical?" business model?

4 as we lived it 8, as we lived it hardware & rudimentary design flow output Aethereal hardware mousetrap FIFO two input control + state port words x bits words port Aethereal Aethereal NI GQ BQ application s topology selection mapping NOC hardware configuration NOC software validation verification simulation test chip / virtual tape out s main issues: 8 network interfaces pinning 9 traffic generators power delivery 6 off-chip ports full custom fifo & standard cell flow NI NI NI NI 0 NI6 0 0 NI NI0 A Electronic ystems results Electronic ystems, as we lived it 0, as we lived it 00- venture capital explorations ''but how large is the market?" "will system integrators relinquish critical?" business model? Philips Corporate esearch Exhibition "it'll save your business" Networks on chips Accelerating your platform Networks on chips At the heart of your platform Get to the market faster -00 Philips Consumer Electronics obile & Personal Automotive 006 Philips NXP Consumer electronics 008 spin-out obile & Personal division TEricsson 009 spin-out Home division Trident Electronic ystems Electronic ystems, as we lived it, unique selling points -00 Philips 006 Philips NXP 008 spin-out TEricsson 009 spin-out Trident 009 NXP's OC business Virage Logic from an NXP internal market to open rd party market vendor with significant OC integrator knowledge (ordered in time) "performance closure" (set-top box / digital TV) transparent multi-chip distributed shared memory (TV video pipes) layout, mesochronous, GAL (TB) multiple use-case switching (TB) simpler single interconnect (automotive, mobile) composability (automotive infotainment) integrated interconnect & memory controller(s) solution (TB) Electronic ystems Electronic ystems

<k.g.w.goossens@tue.nl>, the new new thing conclusions new technologies D, optical, wireless,... variability, reliability,.

5 the new new thing conclusions new technologies D, optical, wireless,... variability, reliability,... power efficiency Æthereal mature predictable & composable NOC CompOC virtual system per application use of NOCs programming models DA, CA, NI security debug adaptivity design flows, benchmarking many challenges ahead, especially for real-time systems it s been a bumpy ride along the hype curve real-time NOC challenges Electronic ystems Electronic ystems end 6 for further information Kees Goossens <k.g.w.goossens@tue.nl> Electronic ystems Group Electronic ystems

Networks on Chip. on-chip interconnect: physical. Kees Goossens. Kees Goossens Eindhoven University of Technology 1

Networks on Chip. on-chip interconnect: physical. Kees Goossens. Kees Goossens Eindhoven University of Technology 1 1 Networks on Chip Kees Goossens Kees Goossens Group Electrical Engineering Faculty on-chip interconnect: physical Kees Goossens