Department of Electrical and Computer Engineering, University of Maryland

Transcription

1 Department of Electrical and Computer Engineering, University of Maryland

2 OUTLINE Introduction: Problem statement Background Goals Co-processing units generation: Approach and baseline Multi-Dataflow Composer Template Interface Layer: hardware and automatic composition Performance assessment Use-case scenario Results Final remarks and future directions

3 OUTLINE: INTRODUCTION Introduction: Problem statement Background Goals Co-processing units generation: Approach and baseline Multi-Dataflow Composer Template Interface Layer: hardware and automatic composition Performance assessment Use-case scenario Results Final remarks and future directions

4 PROBLEM STATEMENT HIGH PERFORMANCES real time applications: Media players, video calling... UP-TO-DATE SOLUTIONS Support for the last audio/video codecs, file formats... MORE INTEGRATED FEATURES in mobile devices: MP3, Camera, Video, GPS... PORTABILITY LONG BATTERY LIFE Convenient form factor, affordable price...

5 PROBLEM STATEMENT HIGH PERFORMANCES real time applications: Media players, video calling... UP-TO-DATE SOLUTIONS Support for the last audio/video codecs, file formats... MORE INTEGRATED FEATURES in mobile devices: MP3, Camera, Video, GPS... PORTABILITY LONG BATTERY LIFE Convenient form factor, affordable price... DATAFLOW MODEL OF COMPUTATION Modularity and parallelism EASIER INTEGRATION AND FAVOURED RE-USABILITY COARSE-GRAINED RECONFIGURABILITY Flexibility and resource sharing MULTI-APPLICATION PORTABLE DEVICES

6 PROBLEM STATEMENT HIGH PERFORMANCES real time applications: Media players, video calling... UP-TO-DATE SOLUTIONS Support for the last audio/video codecs, file formats... Automated are fundamental to guarantee MP3, Camera, Video, GPS.... Dealing with systems, in particular for, state of the art still lacks in providing a broadly accepted solution. MORE INTEGRATED FEATURES in mobile devices: PORTABILITY LONG BATTERY LIFE Convenient form factor, affordable price... DATAFLOW MODEL OF COMPUTATION Modularity and parallelism EASIER INTEGRATION AND FAVOURED RE-USABILITY COARSE-GRAINED RECONFIGURABILITY Flexibility and resource sharing MULTI-APPLICATION PORTABLE DEVICES

7 Flexibility BACKGROUND: CG RECONFIGURABILITY High flexibility bit-level reconfiguration Slow and memory expensive configuration phase Medium flexibility word-level reconfiguration Fast configuration phase FG CG GPP DSP RP Bit-level Word-level Flexibility ASIC Performance Reconf. Speed Config. Storage

8 BACKGROUND: THE DATAFLOW MOC Directed graph of actors (functional units) Actors exchange tokens (data packets) through dedicated channels actions state Explicit the intrinsic application parallelism. Modularity favours model re-usability/adaptivity. I/O ports number I/O ports depth I/O ports burst of tokens

9 GOALS AND WORK EVOLUTION : automatic deployment of, by means of and strategies. High-level dataflow combination tool, front-end of the Multi-Dataflow Composer tool. Concrete definition of the hardware template and of the dataflow-based mapping strategy. Integration of the complete synthesis flow. Implementation of a coarse-grained multi-standard decoder.

10 Flexibility Technological target GPP DSP ASIP RECONF ASIC Performance

11 Flexibility Technological target GPP DSP ASIP RECONF ASIC Performance Reconfigurable Systems are suitable to cope with flexibility and efficiency. Specialized computing platforms, re-targetable for different functionalities.

12 Flexibility Technological target GPP DSP ASIP RECONF ASIC Performance Reconfigurable Systems are suitable to cope with flexibility and efficiency. Specialized computing platforms, re-targetable for different functionalities. High flexibility bit-level reconfiguration Slow and memory expensive configuration Applications with high control flow FG Bit level CG Word level Flexibility Reconf. Speed Medium flexibility word-level reconfiguration Config. Storage Fast configuration phase Applications with high level of instruction/data parallelism

13 What, Why and How WHAT: Automatic definition of efficient coarse-grained systems. WHY: Enable multi-context systems, saving both resources and power. HOW: Combining the dataflow model of computation and coarse-grained reconfigurable approaches. Implementing early-stage power management strategies.

14 Timeline of the Research Activities High-level dataflow combination tool, front-end of the Multi-Dataflow Composer tool. Concrete definition of the hardware template and of the dataflow-based mapping strategy. Integration of the complete high-level synthesis flow. Design Space Exploration extension. Low-power extension: clock gating support. Implementation of a coarse-grained multi-standard decoder. Co-processor generator: template definition. Low-power extension: power gating support. Co-processor generator: framework and drivers.

15 Reconfigurable Platform Composer Tool Project (L.R. 7/2007, CRP-18324) January 2012 December Co-Processor Generator Multi-Dataflow Composer (MDC) tool TIME TO MARKET SYSTEM COMPLEXITY Dynamic Power Manager Structural Profiler Baseline MDC Tool DESIGN AUTOMATION POWER MANAGEMENT

16 MDC: Basic Approach Dataflow Description Coarse Grained Hardware Platform 1:1

17 MDC: Basic Approach Dataflow Description Coarse Grained Hardware Platform 1:1 Dataflow Descriptions Coarse Grained Reconfigurable Hardware Platform 2:1 APPLICATION # KERNEL # ACTORS # SBOX zoom

18 front-end back-end MDC: Overview N:N N:1 HDL actors library CAL RVC-CAL specifications ORCC front-end IR back-ends multi dataflow Tab MDC HDL comm. protocol

19 front-end back-end MDC: Overview N:N N:1 HDL actors library CAL RVC-CAL specifications ORCC front-end IR back-ends multi dataflow Tab MDC HDL SBox D1 D2 S0 0 1 S1 0 1 S2 0 1 comm. protocol

20 front-end back-end MDC: Overview N:N N:1 HDL actors library CAL RVC-CAL specifications ORCC front-end IR back-ends multi dataflow Tab MDC HDL comm. protocol

21 Complete Synthesis: MDC+Turnus+Xronos front-end CAL RVC-CAL specifications ORCC front-end IR back-ends multi dataflow Tab MDC START: MDC composes the multi-dataflow network

22 Complete Synthesis: MDC+Turnus+Xronos front-end TRACES TURNUS Co- Exploration Framework WEIGHTS FIFO SIZES XRONOS High Level Synthesis HDL Components Library HW CG Reconfigurable Platform (with SBox queues/fanouts) CAL RVC-CAL specifications ORCC front-end IR back-ends multi dataflow Tab MDC STEP 2: Xronos, interacting with Turnus, generates the functional units to be instantiated

23 Complete Synthesis: MDC+Turnus+Xronos front-end back-end TRACES TURNUS Co- Exploration Framework WEIGHTS FIFO SIZES XRONOS High Level Synthesis HDL Components Library HW CG Reconfigurable Platform (with SBox queues/fanouts) CAL RVC-CAL specifications ORCC front-end IR back-ends multi dataflow MDC opt HW CG Reconfigurable Platform (without Sbox queues/fanouts) STEP 3: MDC generates the optimized reconfigurable hardware platform Tab

24 MDC settings LIST OF INPUT SPECIFICATIONS TICK TO GENERATE THE MULTI-DATAFLOW NETWORK TICK TO GENERATE THE MULTI-DATAFLOW HDL

25 Related Publications Publication on journals 1. Sau C, Meloni P, Raffo L, PALUMBO F., Bezati E, Casale-Brunet S, Mattavelli M (2015, In Press) Automated Design Flow for Multi-Functional Dataflow-Based Platforms. Jrnl of Signal Processing Systems 2. PALUMBO F., Carta N, Pani D, Meloni P, Raffo L (2014). The multi-dataflow composer tool: generation of on-the-fly reconfigurable platforms. Jrnl of Real-Time Image Processing Publication on conference proceedings and book chapters (indexed on Scopus) 1. Sau C, Raffo L, PALUMBO F, Bezati E, Casale-Brunet S, Mattavelli M (2014). Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case. XIVth Conf on Embedded Computer Systems: Architectures, Modeling, and Simulation 2. Nezan J, Siret N, Wipliez M, PALUMBO F, Raffo L (2012). Multi-Purpose Systems: A Novel Dataflow-Based Generation and Mapping Strategy. Symp on Circuits and Systems 3. PALUMBO F, Carta N, Raffo L (2011). The Multi-Dataflow Composer tool: a runtime reconfigurable platform composer. Conference on Design and Architectures for Signal and Image Processing 4. PALUMBO F, Pani D, Manca E, Raffo L, Mattavelli M, Roquier G (2010). RVC: a Multi-Decoder CAL Composer tool. Conference on Design and Architectures for Signal and Image Processing

26 Reconfigurable Platform Composer Tool Project (L.R. 7/2007, CRP-18324) January 2012 December Co-Processor Generator Multi-Dataflow Composer (MDC) tool TIME TO MARKET SYSTEM COMPLEXITY Dynamic Power Manager Structural Profiler Baseline MDC Tool DESIGN AUTOMATION POWER MANAGEMENT

27 Profiler and Power Manager A B C D E B F Do we always need to merge?

28 Profiler and Power Manager A B C D E B F E S0 B S1 F A C D Do we always need to merge?

29 Profiler and Power Manager B 3μW A 12μW D 8μW E B F 15μW 3μW 5μW = 52μW C 6μW E 15μW F 5μW S0 2μW B 3μW S1 2μW = 53μW A 12μW D 8μW C 6μW Do we always need to merge?

30 Profiler and Power Manager A B α β γ C D D B D B D Are there any preferable merging sequence?

31 Profiler and Power Manager A B α β γ C D D B D B D D A S0 B S1 S2 C αγβ D Are there any preferable merging sequence?

32 Profiler and Power Manager A B α β γ C D D B D B D D A S0 B S1 S2 C αγβ D longest chain 2 SBoxes Are there any preferable merging sequence?

33 Profiler and Power Manager A A B S0 C α β γ βαγ S4 B S5 C D D B D B D S1 D S2 D S3 S5 D A S0 B S1 S2 C αγβ D longest chain 2 SBoxes Are there any preferable merging sequence?

34 Profiler and Power Manager A A B S0 C α β γ βαγ S4 B S5 C D D B D B D S1 S2 D S3 D S5 longest chain 4 Sboxes D A S0 B S1 S2 C αγβ D longest chain 2 SBoxes Are there any preferable merging sequence?

35 Profiler and Power Manager A A B S0 C α β γ βαγ S4 B S5 C D D B D B D S1 S2 D S3 D S5 longest chain 4 Sboxes D A S0 B S1 S2 C αγβ D longest chain 2 SBoxes Are there any preferable merging sequence?

36 Profiler and Power Manager A B C D E B F Do we always need all the resources active?

37 Profiler and Power Manager A B C D E B F E S0 B S1 F A C D Do we always need all the resources active?

38 Profiler and Power Manager A B C D E B F E S0 B S1 F A C D Do we always need all the resources active?

39 Profiler and Power Manager A B C D E B F E S0 B S1 F A C D Do we always need all the resources active?

40 Profiler and Power Manager A B C D E B F E S0 B S1 F A C D Do we always need all the resources active?

41 Profiler and Power Manager A B C D E B F E S0 B S1 F A C D Do we always need all the resources active?

42 Profiler and Power Manager A B C D E B F E S0 B S1 F A C D Do we always need all the resources active?

43 Profiler and Power Manager MDC tool extensions: Topology Definer addresses the structural issues. Logic Region Definer addresses the dynamic one. TOPOLOGY DEFINER 1 2 LOGIC REGION DEFINER HDL

44 COMBINATIONS GENERATOR MDC TOOL LOW-LEVEL FEEDBACK ANALYSIS PARETO ANALYSIS Structural Flow TOPOLOGY DEFINER 1 2 LOGIC REGION DEFINER HDL DFG TIMING TOP.P DFG AREA TOP.F DFG POWER

45 COMBINATIONS GENERATOR Structural Flow TOPOLOGY DEFINER 1 2 LOGIC REGION DEFINER HDL α D D _ notmer D _ Mer D _ partmer N 2 N! 1 N! C N k 1 N! k 1 N, k! N 2 k 1 k! β γ

46 COMBINATIONS GENERATOR MDC TOOL Structural Flow TOPOLOGY DEFINER 1 2 LOGIC REGION DEFINER HDL DFG DFG DFG 13 networks

47 COMBINATIONS GENERATOR MDC TOOL LOW-LEVEL FEEDBACK ANALYSIS Structural Flow TOPOLOGY DEFINER 1 2 LOGIC REGION DEFINER HDL DFG TIMING DFG AREA DFG POWER DFG = <V,E> V = set of vertices, viєv E = set of edges, eiєe CP k => isolated critical path CP sbox CP static a i p i Area Power max f ( b)*ln( Ns) ( v i ( p i CP k g( b) Sbox1 x2 : f ( b) 0.268* b 59.85, g( b) 0.294* b Sbox2 x1 : f ( b) 0.114* b 87.70, g( b) 0.185* b ) A ) P i i a i p i CP max CP, CP static sbox

48 COMBINATIONS GENERATOR MDC TOOL LOW-LEVEL FEEDBACK ANALYSIS PARETO ANALYSIS Structural Flow TOPOLOGY DEFINER 1 2 LOGIC REGION DEFINER HDL DFG TIMING DFG AREA DFG POWER

49 COMBINATIONS GENERATOR MDC TOOL LOW-LEVEL FEEDBACK ANALYSIS PARETO ANALYSIS Structural Flow TOPOLOGY DEFINER 1 2 LOGIC REGION DEFINER HDL DFG TIMING TOP.P DFG AREA DFG POWER TOP.P: Fully Merged

50 COMBINATIONS GENERATOR MDC TOOL LOW-LEVEL FEEDBACK ANALYSIS PARETO ANALYSIS Structural Flow TOPOLOGY DEFINER 1 2 LOGIC REGION DEFINER HDL DFG TIMING TOP.P DFG AREA TOP.F DFG POWER TOP.F: Partially Merged

51 MDC settings LIST OF INPUT SPECIFICATIONS TICK TO ENABLE THE TOPOLOGY DEFINER. REQUESTED INPUT: Characterized library of components

52 Dynamic Flow TOPOLOGY DEFINER 1 2 LOGIC REGION DEFINER HDL TOP.P: Fully Merged COMPARE & SPLIT CGS = CLOCK GATED SET CHOSE TARGET AND IMPLEMENT

53 MDC settings LIST OF INPUT SPECIFICATIONS TICK TO ENABLE THE LOGIC REGION DEFINER. REQUESTED INPUT: Target technology + max number of cells available

54 Profiler and Power Manager: Results APPLICATION # KERNEL # ACTORS # SBOXES zoom ASIC 90 nm technology Cadence SoC Encounter FREQ OPTIMAL: 5 over 7 merged POWER OPTIMAL: all merged [MS: Merged Specifications] 70% APPLICATION z2p1 z2p1_so z3p2 z3p2_so Total Power [mw] 6,908 1,737 6,036 1,732 [z2p1: performance, Z3p1: power, *so: switch-off]

55 Related Publications Publication on journals 1. Sau C, Carta N, Raffo L, PALUMBO F. (2015, In Press) Early Stage Automatic Strategy for Power-Aware Signal Processing Systems Design. Jrnl of Signal Processing Systems 2. PALUMBO F., Sau C, Raffo L. (2014) Coarse-grained reconfiguration: dataflowbased power management. IET COMPUTERS & DIGITAL TECHNIQUES Publication on conference proceedings and book chapters (indexed on Scopus) 1. Fanni T, Sau C, Meloni P, Raffo L, PALUMBO F (2015, In Press) Power Modelling for Saving Strategies in Coarse-Grained Reconfigurable Systems. To be presented at the PhD Forum of the International Conference on ReConFigurable Computing and FPGA's 2. Fanni T, Sau C, Raffo L, PALUMBO F (2015, In Press) Automated power gating methodology for dataflow-based reconfigurable systems. ACM International Conference on Computing Frontiers 3. PALUMBO F, Sau C, Raffo L (2014) Power-awarness in coarse-grained reconfigurable designs: A dataflow based strategy. IEEE Work. on Signal Processing Systems 4. PALUMBO F, Sau C, Raffo L (2013). DSE and profiling of multi-context coarsegrained reconfigurable systems. Symp. on Image and Signal Processing and Analysis

56 Reconfigurable Platform Composer Tool Project (L.R. 7/2007, CRP-18324) January 2012 December Co-Processor Generator Multi-Dataflow Composer (MDC) tool TIME TO MARKET SYSTEM COMPLEXITY Dynamic Power Manager Structural Profiler Baseline MDC Tool DESIGN AUTOMATION POWER MANAGEMENT

57 Basic problem

58 Basic problem COARSE-GRAINED RECONFIGURABLE DATAPATH (automatically generated)

59 Basic problem COARSE-GRAINED RECONFIGURABLE DATAPATH (automatically generated)

60 Basic problem COARSE-GRAINED RECONFIGURABLE DATAPATH (automatically generated)

61 Basic problem AD-HOC FSM (manually generated) COARSE-GRAINED RECONFIGURABLE DATAPATH (automatically generated)

62 Basic problem HUGE AD-HOC EFFORT!!! FSM (manually generated) [1], [2] COARSE-GRAINED RECONFIGURABLE DATAPATH (automatically generated) [1] F. Palumbo, N. Carta, D. Pani, P. Meloni and L. Raffo, The multi-dataflow composer tool: generation of on-the-fly reconfigurable platforms, Journal of Real-Time Image Processing, vol. 9, no. 1, pp , [2] N. Carta, C. Sau, D. Pani, F. Palumbo and L. Raffo, A Coarse-Grained Reconfigurable Approach for Low-Power Spike Sorting Architectures, IEEE/EMBS Conference on Neural Engineering, 2013.

63 front-end back-end MDC Co-Processing Unit Generator TRACES TURNUS Co- Exploration Framework WEIGHTS FIFO SIZES XRONOS High Level Synthesis HDL Components Library front-end Reconfigurable Platform CAL RVC-CAL specifications ORCC IR back-ends multi dataflow MDC STEP 1: High level specification composition + Reconfigurable datapath generation

64 front-end back-end MDC Co-Processing Unit Generator TRACES TURNUS Co- Exploration Framework WEIGHTS FIFO SIZES XRONOS High Level Synthesis HDL Components Library front-end Reconfigurable Platform CAL RVC-CAL specifications ORCC IR back-ends multi dataflow MDC template TEMPLATE INTERFACE LAYER Drivers STEP 2: Coprocessor hardware-software specification

65 front-end back-end Coprocessor Deployment MDC Co-Processing Unit Generator TRACES TURNUS Co- Exploration Framework WEIGHTS FIFO SIZES XRONOS High Level Synthesis HDL Components Library IP front-end Reconfigurable Platform CAL RVC-CAL specifications ORCC IR back-ends multi dataflow MDC template Drivers TEMPLATE INTERFACE LAYER Drivers STEP 3: IP deployment

66 Template Interface Layer Memory-mapped loosely coupled coprocessor: accessible through the system bus as a memory-mapped IP; Stream-based tightly coupled coprocessor: accessible through different full duplex links, one for each I/O port. In both cases the Template Interface Layer: integrates a bank of configuration registers, to store the desired configuration; One (or more) front-end(s), to load data into the reconfigurable computing core; one (or more) back-end(s), to read the computed data from the reconfigurable computing core.

67 MDC settings LIST OF INPUT SPECIFICATIONS TICK TO ENABLE COPROCESSOR GENERATION. REQUESTED INPUT: TIL to be generated.

68 Related Publications Publication on conference proceedings and book chapters (indexed on Scopus) 1. Sau C, Fanni L, Meloni P, Raffo L, PALUMBO F (2015, In Press) Reconfigurable Coprocessors Synthesis in the MPEG-RVC Domain. To be presented at the International Conference on ReConFigurable Computing and FPGA's 2. Sau C, PALUMBO F (2014) Automatic Generation of Dataflow-Based Reconfigurable Co-processing Units. Conf on Design and Architectures for Signal and Image Processing

69 The MDC has been developed within the MPEG-RVC domain to automatically deploy flexible and adaptive reconfigurable platforms Co-Processor Generator TO DOs Power Gating Power Modelling TIME TO MARKET SYSTEM COMPLEXITY Dynamic Power Manager Structural Profiler Baseline MDC Tool Multi-Accelerator DESIGN AUTOMATION Dynamic Partial Reconfiguration POWER MANAGEMENT Partitioning

70 Opportunities Journal of Electrical and Computer Engineering Special Issue on Application-Driven Design of Parallel Embedded Systems Lead Guest Editor Paolo Meloni, Universita degli Studi di Cagliari, Cagliari, Italy Guest Editors Maxime Pelcat, INSA-Rennes, Rennes, France Francesca Palumbo, University of Sassari, Sassari, Italy 29 th January 2016

71 Opportunities LP-EMS16 2 nd Workshop on Design of Low Power Embedded Systems co-located ACM International Conference on Computing Frontiers Como (IT), May 2016 Workshop Organizers Francesca Palumbo, Università di Sassari, PolComIng, fpalumbo@uniss.it Maxime Pelcat, INSA de Rennes, IETR, maxime.pelcat@insa-rennes.fr Daniel Menard, INSA de Rennes, IETR, daniel.menard@insa-rennes.fr 2015 Program Committee (To be confirmed ) Jani Boutellier, University of Oulu Pekka Jääskeläinen, Tampere University of Technology (TUT) Eduardo Juarez, Universidad Politecnica de Madrid (UPM) Sebastien Lafond, Åbo Akademi University 1 st week Jean Francois Nezan, INSA Rennes, IETR laboratory of Fernando Pescador, Universidad Politecnica de Madrid (UPM) February Muhammad Shafique, Karlsruhe Institute of Technology (KIT)

72 Reconfigurable Platform Composer Tool Project (L.R. 7/2007, CRP-18324) January 2012 December